A Real-time Input Data Buffering Scheme Based on Time Synchronization for a T-DMB Software Baseband Receiver

A Real-time Input Data Buffering Scheme Based on Time Synchronization for a T-DMB Software Baseband Receiver Jeong Han Jeong, Moohong Lee, Byungjik Keum, Jungkeun Kim, Young Serk Shim, and Hwang Soo Lee MMPC and the School of EECS, KAIST Daejeon 305-701, Korea Abstract-To decode a broadcasting signal such as a T-DMB signal using a software baseband receiver running on a digital signal processor (DSP), real-time input data buffering is important. A time offset of each received frame, which is caused by a difference in the sampling frequency between the transmitter and the receiver, makes input buffer management difficult, eventually resulting in the performance deterioration of the receiver. This work proposes an input data buffering scheme based on a ring buffer for a T-DMB software baseband receiver running on a DSP. The time offset of each received frame is estimated by a time synchronization block using a phase reference symbol and is used by a buffer controller to control the ring buffer so that the receiver on the DSP always reads valid data for data decoding. The validity of the proposed scheme is confirmed by showing that the ring buffer never goes into an overflow state when buffering the input data with a time-varying time offset. Thus, the specified receiver performance is guaranteed over time. I. INTRODUCTION Various transmission systems such as Terrestrial Digital Multimedia Broadcasting (T-DMB), Terrestrial Integrated Services Digital Broadcasting (ISDB-T), and Digital Video Broadcasting Terrestrial (DVB-T) have been deployed in many countries around the world for mobile TV services. Among these systems, the T-DMB system [1] is based on the Eureka 147 Digital Audio Broadcasting (DAB) standard [2]. These systems use orthogonal frequency division multiplexing (OFDM) as their transmission technique because OFDM is considered to be strong in multipath fading channels [3]-[5]. As the performance of OFDMbased systems is sensitive to time and frequency synchronization at the receiver, many synchronization techniques have been researched [5]-[8]. Based on these synchronization techniques, diverse types of receivers in hardware and in software for DAB and T-DMB have been developed [5], [8]-[12]. If baseband functions such as synchronization, OFDM demodulation and channel decoding for DAB and T-DMB are implemented in software that runs on a DSP or many DSPs, the most urgent issue involves storing the real-time input data in a buffer placed directly after an analog-todigital converter (ADC) for the subsequent signal processing, such as the baseband functions by a DSP. 1 In this work, an input data buffering scheme is proposed based on a ring buffer for a T-DMB software baseband receiver. The time offset of each frame is estimated by a time synchronization block and used by a buffer controller to control the ring buffer so as to make the DSP read valid data for data decoding. An overview of a T-DMB software baseband receiver is briefly introduced in Section II. In Section III, an input data buffering scheme based on a ring buffer for a T-DMB software baseband receiver is proposed. Results that confirm the validity of the proposed scheme are presented in Section IV. Finally, conclusions are presented in Section V. II. OVERVIEW OF A T-DMB SOFTWARE BASEBAND RECEIVER When a software baseband receiver is implemented on a digital signal processor (DSP) to decode broadcasting signals such as T-DMB signal in real time, the DSP clock speed should be considerably faster than the ADC clock speed. However, due to this great difference in the clock speeds, the input digital data generated by the ADC at a lower speed should be stored in the buffer in advance. The DSP then reads the stored data at a faster speed to perform signal processing tasks such as time and frequency synchronization, OFDM demodulation, and channel decoding, as shown in Fig. 1. Therefore, real-time input data buffering is important when implementing a software baseband receiver on a DSP. The transmission frame of the T-DMB system is made up of a synchronization channel, a fast information channel (FIC) with three OFDM symbols, and a main service channel (MSC) with 72 OFDM symbols [1]-[2]. The synchronization channel is composed of a null symbol with no energy, which is slightly longer than the other symbols, and a phase reference symbol (PRS) that is used for synchronization in the receiver and as a phase reference for DQPSK modulation. This work was supported by the IT R&D program of MKE/IITA under Contract number 2005-S-609-04, which is the International Joint Project between Texas Instruments and KAIST in Korea. Figure 1. T-DMB software baseband receiver structure. 978-1-4244-2603-4/08/$25.00 2008 IEEE 214 ATNAC 2008

In a T-DMB software baseband receiver, it is efficient to buffer input data on a frame basis because the null symbol transmitted at the beginning of each frame can be used to distinguish each frame. On the other hand, if symbol-based buffering is used, every symbol should be tracked to distinguish between the null symbol and the other symbols due to different symbol lengths, resulting in complex buffer management. Frame-based buffering in a T-DMB software baseband receiver can be performed based on frame trigger pulses synchronized to the DSP clock. These pulses are generated at a set frame rate (one pulse per frame length of 96ms). Therefore, the DSP will read input data samples corresponding to a frame from the input buffer when a frame trigger pulse occurs and will perform the desired signal processing to decode the input data. Normally, the start of each received T-DMB frame continuously changes in one direction or the other direction due to the sampling clock difference between the transmitter and the receiver in the T-DMB system. Therefore, if a double buffer [13] is used to store the T-DMB input signal, management of the buffer becomes complex. The reason for this is as follows: if a double buffer that can hold a total of four frames of data with two frames on each element buffer is used, the start of the first received frame will be somewhere within an element buffer (BUF1) of the double buffer rather than at the beginning of that buffer. In addition, occasionally, the data of a received frame will span across two element buffers (BUF1 and BUF2) of a double buffer. As a result, when the DSP reads data from the double buffer, the address of the read pointer should jump around over the double buffer, leading to complex buffer management. On the other hand, a ring buffer [14]-[15] has a flexible structure that is able to read and write a data block with a changing start address and a variable length from and to the buffer, as the pointer of the ring buffer automatically goes back to the beginning of the buffer when it reaches the end of the buffer. Therefore, a ring buffer is used here to store real-time T-DMB input data. As a ring buffer is simultaneously accessed by a data writing device to write data and a data reading device to read data, with different clock speeds, it can fall into an underrun or overflow state. A common ring buffer management method to avoid an underrun or overflow state is based on Read/Write counts [16], as illustrated in Fig. 2. When the address of the ring buffer counterclockwise increases from the virtual start position marked by (A), the writable buffer space is between the WP and the RP and the readable buffer space is between the RP and the WP. When the data reading device is faster than the data writing device, the RP will approach the WP, as shown in Fig. 2 (a), eventually resulting in an underrun state (a state in which there is no data to read). To avoid this state, the data reading device checks before reading. If the distance between the WP and the RP becomes less than a specified value (here, the size of one element buffer), the data reading device stops reading data and waits for a time. On the other hand, if the data reading device is slower than the data writing device, the WP will approach the RP, resulting in an overflow state (a state in which there is no space to write), as depicted in Fig. 2 (b). Likewise, the data writing device checks the ring buffer state before writing and waits for a Figure 2. The WP and the RP on the ring buffer, (a) when the data reading device is faster, (b) when the data writing device is faster. time if there is not enough space to write. In this work, the following assumptions hold: a T-DMB software baseband receiver is implemented on a DSP chip. The incoming analog signal is transformed into digital data through an ADC and is stored in the ring buffer using an enhanced direct memory access (EDMA) controller [13], [16], which is an independent processor on the DSP chip. The ring buffer can store only eight data frames on eight elements buffers and the writing pointer WP is synchronized to the receiver s sampling clock. Initially, the distance between the WP and the RP is set to the size of two data frames, as an initial transmitted frame with an unknown frame start spans over two frames. The ADC clock and the DSP clock are assumed to be generated from a common reference clock. When the T-DMB input data with a time offset, which is caused by a difference in the sampling frequency between the transmitter and the receiver, is stored in a ring buffer, the start of each transmitted frame can change over time, as shown in Fig. 3. Therefore, the length of a frame to be processed in the receiver will become different compared to that of a transmitted frame. For example, as the T-DMB transmitter uses a sampling clock frequency f st of 2.048 MHz and because the length of a frame for transmission mode I is 96 ms, one frame is composed of 196,608 data samples. The space in the ring buffer between two marks (A) and (B), which accommodates a frame, can only hold 196,608 data samples that are generated by the ADC with the sampling frequency f sr. When the sampling clock frequency f sr of the receiver is larger than that of the transmitter f st (that is, f sr > f st ), more than 196,608 (that is, 196,608 + α; α is a time offset) data samples in the receiver are required to receive a transmitted frame, as depicted in Fig. 3 (a). The arrows around the ring buffer indicate the start positions of transmitted frames. Figure 3. The start positions of transmitted frames (a) when f sr > f st, (b) when f sr < f st. 215

On the other hand, when the sampling clock frequency f sr of the receiver is smaller than that of the transmitter f st (that is, f sr < f st ), less than 196,608 (that is, 196,608 - α) data samples in the receiver are required to receive a transmitted frame, as shown in Fig. 3 (b). Therefore, a proper method to manage a ring buffer that stores real-time input data with a time offset for post-signal processing is necessary to implement a T-DMB software baseband receiver on a DSP. III. THE PROPOSED INPUT DATA BUFFERING SCHEME In this work, an input data buffering scheme based on a ring buffer for a T-DMB software baseband receiver is proposed. The time offset of each frame is estimated by a time synchronization block using the PRS symbol and is used by a buffer controller to control the ring buffer so that the DSP reads valid data for data decoding. This process is illustrated in Fig. 4. In the beginning, the initial synchronization process is executed using the first two frames stored in the buffer. The initial synchronization process is composed of frame synchronization [5] for a rough estimation of the start of a frame, symbol synchronization [10] to determine the start of the PRS symbol, and frequency synchronization [6]-[7] to detect the frequency offset between local oscillators in the transmitter and the receiver. A tracking process is then performed for each succeeding frame. The tracking process includes symbol synchronization [5] to determine the time offset generated by the sampling frequency difference between the transmitter and the receiver, frequency synchronization to estimate the frequency offset between local oscillators in the transmitter and the receiver, and a Doppler effect caused by the motion of the receivers. In this work, the channel impulse response method [5] is used to estimate the time offset α for each frame in the tracking process. Considering that the time offset in the time domain is represented by a linear phase shift in the frequency domain, the received PRS symbol on the kth subcarrier Z r (k) can be expressed by Z ( k) = Z( k) e r j2 πkα/ N where Z(k) is the reference PRS symbol and N represents the IFFT size. Therefore, the time offset can be obtained from the following channel impulse response expression: * { r } (1) h( n) = IFFT Z ( k) Z ( k) = Aδ( n- α). (2) In (2), IFFT denotes the inverse fast Fourier transform and * indicates a complex conjugate operation. A is a constant and δ(n) is a delta function. The details of the proposed input data buffering scheme based on a ring buffer are given below. Using the frame start information found with the first two frames during the initial synchronization process, the buffer controller moves the read pointer RP to the next readable address on the ring buffer. The DSP reads input data corresponding to the PRS symbol of the third frame from the RP position on the ring buffer. After in-phase/quadrature-phase (IQ) demodulation and frequency synchronization and compensation are executed, the symbol synchronization block estimates the time offset of the third frame using the PRS symbol data and provides it to the buffer controller. The buffer controller moves the RP to a new address that is obtained by adding the estimated time offset to the current address of the RP. The DSP reads input data corresponding to the FIC and MSC symbols from the new address for the subsequent signal processing steps of IQ demodulation, frequency synchronization and compensation, OFDM demodulation, and channel decoding. After processing the third frame, the DSP waits for the next frame trigger pulse. For succeeding frames, the same operation used with buffer management and data decoding described above is performed. However, the ring buffer can fall into an underrun or overflow state due to the sampling clock difference between the transmitter and the receiver. When the sampling clock speed of the receiver is faster than that of the transmitter (that is, f sr > f st ), the RP slowly approaches the WP after many frames, which is depicted by the short dotted arrow pointing at the WP in Fig. 5 (a). While the RP remains at a point on an element buffer that is an element buffer away from the WP (between the two marks (A) and (B) in Fig. 5 (a)), the DSP will read valid data from the ring buffer. However, when the distance between the RP and the WP is less than one element buffer size, the DSP does not read data and waits for the next frame trigger pulse. Otherwise, the ring buffer eventually falls into an underrun state and the DSP will simultaneously read invalid data from the same memory space where the EDMA writes the ADC output data. As the sampling clock speed of the receiver is faster than that of the transmitter, the skipping of one frame trigger pulse does not cause any problem when decoding real-time broadcasting data. (a) (b) Figure 4. The proposed input data buffering scheme based on a time offset provided by a time synchronization block. Figure 5. The usage of the ring buffer in the proposed input data buffering scheme: (a) the sampling clock speed of the receiver is faster than that of the transmitter, (b) the sampling clock speed of the transmitter is faster than that of the receiver. 216

When the sampling clock speed of the receiver is lower than that of the transmitter (that is, f sr < f st ), the RP slowly fall behind against the WP, as marked by the short dotted arrow pointing downward in Fig. 5 (b). While the RP remains at a point on an element buffer that is two element buffers away from the WP (between the two marks (A) and (H) in Fig. 5 (b)), the DSP will read valid data from the ring buffer. However, when the distance between the WP and the RP becomes larger than the size of three element buffers, the DSP will read two frames of data in a row and will decode them. Otherwise, the ring buffer eventually falls into an overflow state and the EDMA will not have sufficient space to write the ADC output data. After decoding of two consecutive frames, the RP will remain at a point on an element buffer that is one element buffer away from the WP. Therefore, the DSP will read valid data until the distance between the WP and the RP again is slightly larger than the size of three element buffers. There can be several methods to make the DSP process two frames in a row depending on the DSP clock speed and other workload to be processed within one frame trigger pulse period. In this work, a method based on an advanced scheduling technique is proposed under the condition that the DSP uses a portion of the frame trigger pulse period to decode the input data of a frame in the normal state. When the DSP meets the condition that requires that two frames are decoded during one frame trigger pulse, the DSP is made to perform data decoding according to a new schedule. The new decoding schedule makes the DSP process more than one frame (for example, 1.3 times per frame) instead of only one frame per frame trigger pulse. This operation will continue for a specified period of time. After this specified period of time, each frame per frame trigger pulse will again be decoded according to the normal schedule. To perform data decoding based on a new schedule, different periods of a frame trigger pulse in addition to the normal period (a frame trigger pulse per frame) can be used. IV. PERFORMANCE VERIFICATION To confirm the validity of the proposed input data buffering scheme, a simple software baseband receiver running on a DSP processor with a clock speed of 567 MHz was implemented on a commercial DaVinci board. The simple software baseband receiver has a ring buffer and several baseband functions including synchronization, as shown in Fig. 4. A commercial tuner was used to receive a T-DMB signal that is generated by a commercial T-DMB generator. A simple ADC board with a reference oscillator to generate a sampling clock frequency (2.048 MHz) was built and used to connect the tuner and the DaVinci board. Through measurements, it was found that the sampling clock speed of the T-DMB signal generator is slightly faster than that of the ADC board (about 67Hz). A T-DMB video signal with a rate of 512 kbps in transmission mode I was used. When the proposed input data buffering scheme was not applied to the ring buffer, the distance variation between the WP and the RP on the ring buffer over time was plotted, as shown in Fig. 6. As expected, the distance between the WP and the RP continues to increase over time because the sampling clock speed of the T-DMB signal generator is faster than that of the receiver. When the proposed input data buffering scheme was applied to the ring buffer, the distance between the WP and the RP stayed within a given range with an expected periodic pattern. To implement the proposed input data buffering scheme efficiently, two frame trigger pulses were used instead of one frame trigger pulse per frame. As a result, the RP always moved over an element buffer that was one element buffer away from the WP. This confirms that while the RP falls behind the WP due to the sampling clock difference between the transmitter and the receiver, the ring buffer based on the proposed scheme never goes into an overflow state. Additionally, the RP will read valid data continually. A computer simulation was also performed to check the effect of the time offset of each received frame on the biterror rate (BER) performance of the baseband software receiver. The simulation conditions were as follows: the number of frames used in the simulation was 100. The transmission mode was mode I, the FFT size was 2,048, the frequency offset was zero, an AWGN channel was used, and the BER was measured after the channel decoder. In addition, it was assumed that the sampling clock speed of the transmitter was faster than that of the receiver. The BER performance of the baseband software receiver with time offsets of 20 samples, 35 samples, and 50 samples, which was implemented on a computer, is plotted in Fig. 7. In these cases, the ring buffer was managed by a common method based on Read/Write counts [16]. As expected, as the time offset increases, the BER performance deteriorates, as these time offsets caused inter-symbol interference when the fast Fourier transform (FFT) was performed for OFDM demodulation. When the proposed input buffering scheme was applied to the ring buffer, the BER performance was feasible because there was no time offset, as shown in Fig. 7 (no delay case). This simulation result shows that if the ring buffer in a baseband software receiver is not properly managed, the performance of the receiver will deteriorate according to the time offset of each received frame. WP - RP (in data samples) 7 6 5 4 3 2 1 x 10 5 conventional proposed 0 0 10 20 30 40 50 60 70 80 90 100 time (min) Figure 6. Distance variation between the WP and the RP on the ring buffer over time when the proposed input data buffering scheme was applied or when it was not applied. 217

BER 10 0 10-1 10-2 10-3 10-4 No delay(proposed scheme) 20 samples delay 35 samples delay 50 samples delay 3 3.5 4 4.5 5 5.5 6 6.5 7 CNR (db) Figure 7. Simulated bit-error rate performance of a software baseband receiver with various time offsets. V. CONCLUSION An input data buffering scheme based on a ring buffer for a T-DMB software baseband receiver running a DSP is proposed in this study. The buffer controller uses the time offset of each received frame, as estimated by a time synchronization block using a phase reference symbol in the received frame, to control the ring buffer. As the proposed ring buffer management scheme holds the distance between the read pointer and the writer pointer on the ring buffer within a given range, the receiver on a DSP always reads valid data for data decoding and the specified bit-error rate performance of the receiver is guaranteed over time. REFERENCES [1] Telecommunications Technology Association in Korea, Digital Multimedia Broadcasting, 2003SG05.02-046, 2003. [2] European Telecommunication Standard, Digital audio broadcasting (DAB) to mobile, portable, and fixed receivers, ETS 300 401, Feb. 1995. [3] S. B. Weinstein and P. M. Ebert, Data transmission by frequencydivision multiplexing using the discrete fourier transform, IEEE Trans. Communications, vol. 19, pp. 628-634, Oct. 1971. [4] J. A. C. Bingham, Multicarrier modulation for data transmission: An idea whose time has come, IEEE Comm. Mag., pp. 5-14, May. 1990. [5] K. Taura et al, A digital audio broadcasting (DAB) receiver, IEEE Trans. Consumer Electronics, vol. 42, pp. 322-326, Aug. 1996. [6] P. H. Moose, A technique for orthogonal frequency division multiplexing frequency offset correction, IEEE Trans. Communications, vol. 42, Oct. 1994. [7] K. Bang et al, A coarse frequency offset estimation in on OFDM system using the concept of the coherence phase bandwidth, IEEE Trans. Communications, vol. 49, pp. 1320-1324, Aug. 2001. [8] J. Cho et al, PC-based receiver for Eureka-147 digital audio broadcasting, IEEE Trans. Broadcasting, vol. 47, pp. 95-102, June 2001. [9] K.-T. Lee, Y.-S. Park, S.-H. Park, J.-H. paik and J.-S. Seo Development of portable T-DMB receiver for data services, IEEE Trans. Consumer Electronics, vol. 53, pp. 17-22, Feb. 2007. [10] Victor H. S. Ha, S.-K. Choi, J.-G Jeon, G.-H. Lee and W.-S. Shim Portable receivers for digital multimedia broadcasting, IEEE Trans. Consumer Electronics, vol. 50, pp. 666-673, May 2004. [11] H. Usuba, S. Kakiuchi and K. Yamauchi A prototype dab receiver, IEEE Int. Conf. Consumer Electronics, June 1996. [12] M. Miranda, C. Ghez, E. Brockmeyer, P. Op De Beeck and F. Catthoor Data transfer and storage exploration for real-time implementation of digital audio broadcast receiver on a trimedia processor, IEEE SBCCI, Sep. 2002, pp. 373-378. [13] Texas Instruments, C6000 Integration Workshop Guide, Rev. 3.1a, Aug. 2005. [14] N. Kehtarnavaz, Real-time digital signal processing based on the TMS320C6000, Elsevier, 2005, pp. 185-200. [15] S. W. Smith, The scientist and engineer s guide to digital signal processing, California Technical, 1997, pp. 506-509. [16] Texas Instruments, TMS320DM644x DMSoC enhanced direct memory access (EDMA) controller user s guide, Rev. D, Feb. 2008. 218