CH7023/CH7024 TV ENCODER PROGRAMMING GUIDE

Chrontel CH7023/CH7024 TV ENCODER PROGRAMMING GUIDE Information presented in this document is relevant to Chrontel driver module software, and Chrontel TV-Out chipset products. It may be only used for Chrontel software development aid. It may not be used for any other purpose. Chrontel and author of this document are not liable for misuse of information contained herein. Chrontel and author of document are not liable for errors found herein. Information contained herein may not be used within life support systems or nuclear facility applications without the specific written consent of Chrontel. Do not distribute this document to nondesignated unauthorized parties in any form without the specific written consent of Chrontel. Do not read and destroy this document if you are not designated recipient. Information contained herein is subject to change with or without notice. Communicate with Chrontel Software and Systems Engineering Department for up-to-date changes. Revision 1.4 May 12, 2006 Prepared By : Li Feng & Pu Yang Reviewed By: Eric Tzou Rev 1.4 05/12/2006 1

Table of Contents Chip Identification.. 3 System Configuration 3 Sync Control.. 3 Clock Setting.........4 DAC Setting...5 Using Utility.. 7 Sub-carrier Generation...20 Timing..21 Input Timing....21 Input Data Format..23 Scaling. 24 Video Output Format...25 Power Management & Connection Detection...26 Power Management...26 Connection Detection.26 Feature....28 Control Registers...28 Position....29 Bandwidth Control and TV Filter........30 Programming Sequence....32 Appendix A Programming IDF = 5(YCbCr 4:2:2).........33 Appendix B Test Mode..........35 Revision History...36 Rev 1.4 05/12/2006 2

CHIP IDENTIFICATION The CH7023/4 is a device targeting handheld and similar systems which accepts a digital input signal, and encodes and transmits data through 10-bit DACs. The device is able to encode the video signals and generate synchronization signals for NTSC and PAL standards. The device accepts different data formats including RGB and YCrCb (e.g. RGB565, RGB666, RGB888, ITU656 like YCrCb, etc.). The only difference from CH7023 and CH7024 is CH7023 has Macrovision copy protection capability and CH7024 does not. Following the steps below to identify CH7023/CH7024 chip. Step 1: Read the value of register 0x00; If value is 0x45, CH7023/CH7024 is present. Other value, none of CH7023/CH7024 is present; Step 2: Write 1 to bit 1 of register 0x40(set 0x40[1]=1) and read back; If the bit is 0, the chip present is CH7024; Else the bit is 1, the chip present is CH7023. Note: Individual bit(s) of a register is enclosed by square brackets. For example, bit 1 of register 0x40 is written as 0x40[1], and 0x40[1:0] means bits 1 and 0 of register 0x40. SYSTEM CONFIGURATION SYNC Control Register 0Eh should be configured to control sync information. Address: 0Eh SYMBOL: DES HPO VPO SYO DEFAULT 0 0 0 0 1 1 0 0 DES DES (0x0E[6]) defines the input sync type. When DES is 1, input sync is encoded inside the input data; when DES is 0, input sync is independent with input data. This bit should be set when the source is YCbCr 4:2:2. HPO, VPO HPO(0x0E[3] ) defines the polarity of horizontal sync. When HPO is 1, the polarity is positive; otherwise is negative. VPO(0x0E[2] ) defines the polarity of vertical sync. When VPO is 1, the polarity is positive; otherwise is negative. Rev 1.4 05/12/2006 3

SYO SYO (0x0E[1]) defines the direction of sync. When SYO is 0, input sync; otherwise output sync. CLOCK SETTING POUTEN Register 0x0E bit 7 is indictor for master and slave mode selection. Address: 0Eh SYMBOL: POUTEN DEFAULT 0 0 0 0 1 1 0 0 POUTEN(0x0E[7]) enables the master mode PCLK output through POUT pin. When POUTEN is set the chip works on master mode otherwise on slave mode. On master mode the user should provide the value of POUT frequency to calculate the values of PLL1N1, PLL2N2 and A(See PLL Setting). XCH Address: 0Fh SYMBOL: XCH DEFAULT 0 0 0 0 0 0 0 0 XCH (bit 7) is an auxiliary bit to help latch input data correctly. When MULTI is 1 or IDF equal 5, this bit should be 1, otherwise should be 0. Crystal Register Address: 0Bh SYMBOL: XTALSEL Reserved Reserved Reserved XTAL[3] XTAL[2] XTAL[1] XTAL[0] DEFAULT 0 0 0 0 0 1 0 0 XTALSEL (0x0B[7] ): whether the crystal frequency is predefined or not. When the crystal frequency is predefined, some registers, such as SCFREQ, will be calculated inside the chip to save programming effort. Rev 1.4 05/12/2006 4

0: Using predefined value. 1: Using other value. When XTALSEL set to predefined value, XTAL[3:0] ( bits 3-0 ) have to program follow by the table below: 0: 3.6864MHz, 1: 3.579545MHz, 2: 4MHz, 3: 12MHz, 4: 13MHz, 5: 13.5MHz, 6: 14.318MHz, 7: 14.7456MHz, 8: 16MHz, 9: 18.432MHz, 10: 20MHz, 11: 26MHz, 12: 27MHz, 13: 32MHz, 14: 40MHz, 15: 49MHz. DAC SETTING DUCVBS SYMBOL: DUCVBS Address: 0Ch DEFAULT 0 0 0 0 0 0 0 0 DUCVBS (bit 7) indicates whether dual CVBS outputs are enabled. 0: Outputs are not dual CVBS. 1: outputs are dual CVBS, and meanwhile, the SVD/DDAC (bit 6 of 0Ah) should be set to 1, and DACSW[1:0] (0Ah[5:4]) should be set to 10. Rev 1.4 05/12/2006 5

SEL_R Address: BIT: SYMBOL SEL_R DEFAUL 1 1 0 0 0 0 0 0 63h SEL_R (bit1) indicates the termination of the DAC. 0: Single termination (no 75ohm on PCB) 1: Double termination (both 75 ohm on PCB and TV side) Rev 1.4 05/12/2006 6

USING UTILITY The Register Table utility is created to help software engineer program PLL1N1, PLL2N2, PLL3N3, PLL3N4, PLL3N5, A, P, T, N, SCFREQ, HTI and VTI registers of CH7023/CH7024. The following section explains how to use Register Table utility step by step. Run the utility Setting Wizard and the popup dialog box is as figure A. Figure A Select Run Register Table Setting, and the Register Table Setting is opened. Figure B Rev 1.4 05/12/2006 7

How to calculate There are six steps to complete the calculation as reference page number indicated below: Step 1 Program System configuration registers: Page 7 Step 2 Program PLL1N1, PLL2N2, PLL3N3,PLL3N4,PLL3N5 and A registers: Page 8. Step 3 Decide H-Total and V-Total: Page 10 Step 4 Program P, N and T dividers registers: Page 11 Step 5 Program SCFREQ Sub-Carrier registers: Page 14 Step 6 Program Input timing registers: Page 16 Step 1: input followings to calculate register values(figure C) o XCH: When checked(xch = 1) XCH button the user should selects the ratio between pixel clock and X clock by using of Dual Edge or Single Edge check button. For IDF = 0, 1, 2,3,4, 6 r4 = r3 when XCH = 0; r4 = 2* r3 when XCH = 1 and data is latched by double edges; For IDF=5, please refer to appendix A for details. o MULTI: MULTI indicates the multiplexed input data. When Multi is set and select single edge X clock is twice of pixel clock. Please refer to Section 2.2.4 for details. o DOTCRB: Check this control to enable TV Dot Crawl reduction (DOTCRB = 1); uncheck this control to disable TV Dot Crawl reduction (DOTCRB = 0). o Master or Slave: Check this control to indicator for master and slave mode. When working on slave mode the utility can t calculate the values of R1,R2 and A. o FSCI: Indicate how the CH7023/CH7024 generate sub_carrier frequency. If the control is checked the CH7023/CH7024 generates sub_carrier frequency through crystal frequency. If unchecked the CH7023/CH7024 generate sub_carrier frequency through UCLK frequency. o Crystal: CH7023/CH7024 has 16 predefined crystal frequencies internally. If using value other than predefined, please input the crystal frequency values to Edit Control Box. o TV_Format: Choose Video Output Format. o UCLK Tolerance: Defines the allowable deviation of real UCLK from the standard UCLK (27MHz); default tolerance is 0.01%. o XCLK : Equals pixel clock or twice pixel clock. See XCH. Rev 1.4 05/12/2006 8

o Pout CLK: When work on master mode CH7023/CH7024 output as reference clock. o HAI,VAI: Define input horizontal active pixel and vertical active pixel. Figure C Step 2: After filled up the required information on step1. Click on Input button, all supported modes should be listed out on list box as well as PLL1N1, PLL2N2, PLL3N3, PLL3N4, PLL3N5 and A settings. PLL1N1, PLL2N2, PLL3N3, PLL3N4, PLL3N5 decide the values of r1, r2, r3, r4 and r5 separately. Write the calculated settings into following registers. Rev 1.4 05/12/2006 9

PLL1N1, PLL2N2, PLL3N3, PLL3N4 and PLL3N5 Address: 2Fh BIT: SYMBOL: Reserved Reserved PLL2N2[2] PLL2N2[1] PLL2N2[0] PLL1N1[2] PLL1N1[1] PLL1N1[0] DEFAULT 0 0 0 1 0 0 1 0 Address: 30h BIT: SYMBOL: Reserved Reserved PLL3N4[2 PLL3N4[1] PLL3N4[0] PLL3N3[2] PLL3N3[1] PLL3N3[0] ] DEFAULT 0 0 0 0 1 0 0 1 Address: 31h BIT: SYMBOL: Reserved Reserved Reserved Reserved Reserved PLL3N5[2] PLL3N5[1] PLL3N5[0] DEFAULT 0 0 0 1 0 1 0 0 A Registers A defines the clock divider for PCLK. These values only work when master mode is selected. Address: 24h SYMBOL: A[31] A[30] A[29] A[28] A[27] A[26] A[25] A[24] DEFAULT 0 0 0 0 0 1 0 0 Address: 25h SYMBOL: A[23] A[22] A[21] A[20] A[19] A[18] A[17] A[16] DEFAULT 0 0 0 0 0 0 0 0 Address: 26h SYMBOL: A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] Rev 1.4 05/12/2006 10

DEFAULT 0 0 0 0 0 0 0 0 Address: 27h SYMBOL: A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] DEFAULT 0 0 0 0 0 0 0 0 Rev 1.4 05/12/2006 11

Figure D Step 3: Double click the mode selected then the new dialog (Figure D) will pop up to confirm the selection. Click OK button on the new dialog and P, N and T clock dividers setting will be generated (Figure E). Rev 1.4 05/12/2006 12

Figure E Step 4: After getting the values of P, N and T fill calculated settings into following registers. P The values of M and N are the coefficient to generate UCLK from XCLK. Address: 28h SYMBOL: P[23] P[22] P[21] P[20] P[19] P[18] P[17] P[16] DEFAULT 0 0 0 0 0 0 1 1 Rev 1.4 05/12/2006 13

Address: 29h SYMBOL: P[15] P[14] P[13] P[12] P[11] P[10] P[9] P[8] DEFAULT 1 0 0 0 1 1 1 1 Address: 2Ah SYMBOL: P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] DEFAULT 0 1 1 1 1 0 0 0 N Address: 2Bh SYMBOL: N[23] N[22] N[21] N[20] N[19] N[18] N[17] N[16] DEFAULT 0 0 0 0 0 1 0 0 Address: 2Ch SYMBOL: N[15] N[14] N[13] N[12] N[11] N[10] N[9] N[8] DEFAULT 1 0 0 1 0 1 0 1 Address: SYMBOL: N[7] N[6] N[5] N[4] N[3] N[2] N[1] N[0] DEFAULT 0 0 0 0 1 1 0 0 2Dh T Address: 2Eh BIT: SYMBOL: T[7] T[6] T[5] T[4] T[3] T[2] T[1] T[0] DEFAULT 0 0 1 1 0 1 1 0 Rev 1.4 05/12/2006 14

Figure F Step 5: Write SCFREQ from registers 0x34 to 0x37 when ACIV bit (0x1C[4]) is set to 1. Please refer to section of Sub-carrier generation for more detail. Rev 1.4 05/12/2006 15

Address: 34h BIT: SYMBOL Reserved Reserved Reserved Reserved Reserved SCFREQ[ SCFREQ[ SCFREQ[ : 26] 25] 24] DEFAUL 0 0 0 0 0 0 0 1 Address: 35h BIT: SYMBOL SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ : 23] 22] 21] 20] 19] 18] 17] 16] DEFAUL 0 0 0 1 1 0 0 1 Address: 36h BIT: SYMBOL SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ : 15] 14] 13] 12] 11] 10] 9] 8] DEFAUL 1 1 1 1 0 1 0 1 Address: 37h BIT: SYMBOL SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ SCFREQ[ DEFAUL 0 0 1 1 1 1 1 1 SCFREQ[26:0], the Sub-carrier Frequency Value. Rev 1.4 05/12/2006 16

Figure G Step 6: Fill the input timing settings (Horizontal/Vertical Total and Horizontal/Vertical Active) into following registers. HAI Address: 11h SYMBOL: HAI[10] HAI[9] HAI[8] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 0 1 0 0 1 Rev 1.4 05/12/2006 17

Address: 12h SYMBOL: HAI[7] HAI[6] HAI[5] HAI[4] HAI[3] HAI[2] HAI[1] HAI[0] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 1 0 0 0 0 0 0 HAI [10:0]: Input Horizontal Active Pixels. HTI Address: 11h SYMBOL: HTI[10] HTI[9] HTI[8] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 0 1 0 0 1 Address: 13h SYMBOL: HTI[7] HTI[6] HTI[5] HTI[4] HTI[3] HTI[2] HTI[1] HTI[0] DEFAULT 1 0 0 0 0 0 0 0 HTI [10:0], the Input Horizontal Total Pixels VAI Address: 17h SYMBOL: VAI[9] VAI[8] DEFAULT 0 0 0 0 0 0 0 0 Address: 18h SYMBOL : VAI[7] VAI[6] VAI[5] VAI[4] VAI[3] VAI[2] VAI[1] VAI[0] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 1 1 1 1 0 0 0 0 VAI [9:0]: Input Vertical Active Pixels. Rev 1.4 05/12/2006 18

VTI Address: SYMBOL: VTI[9] VTI[8] DEFAULT 0 0 0 0 0 0 0 0 Address: 19h SYMBOL : VTI[7] VTI[6] VTI[5] VTI[4] VTI[3] VTI[2] VTI[1] VTI[0] DEFAULT 1 1 1 1 1 0 1 1 NOTE: Except H/V total and H/V active which can calculate from RegTab tool; sync pulse width and sync offset need to match the input timing of graphic controller. In the section TIMING has detail information for these registers. Figure H is the description of timing. 17h HA HO HW VA active region VO VW Figure H: Timing Description Rev 1.4 05/12/2006 19

Sub-carrier Generation ACIV ACIV(0x1C[4]) controls whether the FSCI value is used to set the sub-carrier frequency, or the automatically calculated (CIV) value. When the ACIV value is 1, the number calculated and present at the SCFREQ registers will be used as the increment value for sub-carrier generation. Whenever this bit is set to 1, the CFRB bit (register 0FH bit 6) bit should be set to 0 otherwise should set to 1. When the ACIV value is 0, the automatically calculated value will be used to set sub-carrier frequency. Address: 1Ch BIT : SYMBOL : ACIV DEFAULT 1 0 0 0 0 0 0 0 FSCISPP adjusts SDTV sub-carrier frequency and is in 2 s compliment format and has 12.87Hz adjustment step with 421KHz to 421KHz adjustment range. FSCISPP Address: 32h SYMBOL : FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ 15] 14] 13] 12] 11] 10] 9] 8] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 0 0 0 0 0 Address: 33h SYMBOL : FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ FSCISPP[ 7] 6] 5] 4] 3] 2] 1] 0] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 0 0 0 0 0 Rev 1.4 05/12/2006 20

TIMING Input Timing Input Timing Achieving Method After chosen input total pixels and lines, there are two ways to set input timing. One is from internal counter (set HVAUTO = 1), by this way the graphic controller only needs to send H sync, V sync and Data Enable signal (DE); the other is from input timing registers (set HVAUTO = 0), so the registers HAI, HTI, HO, HW, VAI, VTI, VO, and VW need to be programmed with input timing. Address: 11h SYMBOL: HVAUTO TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 0 1 0 0 1 HVAUTO (bit 7): defines how to achieve input timing information 0: from the register map input such as HTI, HAI, etc; 1: from internal counter; Input Timing Registers When HVAUTO is set to 0, the input timing information is achieved from input timing registers HAI, HTI, HO, HW, VAI, VTI, VO, and VW. The detail description of registers HAI, HTI, VAI and VTI are in section of USING UTILITY. HO Address: 14h SYMBOL: HO[10] HO[9] HO[8] DEFAULT 0 0 0 0 0 0 0 0 Address: 15h SYMBOL: HO[7] HO[6] HO[5] HO[4] HO[3] HO[2] HO[1] HO[0] DEFAULT 0 0 0 0 0 1 0 0 HO [10:0]: Input Horizontal Sync Offset (pixels from blanking starts). Rev 1.4 05/12/2006 21

HW Address: 14h SYMBOL: HW[9] HW[8] DEFAULT 0 0 0 0 0 0 0 0 Address: 16h SYMBOL: HW[7] HW[6] HW[5] HW[4] HW[3] HW[2] HW[1] HW[0] DEFAULT 0 0 0 0 0 0 1 0 HW [9:0]: Input Horizontal Sync Pulse Width (unit: pixel). VO Address: 17h SYMBOL: VO[9] VO[8] DEFAULT 0 0 0 0 0 0 0 0 Address: 1Ah SYMBOL: VO[7] VO[6] VO[5] VO[4] VO[3] VO[2] VO[1] VO[0] DEFAULT 0 0 0 0 0 1 0 0 VO [9:0]: Input Vertical Sync Offset (lines from blanking starts). VW Address: 1Bh SYMBOL: Reserved Reserved VW[5] VW[4] VW[3] VW[2] VW[1] VW[0] DEFAULT 0 0 0 0 0 0 1 1 VW [5:0]: Input Vertical Sync Pulse Width (unit: line). Rev 1.4 05/12/2006 22

Input Data Format The CH7023/CH7024 is flexible to accept several input data format of sources. Registers 0Ch and 0Dh should be configured appropriately to inform CH7023/CH7024 the input data format. MULTI Address: 0Ch SYMBOL: MULTI DEFAULT 0 0 0 0 0 0 0 0 MULTI (bit 0) indicates the multiplexed input data. Please refer to Datasheet Section 2.2.4 for details. HIGH, SWAP, IDF Address: 0Dh REVERS SYMBOL: HIGH SWAP[2] SWAP[1] SWAP[0] IDF[2] IDF[1] IDF[0] E DEFAULT 0 0 0 0 0 0 0 0 HIGH (bit 7) aligns the input data pins to the high part of D[23:0]. Please refer to Datasheet Section 2.2.4 for details. REVERSE (bit 6) changes R[7:0] to R[0:7], G[7:0] to G[0:7], B[7:0] to B[0:7], D[11:0] to D[0:11]. Please refer to Datasheet Section 2.2.4 for details. SWAP[2:0] (bits 5-3) change the order of three components of RGB or YCrCb input data. Please refer to Datasheet Section 2.2.4 for details. IDF[2:0] (bits 2-0) define the input data format. Please refer to Datasheet Section 2.2.4 for details. Rev 1.4 05/12/2006 23

Scaling Vertical Scaling For one input of Horizontal active pixels and Vertical active lines (HAI and VAI), there is more than one input of Horizontal total pixels and Vertical total lines (HTI and VTI). Based on system configuration the combinations of HTI and VTI decide different scaling sizes. Note: To enable simultaneous display of panel and TV, the timing selected should also comply with the timing requirement from the panel spec. Input vertical total line (VTI) decides vertical size of the video output. Bigger VTI generates smaller vertical size. By choosing different VTI, we can scale down or up the vertical size of the video output. Note: When scaling vertical size, the timing and clock have to be re-programmed base on the Horizontal total pixels and Vertical total lines that is selected. Horizontal Scaling CH7023/CH7024 provides a convenient way to scale horizontal size without re-sending timing and clock from graphic controller. By adjusting the value of register TVHA, the horizontal size of the output can be changed. Bigger TVHA generates bigger horizontal TV size. Address: 1Eh SYMBOL: Reserved Reserved Reserved Reserved Reserved TVHA[10 TVHA[9] TVHA[8] ] DEFAULT 0 0 0 0 0 1 0 1 Address: 1Fh SYMBOL: TVHA[7] TVHA[6] TVHA[5] TVHA[4] TVHA[3] TVHA[2] TVHA[1] TVHA[0] DEFAULT 1 0 1 0 0 0 0 0 TVHA[10:0] uses to define the TV Output Horizontal Active pixels. Rev 1.4 05/12/2006 24

Video Output Format Address: 0Ah SYMBOL: VOS[3] VOS[2] VOS[1] VOS[0] DEFAULT 0 0 0 1 0 0 0 0 VOS[3:0] (bits 3-0): define the Video Output Format VOS[3:0] as the follow table. Video Output Format VOS[3:0] VOS[3:0] Video Output formats 0000 NTSC_M 0001 NTSC_J 0010 NTSC_443 0011 PAL_B/D/G/H/K/I 0100 PAL_M 0101 PAL_N 0110 PAL_Nc 0111 PAL_60 Rev 1.4 05/12/2006 25

POWER MANAGEMENT & CONNECTION DETECTION Power Management Address: 04h SYMBOL PDDAC[1] PDDAC[0] FPD : DEFAUL 0 0 0 0 0 0 0 1 FPD (bit 0) controls the power on/off state. When FPD is 0, the CH7023/CH7024 is in power-up state. When FPD is 1, the CH7023/CH7024 is in power-down state. DAC Power Management PDDDAC[1] is power down control for DAC1; when set to 1, DAC1 is power down. PDDDAC[0] is power down control for DAC0; when set to 1, DAC0 is power down. Connection Detection Connection Detection Sequence Address: 62h BIT: SYMBOL SENSEE : N DEFAUL 0 0 1 1 0 1 0 0 SENSEEN enables the connection detection. The detection sequence is as following: Step 1: Set FPD = 0(0x04[0]=0) to Power up CH7023/CH7024 and set SEL_R(0x63[1]) to indicate the termination of the DAC. Step 2: set SENSEEN(0x62[7]) to 1 Step 3: read detection result from register 7Eh. If ATTACH0 = 01(0x7E[1:0]=01), then single composite output is connected; If ATTACH1 = 01(0x7E[3:2]=01), ATTCH2 = 01(0x7E[5:4]=01) and DUCVBS = 0 (0x0C[7]=0), then S-Video output is connected; If ATTACH1=01, ATTCH2=01 and DUCVBS=1, then dual composite outputs are connected; Step 4: set SENSEEN to 0 NOTE: Details of how to enable outputs to DAC are in sections DAC Power Management and DAC Switch. Rev 1.4 05/12/2006 26

Attached Display Address: 7Eh BIT: SYMBO Reserve Reserve ATTACH2 ATTACH2 ATTACH1 ATTACH1 ATTACH0 ATTACH0 TYPE: R R R R R R R R DEFAU 0 0 0 0 0 0 0 0 ATTACH2[1:0] (bits 5-4) returns attach information for S-Video C channel. When ATTACH2 = 01, S-Video C channel is connected. Otherwise, C channel is not connected. ATTACH1[1:0] (bits 3-2) of Register 7Bh returns attach information for S-Video Y channel. When ATTACH1 = 01, S-Video Y channel is connected. Otherwise, Y channel is not connected. ATTACH0[1:0] (bits 1-0) of Register 7Bh returns attach information for composite video channel. When ATTACH0 = 01, composite video channel is connected. Otherwise, composite video channel is not connected. DAC Switch Address: 0Ah SVD/DD DACSW[ DACSW[ SYMBOL: AC 1] 0] TYPE : R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 0 0 0 1 0 0 0 0 SVD/DDAC (bit 6): 1 enables two DAC outputs and the outputs are S-Video or dual CVBS. 0 enables single composite video output. DACSW[1:0] (bit 5-4): control the DAC switches per the following table. DACSW[1:0] Note 00 ALL DAC output switched off 01 ( CVBS DAC0 output CVBS signal format) 10 ( S-Video DAC0 output Y signal, DAC1 output C signal format) 11 Reserved (Invalid state) Rev 1.4 05/12/2006 27

FEATURE Control registers Hue Address: 05h BIT: SYMBOL Reserved HUE[6] HUE[5] HUE[4] HUE[3] HUE[2] HUE[1] HUE[0] DEFAUL 0 1 0 0 0 0 0 0 HUE[6:0] (bits 6-0) bits adjust hue setting of the image. The color can be tuned based on the formula (HUE[6:0]-64)/2 degrees. The power-on default angle is 0 degree. The weight of magenta color will be increased if the degree of angle is getting more positive. The weight of green color will be increased if the degree of angle is getting more negative. Saturation Address: 06h BIT: SYMBOL Reserved SAT[6] SAT[5] SAT[4] SAT[3] SAT[2] SAT[1] SAT[0] DEFAUL 0 1 0 0 0 0 0 0 SAT[6:0] (bits 6-0) adjust the color saturation of the image. Each increment will increase a level of saturation and vice versa. Contrast Address: 07h BIT: SYMBOL Reserved CTA[6] CTA[5] CTA[4] CTA[3] CTA[2] CTA[1] CTA[0] DEFAUL 0 1 0 0 0 0 0 0 CTA[6:0] (bits 6-0) adjust the contrast level of the image. Each increment will increase a level of contrast and vice versa. Brightness Address: 08h BIT: SYMBOL BRI[7] BRI[6] BRI[5] BRI[4] BRI[3] BRI[2] BRI[1] BRI[0] DEFAUL 1 0 0 0 0 0 0 0 Rev 1.4 05/12/2006 28

BRI [7:0] adjusts the brightness level of the image. Each increment will increase a level of brightness and vice versa. Sharpness Address: 09h BIT: SYMBOL Reserved Reserved Reserved Reserved Reserved TE[2] TE[1] TE[0] DEFAUL 0 0 0 0 0 1 0 0 TE[2:0] (bits 2-0) control the sharpness (text enhancement) adjustment of the image. In default, bits [2:0] are set to 100 for normal operation. Setting values higher than the power-on default will boost the high frequency band of the image. In contrast, setting values less than the power-on default will soften the image. Position Adjustment VP Address: 20h BIT: SYMBOL VPENB VP[1] VP[0] DEFAUL 0 0 0 0 0 0 0 0 Address: 21h BIT: SYMBOL VP[9] VP[8] VP[7] VP[6] VP[5] VP[4] VP[3] VP[2] DEFAUL 1 0 0 0 0 0 0 0 VP[9:0] defines the TV vertical position adjustment. The number of lines that is adjusted is determined by VP[9:0]-512. If the value is positive, the picture is moved upward; if the value is negative, the picture is moved downward. HP Address: 22h BIT: SYMBOL HP[1] HP[0] DEFAUL 0 0 0 0 0 0 0 0 Rev 1.4 05/12/2006 29

Address: 23h BIT: SYMBOL HP[9] HP[8] HP[7] HP[6] HP[5] HP[4] HP[3] HP[2] DEFAUL 1 0 0 0 0 0 0 0 HP[9:0] defines TV horizontal position adjustment. The number of pixels that is adjusted is determined by HP[9:0]-512. If the value is positive, the picture is moved to the right; if the value is negative, the picture is moved to the left. Bandwidth Control and TV Filter CFBP, CBW, YSV, YCV Address: 0Fh SYMBOL: CFBP CBW YSV[1] YSV[0] YCV[1] YCV[0] DEFAULT 0 0 0 0 0 0 0 0 CFBP (bits 5) bypasses TV Chroma filter, when CFBP= 1 ; otherwise enable the filter. CBW (bits 4) increases TV Chroma bandwith, when CBW= 1 ; otherwise decrease the Chroma bandwith. YSV[1:0] (bits 3-2) define the S-video Luma channel bandwidth control YSV[1:0]. YSV[1:0] can be set to 0, 1, 2. Larger YSV value results in higher luma channel bandwidth. YCV[1:0] (bits 1-0) define the Composite Luma channel bandwidth control YCV[1:0]. YCV[1:0] can be set to 0, 1, 2. Larger YCV value results in higher luma channel bandwidth AFF Address: 10h Reserve Reserve Reserve SYMBOL: Reserved AFF[2] AFF[1] AFF[0] d d d DEFAULT 0 0 0 0 0 0 0 1 Rev 1.4 05/12/2006 30

AFF[2:0] (bits 2-0) define the TV Adaptive Flicker Filter Control AFF[2:0]. Larger setting has stronger De-flicker effect. When AFF is 7, FC1 and FC2 are used. Dot Crawl Reduction Address: 1Ch SYMBOL : DOTCRB DEFAULT 1 0 0 0 0 0 0 0 DOTCRB(bit 0) enables TV Dot Crawl reduction when set to 1. And 0 disables Dot Crawl reduction. Rev 1.4 05/12/2006 31

Programming Sequence Connection detection Is a TV connected? No, exit. Yes Set FPD=0 to power up CH7023/CH7024 and power down digital path Set POUTEN to select clock master/slave Set crystal value Set XCH to select 1x/2x data rate to input clock and SEL_R to select single/double termination Set PLL settings, (A,) N, P, T, ( r1, r2,) r3, r4, r5 Set ACIV to select sub-carrier generation ACIV=1 ACIV=0 If crystal is predefined, use pre-stored Use chip auto calculated values sub-carrier values or calculate SCFREQ Set TV output format, DUCVBS and DAC switch Set input data format Set sync control bits, DES, VPO, HPO, SYO Set input timing achieving method HVAUTO=1 HVAUTO=0 Graphics Controller sending H,V syncs and DE Set input timing registers Set input timing from internal counter Graphics controller sending timing and clock Turn on DAC power Adjust features such as hue, saturation, brightness, contrast, sharpness, positions, bandwidth controls, AFF and DOTCRB Rev 1.4 05/12/2006 32

Appendix A: Programming IDF=5(YCbCr 4:2:2) When IDF = 5, the input data format is YCbCr 4:2:2. CH7023/CH7024 follows ITU-R BT.656 standards to set timing information automatically. Clock Master Mode The sequence to enable this mode is as following: 1. Set FPD=0 to power up CH7023/CH7024 2. Set TV_BP=1 Address: 0Ah SYMBOL: TV_BP DEFAULT 0 0 0 1 0 0 0 0 3. Set POUTEN to select clock master/slave 4. Set crystal value 5. Set XCH=1 6. Set MULTI=1, DCLSEL=1(0x0C[6]=1), DES=1 Address: 0Ch SYMBOL: DCKSEL DEFAULT 0 0 0 0 0 0 0 0 DCKSEL (bit 6) indicates whether the front uses DCLK or PCLK 0: uses PCLK 1: uses DCLK 7. Set input data format IDF=0x05 8. Set ACIV to select sub-carrier generation when ACIV=1, if crystal is predefined, use pre-stored sub-carrier values or calculate SCFREQ; when ACIV=0, use chip auto calculated values; 9. Set TV output format, DUCVBS and DAC switch 10. Set A, r1, r2, r3, r4 and r5. 11. Set PG=1(0x02[0] = 1) and set CBCRSW=1(0x10[3] = 1), then set PG = 0. Address: 02h BIT: SYMBOL PG DEFAUL 0 0 0 0 0 0 0 0 PG ( bit 0 ) is for page selection. 0: 1 st page; 1: 2 nd page Address: 10h Rev 1.4 05/12/2006 33

SYMBOL: CBCRSW DEFAULT 0 0 0 0 0 0 0 0 CBCRSW (bit 3) switches the order of CbCr component in the YCbCr 4:2:2 input format. 12. Turn on DAC power 13. Adjust features. Clock Slave Mode 1. Set FPD=0 to power up CH7023/CH7024 2. Set TV_BP=1 3. Set POUTEN to select clock master/slave 4. Set crystal value 5. Set XCH=1 6. Set MULTI=1, DCLSEL=1, DES=1 7. Set input data format IDF=0x05 8. Set ACIV to select sub-carrier generation when ACIV=1, if crystal is predefined, use pre-stored sub-carrier values or calculate SCFREQ; when ACIV=0, use chip auto calculated values 9. Set TV output format, DUCVBS and DAC switch 10. Set r3, r4 and r5. 11. Set PG=1and set CBCRSW=1, then set PG = 0 12. Turn on DAC power 13. Adjust features. Rev 1.4 05/12/2006 34

Appendix B: Test Mode CH7023/CH7024 provides test pattern following the sequence below. 1. Enable CH7023/CH7024. For IDF=0,1,2,3,4,6, follow the details in Programming Sequence section; for IDF=5, follow the details in appendix A. 2. Set PG=1(0x02[0] = 1) to go to register map page 1 3. Set TEST=1 to enable test mode and set TSTSYNC to use internal sync. 4. Set TSTP to select test pattern. 5. After test is done, set PG=0(0x02[0] = 1) to go back to register map page 0. Address: 04h SYMBOL TEST TSTSYNC TSTP[4] TSTP[3] TSTP[2] TSTP[1] TSTP[0] : DEFAUL 0 0 0 0 0 1 0 0 TEST (bit 6) is to enable internal test mode when TEST is 1 ; otherwise disable the internal test mode. TSTSYNC(bit 5) selects internally generated test sync for datapath when TSTSYNC = 1 ; otherwise, external input sync is used TSTP[4:0] (bits 4-0) selects input data for datapath. The table below has the details. Test pattern selection TSTP[4:3] TSTP[2:0] Input Video Patterns 00 (internal pattern) 000 All black 001 All white 010 Horizontal ramp 011 Vertical ramp 100 Color bar 101 One pixel color bar 110 Vertical zigzag, horizontal square, 8 pixel wide Rev 1.4 05/12/2006 35

Revision History Rev. Date Page Description 1.0 02/15/06 All First Revision 1.1 02/24/06 4 XCH description 31 Added appendix A 33 Added appendix B 1.2 03/03/06 4 XCH description 7 Multi description 33 CBCRSW description 1.3 3/16/06 All Added CH7024 support 1.4 5/12/06 3 Added section Chip Identification 19 Added Figure H: Timing Description Rev 1.4 05/12/2006 36