Design of Efficient Programmable Test-per-Scan Logic BIST Modules

Design of Efficient Programmable Test-per-Scan Logic BIST Modules Devika K N 1 and Ramesh Bhakthavatchalu 2 Electronics and Communication Engineering Amrita School of Engineering, Amritapuri Amrita Vishwa Vidyapeetham, Kerala Amrita University, India devikanandalal@gmail.com 1, rameshb@am.amrita.edu 2 Abstract This paper focus on the design of Programmable Logic BIST structures for Very Large Scale Integration (VLSI) Integrated Circuit(IC) testing. The advancements happening in VLSI technology day by day have made chip testing more complicated. This has paved way for the increased popularity of Logic Built In Self Test (LBIST) compared to Automatic Test Equipment (ATE). Logic BIST allows self testing of chips with the help of an additional built-in hardware structure inside the circuit. Test-per-scan Logic BIST structure includes Test pattern generator, Response Analyzer, ROM, and Comparator. LFSR does the role of test pattern generator in Logic BIST since it is more efficient than binary counters. MISR is commonly used as an output response analyzer which acts as an alternative to n-parallel LFSRs. Comparator compares the responses stored in ROM and MISR output. Reconfigurability is added to every structural element in BIST to improve the fault coverage of IC testing. The proposed structural architecture is simulated in Modelsim RTL simulator. The different sized (16, 32, 48) programmable structures in Logic BIST were synthesized in Xilinx Spartan 3E and Spartan 6 for implementing them on FPGA. Four structural representations such as Modular, Standard, Hybrid and Complete form were implemented for PRPG and MISR design. All the designs were synthesized in ASIC in RTL compiler using 90nm standard cell technology library. The results of the proposed programmable PRPG and MISR designs were analyzed for speed, power and area with the equivalent modules generated by third party sign-off tool. Keywords FPGA, PRPG, MISR, Reconfigurability, primitive polynomial, ASIC, SOC. I. INTRODUCTION This modern era of VLSI technology has witnessed a tremendous increase in the design complexity as well as higher density in System-on-chip (SOC) designs shooting at a faster rate. The Integrated circuits manufactured for critical applications are diagnosed with latent faults which may not be evident at the time of manufacturing testing but appears fatal in the later life span of the chip due to environmental variation. To ensure safety and durability, infield testing should be implemented within SOC s for detecting stuck at faults and bridging faults arising due to manufacturing defects. This lead to an innovative methodology called Logic BIST where circuit can be tested at-speed using built-in circuitry. Rapid testing and reduction in costs are the attractive features of Logic BIST structures compared to ATPG based testing [1]. While the former uses a random number generator to generate test patterns, the latter uses Automatic Test Equipment to provide stored deterministic patterns to the circuit under test. Since the patterns are generated at real time of circuit testing, it significantly reduces the memory usage adding to its features at the expense of small area overhead. Pseudo Random Pattern Generator (PRPG) and Multiple Input Shift Register (MISR) forms the critical components in Logic BIST. Pseudo Random Pattern Generator is implemented using an LFSR which generates random test patterns [2], [3]. Same LFSR structure is modified to work as MISR. Many research works have been done and is still under progress for implementing high performance LBIST circuits. One of the work utilizes a new adaptive low shift power random test pattern generator (ALP-RTPG) for generating test patterns in LBIST to reduce the power consumed [4]. But it results in significant test coverage loss with increase in the number of primary inputs. Another approach incorporates reconfigurable interconnects so as to reduce the correlation between test patterns [5]. It allows the requirement of fewer control bits compared to other BIST methods but can cause bus contention inside scan chains for those test vectors that is not desired. Paper [6] makes use of ATPG to provide deterministic patterns to deterministic BIST. But it converts failure diagnosis to a complex process. In this paper an n-bit reconfigurable LBIST structure that would be able to test any circuit has been designed and implemented. The proposed approach makes the design flexible by adding reconfigurability to each components of LBIST. It is simulated and synthesized using verilog on the Xilinx Spartan 3E for implementation in FPGA and in Encounter RTL compiler for implementation in ASIC [7]. The structures are designed and compared to verify its performance, area overhead and to maximize efficiency. The structure of the paper proceeds as follows: Section II describes the typical architecture of Logic BIST and its structural components. Section III discusses how programmable LBIST is implemented. Section IV shows the simulation and synthesis results of LBIST components in Xilinx and RTL compiler. Section V concludes the paper and discusses the future scope in this field. II. TYPICAL LOGIC BIST ARCHITECTURE Logic BIST is an extra testing circuitry embedded in the chip that perform structural based test after manufacturing. 978-1-5386-1716-8/17/$31.00 2017 IEEE

Fig. 2. N-bit Modular LFSR architecture Fig. 1. Typical Logic BIST architecture Logic BIST design includes on-chip/board circuitry to provide test patterns and to analyze output responses. Fig. 1. shows the typical Logic BIST architecture. Test pattern Generator, Multiple Input Signature Register, Comparator, ROM, and BIST controller forms the basic elements of the structure. This circuitry tests the chip infield thus avoiding the need for an ATE. It ensures high fault coverage with minimum vectors at the expense of 15% area overhead of the chip. In Logic BIST architecture PRPG plays the role of test pattern generator and MISR does the output response analysis. BIST components are detailed below: A. Pseudo Random Pattern Generator PRPG generates the required test vectors which are fed into the circuit to be tested. LFSR is the basic structure that generates pseudo random patterns based on the feedback polynomial provided [8],[9],[10],[11]. It is a kind of shift register where selected bits called taps are XORed to construct the feedback polynomial which is fed to LSB flip-flop of LFSR. Characteristic polynomial of degree n over GF (2) defines the internal structure of an n-bit LFSR where coefficients denote the existence of feedback path [12], [13]. Only primitive polynomials are considered as candidates for feedback loop in LBIST applications since they generate maximum length sequences. Such polynomials can be determined by checking whether the latter could completely divide x t + 1, where t = 2 n 1. Basic theory behind LFSR is Galois field. Every arithmetic operation in LFSR is based on modulo 2 where multiplication is equivalent to AND operation and addition is considered as XOR operation. PRPG can be implemented in four different forms: Standard, Modular, Complete and Hybrid. Fig. 2. shows N-bit Modular PRPG architecture. This configuration is better among all the four in terms of speed of execution, area, and power consumption. While standard form has higher critical path with increasing number of taps in the feedback polynomial. Complete PRPG demands more area due to additional gates used in circuit for generating 2 n patterns. Hybrid PRPG could be used only if the feedback polynomial satisfies a particular condition thus limiting its usage but has comparable features as that of standard form. Fig. 3. N-bit Modular MISR architecture B. Multiple Input Signature Register Multiple Input Signature Register is a modified form of LFSR that compresses long output sequence of bits from CUT into compressed data stream. It reduces the area overhead by acting as an alternative to multiple LFSR in parallel which is determined by the primary outputs of CUT. MISR compresses all outputs into a single LFSR and the resulting output value is known as signature [14]. It can be constructed from a LFSR structure since LFSR has linear properties and conforms to superposition principles. Signature is thus obtained as a result of performing modulo operation of each primary output with feedback polynomial and then XOR sum of the resultant. MISR produces compressed output that is compared with the expected outputs (Golden signature) using a comparator to check for faulty or fault-free circuit [15],[16]. Fig. 3. shows N-bit modular MISR architecture. C. Comparator Comparator performs data comparison where inputs are in the form of binary numbers. It checks whether a given number is equal, greater or less than the other one in terms of magnitude. In this context comparator does the comparison between golden signature stored in ROM and the resultant signature obtained from MISR and checks whether they are equal. The equality between the values indicates a fault-free circuit. If the values are not the same, it confirms that the circuit is faulty. Golden signature is the output from same identical circuit as that under test when it is in a fault-free condition. It is obtained through simulations under similar operations. D. Read Only Memory(ROM) Read only Memory (ROM) is a storage element that can retain data even when the power is off. In Logic BIST, stores Golden signature values of fault-free circuit. These values are pre-calculated through simulations. No amount of memory is used by this self-testing circuitry for storing test vectors thus saving large memory space.

E. Circuit Under Test Circuit Under Test could be combinational or sequential circuits. ISCAS-89 and ISCAS-99 circuits can be considered as the circuit to be tested to verify the working of Logic BIST architecture. These designs are the benchmark circuits which are designed using gate level modeling. The number of primary inputs and outputs of the circuit to be tested determines the size of PRPG and MISR to be used in LBIST structure. to replace third party generated equivalent structures to study the performance characteristics. This paper presents an idea of designing every basic component in a Logic BIST reconfigurable to accept any number of inputs of any bit size. Modular form of PRPG and MISR is efficient in terms of performance and speed compared with other configurations like standard, Complete and Hybrid. The proposed reconfigurable designs were found to be efficient in terms of speed, area, and power on comparison with equivalent third party tool generated modules as shown in table VII. IV. SIMULATION AND SYNTHESIS RESULTS Different components of Logic BIST structure is designed in verilog HDL, simulated in Modelsim 6.5 RTL simulator and Xilinx ISE is the software tool used for FPGA synthesis. Encounter RTL compiler is the EDA tool used for the synthesis of the design in ASIC. Fig. 4. Fig. 5. N-bit Modular LFSR architecture N-bit Modular MISR architecture III. PROPOSED ARCHITECTURE OF LOGIC BIST This paper focuses on the design of a Programmable Logic BIST structure. Every element inside the structure is made reconfigurable so that any circuit with different inputs could be tested by the same built-in testing circuitry. Reconfigurable PRPG is designed by adding multiplexers into the basic design of LFSR having XOR gates and flipflops as the core components. Feedback polynomial decides the position of XOR gates in LFSR. Multiplexers enable the designer to feed any initial value called seed with the help of select signal called load. In the other case pseudo random patterns starting from the initial value are generated through shift operation. The size of PRPG can also be varied to meet the circuit features adding to its flexibility. Fig. 4. Shows the proposed architecture for reconfigurable PRPG. MISR can also be made programmable by modifying the LFSR structure by adding XOR gates at the input of every flip-flop depending on the primary outputs of CUT. Fig. 5. shows the proposed architecture for MISR. The signature value obtained is provided as one of the input to a reconfigurable comparator whose other input is the golden signature stored in programmable ROM. Comparator is designed to accept any bit size input, provided the two inputs are of the same number of bits. ROM is also made programmable to store required number of signature values based on the number of signature a fault-free version of the circuit under test could actually produce. PRPG and MISR modules thus designed were used A. Synthesis result in Xilinx ISE tool Synthesis of 48 bit PRPG and MISR in its various configurations were done are their results were analyzed in both Spartan 6 and spartan 3E FPGA. Analysis shows that modular form of PRPG and MISR have maximum operational frequency compared to standard, complete or hybrid structure for any bit configuration. ASIC synthesis of 16bit PRPG is shown in fig. 6. Fig. 7. and fig. 8. displays FPGA synthesis of 48 bit modular PRPG and programmable 16 bit ROM respectively. Table I. and Table II. highlights the parametric analysis results of 48 bit PRPG and MISR in Spartan 6 and Spartan3E respectively. Complete PRPG/MISR has least speed of execution due to more number of gates involved in its critical path. Hybrid form has comparable properties to that of Standard one. Comparator and ROM were designed for 16 and 32 bit. B. Synthesis results in RTL compiler ASIC synthesis of every design also proved that modular structure had maximum speed of execution of about 1.37 GHz and less switching power. Standard PRPG/MISR had less speed and greater area overhead compared to hybrid form. Complete structure due to more number of gates used for its implementation showed up highest area overhead. Hybrid form utilized lesser number of XOR gates owing to its structural property and thus had efficient gate utilization. Table III. and table IV. shows the synthesis results of 48 bit PRPG and MISR in RTL compiler respectively. Fig. 9. displays the synthesis results of 16 bit comparator in RTL compiler while fig. 10. shows the synthesis of 48 bit modular MISR in Spartan 3E FPGA. TABLE I. PARAMETER ANALYSIS FOR 48 BIT PRPG IN XILINX FPGA Parameters Spartan-3E Spartan-6 S M C H S M C H FF s 48 48 48 48 48 48 48 48 LUTs 49 48 61 49 48 48 58 48 Slices/LUT-FF 28 28 34 28 48 48 48 48 Bonded IOBs 99 99 99 99 99 99 99 99 GCLK/BUFGs 1 1 1 1 1 1 1 1 Speed(GHz) 369 510 233 369 573 635 245 596

TABLE II. PARAMETER ANALYSIS FOR 48 BIT MISR IN XILINX FPGA Parameters Spartan-3E Spartan-6 S M C H S M C H FF 48 48 48 48 48 48 48 48 LUTs 49 54 62 49 50 48 58 48 Slices/LUT-FF 28 31 35 28 48 48 48 48 Bonded IOBs 147 147 147 147 147 147 147 147 BUFG/GCLKs 1 1 1 1 1 1 1 1 Speed(GHz) 387 517 233 387 573 635 245 596 S-Standard, M-Modular, C-Complete, H-Hybrid TABLE III. SYNTHESIS RESULTS OF 48 BIT PRPG IN RTL COMPILER Type of LFSR Size Area(nm 2 ) Mapped gates Power(nW) Speed(GHz) Standard 48 448.02 146 21054.91 1.188 Modular 48 448.70 146 21020.19 1.374 Complete 48 478.12 163 22203.97 0.617 Hybrid 48 448.02 146 21294.87 1.188 Fig. 8. FPGA Synthesis design of 16bit ROM TABLE IV. SYNTHESIS RESULTS OF 48 BIT MISR IN RTL COMPILER Type of LFSR Size Area(nm 2 ) Mapped gates Power(nW) Speed(GHz) Standard 48 579.35 194 32487.640 1.158 Modular 48 578.66 194 32662.183 1.183 Complete 48 612.864 212 33954.71 0.332 Hybrid 48 453.492 148 24078.032 1.168 Fig. 6. Schematic diagram of 16bit Modular PRPG in ASIC Synthesis Fig. 9. ASIC Synthesis design of 16bit Comparator Fig. 7. Technology Schematic of 48bit Modular PRPG in FPGA Fig. 10. Technology Schematic of 48bit Modular MISR in FPGA Logic BIST synthesis were done for the entire set of ISCAS-89 benchmark circuits for comparison of results and performance analysis. Table V explains the LBIST synthesis details while table VI highlights about the test and scan information s for these 27 circuits. V. CONCLUSION AND FUTURE SCOPE This paper presents a reconfigurable Logic BIST architecture where every component was designed to be programmable.

TABLE V. LOGIC BIST SYNTHESIS DETAILS OF DIFFERENT ISCAS-89 DESIGNS ISCAS PI PO Flip No of Scan Total Tested Test Design Flops scan chain Faults Faults coverage chains length S27 4 1 3 1 3 5041 4466 88.59 S298 3 6 14 2 7 5581 4796 85.99 S344 9 11 15 3 5 5879 4744 80.69 S349 9 11 15 3 5 5523 4300 77.86 S386 7 7 6 2 3 5698 4569 80.19 S400 3 6 21 2 11 5597 4372 78.11 S420 18 1 16 1 16 5751 4722 82.11 S444 3 6 21 2 11 5839 4594 78.68 S510 19 7 6 2 3 5896 4728 80.19 S526 3 6 21 2 11 5813 4871 83.79 S641 35 24 19 3 7 6907 4773 69.10 S713 35 23 19 5 4 6865 4767 69.44 S820 18 19 5 1 5 7253 4911 67.71 S832 18 19 5 1 5 7203 4914 68.22 S838 34 1 32 1 32 6537 4976 76.12 S953 16 23 29 4 8 7389 5282 71.48 S1196 14 14 18 3 6 7548 4615 61.14 S1238 14 14 18 3 6 7627 4609 60.43 S1423 17 5 74 5 15 7873 5240 66.56 S1488 8 19 6 2 3 7911 4620 58.40 S5378 35 49 179 6 30 12327 7950 64.49 S9234 36 39 211 15 10 10857 7606 70.06 S13207 62 152 638 22 27 22449 14860 66.19 S15850 77 150 534 28 19 25091 13480 53.72 S35932 35 320 1728 32 54 27592 15031 54.48 S38417 28 106 1636 26 61 51227 44243 86.37 S38584 38 304 1426 31 42 62394 24493 39.26 TABLE VI. TEST AND SCAN DETAILS IN LBIST FOR DIFFERENT ISCAS-89 DESIGNS ISCAS Test Scan Test Test Design Cycles Cycles Sequences coverage S27 193 12384 95 88.59 S298 191 8740 94 85.99 S344 199 8910 98 80.69 S349 199 8910 98 77.86 S386 217 9504 107 80.19 S400 197 9310 97 78.11 S420 199 14058 98 82.11 S444 191 9025 94 78.68 S510 203 8888 100 80.19 S526 187 8835 92 83.79 S641 209 9256 103 69.10 S713 213 3286 105 69.44 S820 221 14410 109 67.71 S832 229 14934 113 68.22 S838 293 23068 145 76.12 S953 209 5200 103 71.48 S1196 313 14196 155 61.14 S1238 297 13468 147 60.43 S1423 207 4429 102 66.56 S1488 317 13904 157 58.40 S5378 377 10716 187 64.49 S9234 211 2310 104 70.06 S13207 241 2760 119 66.19 S15850 275 3425 136 53.72 S35932 251 6875 124 54.48 S38417 343 11286 170 86.37 S38584 391 8970 194 39.26 This design thus ensures self-testing of any kind of circuitry with varying configurations. PRPG and MISR structures were made reconfigurable by adding multiplexers into its designs and providing flexibility in the position of tap insertions which determines the feedback polynomials and the patterns generated. For MISR, XOR gates were added to every flipflop inputs depending on the number of primary outputs of the CUT. Comparator and ROM were also designed to compare and store any number of inputs with varying size. TABLE VII. COMPARISON OF PERFORMANCE PARAMETERS BETWEEN THIRD PARTY GENERATED AND RECONFIGURABLE LOGIC BIST MODULES Design Area(nm 2 ) Power(nW) Speed(GHz) Original New Original New Original New Netlist Netlist Netlist Netlist Netlist Netlist s27 1869 1867 83990.272 71611.639 0.2679 0.2745 s298 2056 2037 91425 75297.437 0.247 0.2593 s344 2141 2074 95961.366 85445.902 0.240 0.2519 s349 2094 2074 95127.456 84480.920 0.240 0.2519 s386 2018 2006 88244.862 72896.09 0.2745 0.2745 s400 2126 2108 92892.159 79150.676 0.236 0.2475 s420 2025 2068 96413.962 80062.812 0.2511 0.2641 s444 2125 2108 93108.119 79288.009 0.236 0.2475 s510 2063 2049 85429.312 74164.771 0.25458 0.2679 s526 2195 2130 88271.122 78581.521 0.2360 0.2475 s641 2172 2148 99605.758 88793.705 0.2348 0.2462 s713 2328 2281 103970.663 93192.840 0.2746 0.2746 s820 2031 2027 83568.456 76118.075 0.2745 0.2761 s832 2044 2038 83519.909 71994.030 0.2745 0.2745 s838 2244 2237 100696.904 87612.279 0.1942 0.1942 s953 2516 2477 99140.407 76919.855 0.2175 0.2273 s1196 2416 2396 111407.334 89630.085 0.2368 0.2482 s1238 2415 2395 108719.470 93112.487 0.2359 0.2475 s1423 3052 3003 137945.42 128169.076 0.17476 0.1747 s1488 2320 2308 93704.957 82839.815 0.2357 0.2671 s5378 4571 4511 192386.015 175070.663 0.1583 0.1686 s9234 5241 5164 203865.65 174954.325 0.1634 0.1641 s13207 10232 10128 458262.846 449548.423 0.1329 0.1389 s15850 11021 10275 481128.040 362911.925 0.1198 0.12409 s35932 24501 23779 904900.427 846070.781 0.1147 0.1147 s38417 22687 22087 1096869.171 1048625.08 0.1211 0.1306 s38584 21984 21884 888992.134 815255.000 0.1176 0.1227 The analysis of this work shows that modular structure is efficient in terms of speed of execution and in gate utilization compared to other forms of Reconfigurable PRPG or MISR. The proposed PRPG and MISR design modules displayed better performance in terms of speed, area and power on comparison with the same structures generated by a third party tool. As future scope, ROM and Comparator modules of Logic BIST structure can also be reconfigured and replaced to analyze the performance variations in analogy with tool generated design equivalent. REFERENCES [1] Nagaraj s vannal, saroja v siddamal, shruti v bidaralli, mahalaxmi s bhille, Design and testing of combinational Logic circuits using built in self Test scheme for fpgas, 2015 fifth international conference on communication systems and network technologies, 2015. [2] Ramesh Bhakthavatchalu and M. Nirmala Devi, Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture, International Journal of Engineering and Technology, vol. 7, no. 3, pp. 973 984, 2015. [3] Ramesh Bhakthavatchalu, Deepthy G R, Sreenivasa Mallia S, HariKrishnan R, ArunKrishnan, Sruthi.B, 32-bit Reconfigurable Logic-BIST Design Using Verilog for ASIC Chips, Recent Advances in Intelligent Computational Systems (RAICS), pp. 386 390, 2011. [4] Xijiang Lin and Janusz Rajski, Adaptive Low Shift Power Test Pattern Generator for Logic BIST, 19th IEEE Asian Test Symposium, 2010. [5] Lei Li and Krishnendu Chakrabarty, Test Set Embedding for Deterministic BIST Using a Reconfigurable Interconnection Network, IEEE Transactions on computer-aided design of Integrated Circuits and Systems, vol. 23, no. 9, pp. 1289 1305, 2004. [6] Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew, Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST, 23rd IEEE VLSI Test Symposium (VTS 05), 2005.

[7] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall PTR, One Lake Street, Upper Saddle River, United States of America, 2003. [8] Valarmathi Marudhai, Implementation of LFSR on ASIC, 2012 Annual IEEE India Conference (INDICON), pp. 275 279, 2012. [9] P. Dhanesh, A Jayanth Balaji, Dual threshold bit-swapping LFSR for power reduction in BIST, Advanced Computing and Communication Systems, 2015 International Conference on, 2015. [10] Amit Kumar Panda, Praveena Rajput, Bhawna Shukla, FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL, Communication Systems and Network Technologies (CSNT), 2012 International Conference on, pp. 769 773, 2012. [11] Li-Ren Huang, Jing-Yang Jou, and Sy-Yen Kuo, Gauss-Elimination- Based Generation of Multiple Seed Polynomial Pairs for LFSR, IEEE Transactions on computer-aided design of Integrated Circuits and Systems, vol. 16, no. 9, September 1997. [12] http://en.wikipedia.org/wiki/linear feedback shift register. [13] Laung-Terng Wang, Cheng Wen Wu, Xiaoqing Wen, VLSI test principles and architectures, DESIGN FOR TESTABILITY, Morgan Kaufmann Publishers,United States of America, 2006. [14] Kazuhiko Iwasaki, Shou-Ping Feng, Tom Fujiwara and Tadao Kasami, Comparison of Aliasing Probability for Multiple MlSRs and M- stage MlSRs with m Inputs, IEEE TRANSACTlONS ON COMPUTER- AIDED DESIGN, pp. 90 95, SEPTEMBER 1991. [15] Maurizio Damiani, Piero Olivo, Michele Favalli, Silvia Ercolani, and Bruno Ricco, Aliasing in Signature Analysis Testing with Multiple Input Shift Registers, IEEE TRANSACTlONS ON COMPUTER-AIDED DESIGN, vol. 9, no. 12, pp. 1344 1353, DECEMBER 1990. [16] Ramesh Bhakthavatchalu, Sreeja Krishnan, Vineeth V, Nirmala Devi M., Deterministic Seed Selection and Pattern Reduction in Logic BIST, VLSI Design and Test, 18th International Symposium on, 2014.