Remote Diagnostics and Upgrades Tim Pender -Eastman Kodak Company 10/03/03
About this Presentation Motivation for Remote Diagnostics Reduce Field Maintenance costs Product needed to support 100 JTAG chains Support non-compliant vendors Scope will not discuss remote access SW schemes will address detailed System Level JTAG Terminology Reconfiguration vs Reprogramming
Agenda Remote Diagnostics Example Benefits JTAG MUX IP Remote Diagnostics Board Overview Altera EPC ISP configuration proms Embedded FPGA BIST Controller JTAG Signal Integrity Summary 3
J PCI Bridge Mode jumpers J F J F J F EPC4 Mode jumpers JTAG Connector J J F J F J F F EPC4 Mode jumpers JTAG Connector J F J PCI F J F Bridge F EPC4 P C I J PCI Bridge F P C I P C I JTAG Connector TDO TMS TCK TDI TDO TMS TCK 20KE FPGA TDI PCI Lcl BUS TDO TMS TCK 20KE FPGA TDI PCI Lcl BUS 20KE FPGA PCI Lcl BUS Remote Diagnostics/ Upgrade Example Remote JTAG Enabled Product J Mode jumpers F J F J F JTAG Connector 20KE FPGA Programming/ Test Files Software JTAG Controller Remote Access PCI Bridge EPC4 J F TDO TMS TCK TDI PCI Lcl BUS System Level JTAG Access Product P C I P C I JTAG access to all chains in the system with a single point of entry (Ideal) Embedded JTAG controller with Test and/or programming files Remote Access can control product or download updated files 4
Benefits - Remote Diagnostics/Upgrades $$$ Test Development Reuse Reduction in Field Service Labor Simple enough for end user test/updates Remote test/updates Time Time to market improved less JTAG debug needed latest FW can be upgraded in the field Better Uptime Remote diagnostics isolate fault so replacement part is in hand. Timely upgrades 5
Benefits- Reduction in Field Service labor Traditional Field Service (FS) Update Labor time = 20,000 hrs or 500 wk (5000 products) (4 hrs/ products) Update cost = $1.5 Million (per upgrade) (20,000 hrs) ($75/hr) Upgrade Cost ($ Millions) 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 Upgrade Costs of 5000 products Field Service Remote Upgrades 1 3 5 7 9 11 Num ber of Upgrades Remote Upgrade Update Cycle Time Update Labor Time time = 1hr 25000 Development cost = $400k (2 Engineer yrs.) (2000hr /yr..) ($100/hr) Hardware cost = $100k Labor Time (hr) 20000 15000 10000 5000 0 Field Service Remote Upgrades (5000 prod) ($20 / prod) Total Upgrade cost = $500k (one time cost) 1 7 13 19 25 31 37 43 Number of products Updated (hundred) 49 6
JTAG MUX IP Overview clk rst_n cmd_sel oe_n host1 host2 host3 host4 hostx_prstn JTAGMUX remote sync serial protocol decode Host Selection TAP HW ChainPrsnt HW HostPrsnt SW Chain Selector Control User Def DIO1 DIO2 Chain Linker dio1 dio2 chain1 chain2 chain3 chain4 chainx_prstn JTAGMUX remote - uses a serial protocol to write or read JTAG registers via software control The JTAG registers allow control of the chain and hosts regardless of Host and chain present inputs JTAGMUX local- The Host Selection and Chain linking is dependant on the Host and Chain present inputs Host priority host1 highest & host4 lowest (incase of multiple hosts) Chain order is guaranteed chain1 first & chain 4 last 7
JTAG MUX local - isolating a chain Chain isolation is important, many silicon vendors have noncompliant JTAG hardware or software Emulator Host drives the DSP, chain1 is selected because chain1 Present pin is connected to ground through JMP1. 8
JTAG MUX local - daisy chain Altera and Xilinx devices are daisy-chained, chain1&2 Present pins are connected to ground through JMP1 & JMP2. 9
Automatic Chain Selection/ Host Adapter Harness VCC JTAG Mux Chain1 DSP DSP EMU tck tms tdi tdo Gnd J T A G H e a d e r Chain1_prsntn Chain2_prsntn Chain3_prsntn Chain4_prsntn Port1_tck Port1_tms Port1_tdi Port1_tdo Port1_prsntn Chain2 Chain3 Altera CPLDs Xilinx FPGAs Altera Byteblaster Chain4 up up EMU tck tms tdi tdo Gnd tck tms tdi tdo Gnd ASSET dio_1 dio_2 dio_3 dio_1 tck tms tdi tdo Gnd Illustration of Reducing the number of JTAG connectors on a Board. Create one JTAG connector on the board. Create a harness that adapts each JTAG host to the JTAG connector. The appropriate chain is automatically selected because the harness routes ground to the corresponding chain present line, no jumpers needed. Note the Asset JTAG tester has optimal control since it has digital io pins 10
Remote Diagnostics Board (RDB) Block Diagram Analog Drivers chain1 System Controller FPGA JTAG Host JTAG PARTITIONING EPLD chain2 EPC config prom chain3 User IF Memory chain4 Mixed Signal/ DOT4 Chain1 is connected to IO pins on the FPGA and depending on the configuration loaded may or may not have soft TAP functionally. Chain 2 has two devices, the Altera EPC4 and FPGA. Chain 3 consists of three 74abt18245 buffers. Chain 4 is a National Semiconductor STA400 Dot 4 chip. 11
Embedded FPGA BIST Controller Use the Centralized FPGA to Test the board at speed BIST routines were developed for FPGA peripherals (SRAM, Relays, Fans, Stepper Motor, ADC) MemBIST VHDL generated by Mentor SW Mentor BSD Architect developed a soft TAP VHDL JTAG interface New instructions were added to soft tap to launch the Test Benches. 12
sync serial protocol decode TAP HW ChainPrsnt H W H o s tp rs n t SW Chain Selector C ontrol User Def DIO1 DIO2 C hain Prsntn EPC4 ISP configuration Prom EPC4 JTAG Host oe oe TDI clk rs t_ n cm d_sel oe_n host1 host2 host3 host4 3128 EPLD H o s t S e le c tio n hostx_prstn TCK JTAG M U X re m o te TAP C h a in Linker chainx_prstn TMS D IO 1 D IO 2 chain1 chain2 chain3 chain4 TDO DIO1 chain1 chain2 DCLK DATA CONFIGn 20KE FPGA STATUSn CONF_DONEn Configuration Pins TDO S O TMS F T BIST TCK Controller TDI T A TRSTnP TAP TDI TCK TMS TDO CSn PGM0 PGM1 PGM2 INIT_CONFn DCLK DATA0 System Controller BIST Controller TDI TAP TDO TCK TMS System level JTAG - All chains are accounted for. The JTAG host can access the JTAG MUX host4 input to gain access to chains 1-4 (only 1&2 shown). The JTAG host can also access the EPLD TAP for reprogramming. The EPC4 will configure the FPGA with the page of memory corresponding to PGM pins driven by the JTAG MUX. 13
TCK Signal Integrity tck 6" 1" 7.000 6.000 Probe 2:U32.1 Probe 3:U33.1 Probe 4:U34.1 1k 1" 5.000 4.000 NO COMPENSATION The waveform shows fluctuations on TCK upper rail into intermediate area for about 3ns (BAD). Fluctuations at the lower rail are marginal since they exceed.8v for less than 1ns. V 3.000 O L 2.000 T A G 1.000 E 0.000 (V) -1.000-2.000 Bad Marginal -3.000 0.000 10.000 20.000 30.000 40.000 50.000 Time (ns) tck 39 6" 1" 7.000 6.000 5.000 Probe 2:U32.1 Probe 3:U33.1 Probe 4:U34.1 68pf 1k SERIES COMPENSATION & CAP The capacitor at the output of the driver slows the rise time down to from 1ns to 3.5 ns. 1" V O L T A G E 4.000 3.000 2.000 1.000 (V) 0.000-1.000-2.000-3.000 Great 0.000 10.000 20.000 30.000 40.000 50.000 Time (ns) 14
TCK Signal Integrity Comment: TCK 2 loads (39 ohm series comp.) tck 39 4" 7.000 6.000 5.000 4.000 Marginal Probe 5:U25.1 Probe 6:U35.1 1k 6" Vo lta ge - V- 3.000 2.000 1.000 Marginal 0.000 SERIES COMPENSATION Adding compensation made the both edges look worse, however it did help the ringing slightly. -1.000-2.000-3.000 0.000 10.000 20.000 30.000 40.000 50.000 Time (ns) Comment: TCK 2 loads ( 100 series ohm and 10pf cap at input) 4" 100 7.000 6.000 5.000 Probe 5:U25.1 Probe 6:U35.1 tck 1k 6" 10p 100 V O L T A G E 4.000 3.000 2.000 1.000 Great 10p INPUT RESISTOR & CAP The new C value is 10pf + Cin which slows the edges down even further. (V) 0.000-1.000-2.000-3.000 0.000 10.000 20.000 30.000 40.000 50.000 Time (ns) 15
Summary Treat TCK like any other clock signal for SI A System level JTAG strategy enables Remote diagnostics and upgrades JTAG MUX Embedded BIST in FPGAs allows HW engineers to test the hardware Concerns with Remote operations Security / Remote Access method Safety Huge Benefits $$ 16
Acronyms BIST Built In Self Test EPLD Electrically Programmable Logic Device EMU Emulator FPGA Field Programmable Gate array FS Field Service FW Firmware HW Hardware IP Intellectual Property ISP In-System Programmable JAM Altera developed Standard Test and Programming Language JTAG Joint Test Action Group, IEEE1149.1 LPT PC Parallel Port PCB Printed Circuit Board SI Signal Integrity STPL Standard Test and Programming Language (JEDEC JESD71) SVF Serial Vector Format SW Software 17