CMOS Design Analysis of 4 Bit Shifters 1 Baljot Kaur, M.E Scholar, Department of Electronics & Communication Engineering, National

Similar documents
Optimized Design and Simulation of 4-Bit Johnson Ring Counter Using 90nm Technology

CMOS DESIGN OF FLIP-FLOP ON 120nm

Design and Analysis of a Linear Feedback Shift Register with Reduced Leakage Power

LOW POWER & AREA EFFICIENT LAYOUT ANALYSIS OF CMOS ENCODER

A NOVEL DESIGN OF COUNTER USING TSPC D FLIP-FLOP FOR HIGH PERFORMANCE AND LOW POWER VLSI DESIGN APPLICATIONS USING 45NM CMOS TECHNOLOGY

LFSR Counter Implementation in CMOS VLSI

ANALYSIS OF POWER REDUCTION IN 2 TO 4 LINE DECODER DESIGN USING GATE DIFFUSION INPUT TECHNIQUE

Design of a Low Power and Area Efficient Flip Flop With Embedded Logic Module

CHAPTER 6 COUNTERS & REGISTERS

International Journal of Computer Trends and Technology (IJCTT) volume 24 Number 2 June 2015

A Power Efficient Flip Flop by using 90nm Technology

Power Efficient Design of Sequential Circuits using OBSC and RTPG Integration

DESIGN AND SIMULATION OF LOW POWER JK FLIP-FLOP AT 45 NANO METER TECHNOLOGY

Design of Low Power D-Flip Flop Using True Single Phase Clock (TSPC)

Design and Simulation of a Digital CMOS Synchronous 4-bit Up-Counter with Set and Reset

Introduction. Serial In - Serial Out Shift Registers (SISO)

DIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME

Scanned by CamScanner

Design of Low Power and Area Efficient 64 Bits Shift Register Using Pulsed Latches

DIGITAL REGISTERS. Serial Input Serial Output. Block Diagram. Operation

Power Optimization by Using Multi-Bit Flip-Flops

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER USING 180NM CMOS PROCESS TECHNOLOGY

data and is used in digital networks and storage devices. CRC s are easy to implement in binary

LOW POWER AND HIGH PERFORMANCE SHIFT REGISTERS USING PULSED LATCH TECHNIQUE

Design And Analysis Of Implicit Pulsed Double Edge Triggered Clocked Latch For Low Power Applications

Abstract 1. INTRODUCTION. Cheekati Sirisha, IJECS Volume 05 Issue 10 Oct., 2016 Page No Page 18532

International Journal Of Global Innovations -Vol.6, Issue.I Paper Id: SP-V6-I1-P46 ISSN Online:

PERFORMANCE ANALYSIS OF AN EFFICIENT PULSE-TRIGGERED FLIP FLOPS FOR ULTRA LOW POWER APPLICATIONS

EFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH

Design of New Dual Edge Triggered Sense Amplifier Flip-Flop with Low Area and Power Efficient

SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur

DESIGN OF LOW POWER TEST PATTERN GENERATOR

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS

Modified Ultra-Low Power NAND Based Multiplexer and Flip-Flop

Chapter 7 Counters and Registers

University College of Engineering, JNTUK, Kakinada, India Member of Technical Staff, Seerakademi, Hyderabad

Analysis of Digitally Controlled Delay Loop-NAND Gate for Glitch Free Design

Design of Low Power and Area Efficient Pulsed Latch Based Shift Register

Modifying the Scan Chains in Sequential Circuit to Reduce Leakage Current

ISSN Vol.08,Issue.24, December-2016, Pages:

Efficient Architecture for Flexible Prescaler Using Multimodulo Prescaler

Area Efficient Pulsed Clock Generator Using Pulsed Latch Shift Register

Module -5 Sequential Logic Design

P.Akila 1. P a g e 60

AN OPTIMIZED IMPLEMENTATION OF MULTI- BIT FLIP-FLOP USING VERILOG

Combining Dual-Supply, Dual-Threshold and Transistor Sizing for Power Reduction

WINTER 15 EXAMINATION Model Answer

Improve Performance of Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

VLSI Design: 3) Explain the various MOSFET Capacitances & their significance. 4) Draw a CMOS Inverter. Explain its transfer characteristics

EFFICIENT POWER REDUCTION OF TOPOLOGICALLY COMPRESSED FLIP-FLOP AND GDI BASED FLIP FLOP

DESIGN OF A NEW MODIFIED CLOCK GATED SENSE-AMPLIFIER FLIP-FLOP

LOW POWER AND AREA-EFFICIENT SHIFT REGISTER USING PULSED LATCHES

Novel Low Power and Low Transistor Count Flip-Flop Design with. High Performance

Low Power Approach of Clock Gating in Synchronous System like FIFO: A Novel Clock Gating Approach and Comparative Analysis

GLITCH FREE NAND BASED DCDL IN PHASE LOCKED LOOP APPLICATION

IC Layout Design of Decoders Using DSCH and Microwind Shaik Fazia Kausar MTech, Dr.K.V.Subba Reddy Institute of Technology.

II. ANALYSIS I. INTRODUCTION

Chapter 4. Logic Design

Sequential Logic Basics

Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath

A Low-Power CMOS Flip-Flop for High Performance Processors

Design of low power 4-bit shift registers using conditionally pulse enhanced pulse triggered flip-flop

Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari

SA4NCCP 4-BIT FULL SERIAL ADDER

High Performance Dynamic Hybrid Flip-Flop For Pipeline Stages with Methodical Implanted Logic

Logic Design Viva Question Bank Compiled By Channveer Patil

Low Power D Flip Flop Using Static Pass Transistor Logic

DESIGN AND ANALYSIS OF COMBINATIONAL CODING CIRCUITS USING ADIABATIC LOGIC

LOW POWER DOUBLE EDGE PULSE TRIGGERED FLIP FLOP DESIGN

PERFORMANCE ANALYSIS OF POWER GATING TECHNIQUES IN 4-BIT SISO SHIFT REGISTER CIRCUITS

Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains

POWER OPTIMIZED CLOCK GATED ALU FOR LOW POWER PROCESSOR DESIGN

PESIT Bangalore South Campus

Low-Power and Area-Efficient Shift Register Using Pulsed Latches

INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)

Parametric Optimization of Clocked Redundant Flip-Flop Using Transmission Gate

Low Power Area Efficient VLSI Architectures for Shift Register Using Explicit Pulse Triggered Flip Flop Based on Signal Feed-Through Scheme

DESIGN OF EFFICIENT SHIFT REGISTERS USING PULSED LATCHES 1 M. AJAY

Design of High Speed Phase Frequency Detector in 0.18 μm CMOS Process for PLL Application

Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533

Power Optimization of Linear Feedback Shift Register (LFSR) using Power Gating

Dual Slope ADC Design from Power, Speed and Area Perspectives

Design And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique

Design of Sequential Circuit using Low Power Adiabatic Complementary Pass Transistor Logic

Dual Edge Triggered Flip-Flops Based On C-Element Using Dual Sleep and Dual Slack Techniques

DESIGN OF DOUBLE PULSE TRIGGERED FLIP-FLOP BASED ON SIGNAL FEED THROUGH SCHEME

Level Converting Retention Flip-Flop for Low Standby Power Using LSSR Technique

Gated Driver Tree Based Power Optimized Multi-Bit Flip-Flops

HIGH PERFORMANCE AND LOW POWER ASYNCHRONOUS DATA SAMPLING WITH POWER GATED DOUBLE EDGE TRIGGERED FLIP-FLOP

Design and Evaluation of a Low-Power UART-Protocol Deserializer

Design of an Efficient Low Power Multi Modulus Prescaler

Low Power Area Efficient Parallel Counter Architecture

UNIT-3: SEQUENTIAL LOGIC CIRCUITS

An Efficient IC Layout Design of Decoders and Its Applications

A Modified Static Contention Free Single Phase Clocked Flip-flop Design for Low Power Applications

AN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS

IT T35 Digital system desigm y - ii /s - iii

Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)

LOW POWER LEVEL CONVERTING FLIP-FLOP DESIGN BY USING CONDITIONAL DISCHARGE TECHNIQUE

Computer Systems Architecture

Transcription:

CMOS Design Analysis of 4 Bit Shifters 1 Baljot Kaur, M.E Scholar, Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training & Research, Chandigarh, UT, (India), jotbabbar94@gmail.com 2 Rajesh Mehra, Associate Professor, Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training & Research, Chandigarh, UT, (India) Abstract - This paper presents CMOS shifters which are designed to reduce area as well as power on 90nm technology. Two designs for shifters have been proposed namely fully automatic and semi-custom. In first approach fully automatic design where inbuilt active devices are used along with auto-routing and placement options. In second approach, semicustom design inbuilt active devices are used along with optimized manual routing and placement. In fully-automatic approach proposed schematic is designed with DSCH and its equivalent layout is created using Microwind. In case of semi-custom design, optimized layout is created with Microwind. It can be observed from simulated results that SIPO area is reduced by 48.55% and power is reduced by 7.30% whereas in PIPO area is reduced by 52.71% and power is reduced by 2.5%. It is well known that as computation point of view PIPO is used. As Circuit is mimicked and the power and area consumption is less in PIPO so we can use it in many applications. Keywords: flip flop, semiconductor, shift register-p-mos,n-mos, Transistor. I. INTRODUCTION Shift Registers in digital circuits are used to shift as well as store the data. That's why there need is increasing day by day. Shifters are used in manipulation of data as well as multiplication of floating numbers etc. The fast development in semiconductor gadget industry has prompted the improvement of high versatile frameworks with upgraded unwavering quality [1]. Those convenient applications, become critical to limit area [2] and utilization because of the restricted accessibility of battery control [1]. That's why, area minimization, power dissipation turns into a vital plan in VLSI [3,4]. In shift registers flip flops are cascaded, having a similar clock, in which the output of one flip-flop is connected with the input of the other flip-flop in the chain, bringing about a circuit that moves one bit in every clock pulse, moving in the information show at its information and moving out the last piece in the array. Shift Register is of two types Parallel and Serial inputs types and Parallel and Serial outputs types. Depending on this further four types of shift registers are there Serial In Serial Out, Serial In Parallel Out, Parallel In Serial Out, Parallel In Parallel Out. In this Shift register we can either use J-K flip flop or D flip flop whereas in this paper D flip flop is used to reduce the complexity. Repeating waveforms can be generated for counter circuits by using shift registers. Shift Registers which has complex circuitry will take long time to generate feedback patterns so they can resemble random noise or pseudo noise. Some of the methods are suggested in this paper to implement that type of shift registers[5]. As,given above there are four types of shift registers given below as [6]: 1. SISO (Serial In Serial Out):Data is shifted serially in one by one bit and shifted serially out one by one bit. It takes n bits to shift data in and n-1 bits to shift data out. 2. SIPO (serial In Serial Out):Data is shifted serially in one by one bit and shifted parallel out. It takes n bits to shift data in and 0 bits to shift data out. 3. PISO (Parallel In Serial Out):Data is shifted parallel in and shifted serially out one by one bit. It takes 1 bit to shift data in and n-1 bits to shift data out. 4. PIPO (Parallel In Parallel Out):Data is shifted parallel in and parallel out. It takes 1 bit to shift data in and 0 bit to shift data out. II. SHIFTERS Serial In and Parallel Out shift register is the type of shift register in which data will load and retrieve in serial and parallel mode respectively. Below Figure 1 is shown how SIPO is working. Figure 1: Serial In Parallel Out Shift Register 483 IJREAMV04I0339123 DOI : 10.18231/2454-9150.2018.0367 2018, IJREAM All Rights Reserved.

Its working is simple as data entered serially one by one bit. Output is taken parallel all the bits simultaneously. To enter data serially n clock pulses are required. To take data parallel out 0 clock pulses are required[7]. Operation of SIPO is as initially, we apply reset or clear so that any previous data stored in the shifter can be removed. When clear is given to the circuit all the flip flops are at low state i.e. zero. When flip flops are at low state output of the circuit will be zero. When first clock signal appeared, then data transfer takes place. In first flip flop which is suppose QA will receive the first bit of data it becomes 1 and other flip flops become low i.e. zero. When second clock signal appeared, in second flip flop which is suppose QB will receive the second bit of data it becomes 1 and other flip flops become low i.e. zero. When third clock signal appeared, in third flip flop which is suppose QC will receive the third bit of data it becomes 1 and other flip flops become low i.e. zero. When last clock signal appeared, in fourth flip flop which is suppose QD will receive the fourth bit of data it becomes 1 and other flip flops become low i.e. zero. At every clock pulse, it will shift the data. Output of one flip flop become the input of other[8]. Figure 2: Truth Table of SIPO Parallel In and Parallel Out shift register is the type of shift register in which data will load and retrieve in parallel mode. Below Figure 4 is shown how PIPO is working. Figure 4: Parallel In Parallel Out Shift Register. Its working is extremely straightforward when contrasted with other shift registers. As shown in the Figure 1 all flip flops are connected with CLEAR. CLEAR is used to clear or reset the flip flop so that if there is any previous data stored in it will be removed and it can be used for future purposes. First Step is to CLEAR all the flip flops and output from Q 0 to Q 3 are at logic'0'. Next step is to provide CLOCK to every flip flop. When logic '1' given to the CLOCK then shift register starts working. Input D 0 is given to the first D flip flop and output is taken from the Q 0. Likewise all the four flip flops are connected and inputs are given corresponding to all the four flip flops. D 1 input is given to the second flip flop and output is taken from the Q 1. D 2 input is given to the third flip flop and output will be taken from Q 2. D 3 input is given to the last flip flop and output will be taken from Q 3. Let us take an example for better understanding. Suppose we have data 0100 i. e D 0 '0', D 1 '1', D 2 '0', D 3 '0' then after one clock pulse output will be Q 0 '0', Q 1 '1', Q 2 '0', Q 3 '0' [9]. This is shown that we need only one clock pulse to enter the given data and output in 0 clock pulse because it work in parallel mode it will give the output as soon as input is received. As shown in Truth Table Initially shift register was RESET. When CLOCK signal is provided then only shifting of data takes place. In first clock pulse 1 is shifted from first flip flop to second. In second clock pulse that one is shifted to the third flip flop and first flop will get new data[10]. Likewise process keeps on going and at last all the flip flops will get some data i. e '1111'. The clock is used to shift data one place to the right side. Figure 3: Waveform of SIPO The above shown truth table of SIPO explains that when no clock signal is provided, no output is achieved. When clock is applied QA becomes high and other remains low i.e. 0. At the second clock pulse, QB will become high and other remains low. When third clock pulse arrives, QC becomes high and other remains low. A last clock pulse QD becomes high and other becomes low. Figure 5: Truth-Table of Shift Register. 484 IJREAMV04I0339123 DOI : 10.18231/2454-9150.2018.0367 2018, IJREAM All Rights Reserved.

III. SIMULATION & RESULTS In DSCH software it deals with graphical or circuit diagram where focus is to draw circuit diagram and apply inputs and outputs respectively. As shown below the circuit diagram of SIPO having clock and clear along with inputs and outputs. From DSCH verilog file is generated. Figure 9: Fully-automatic SIPO Below shown are simulation result of layout structure in Microwind. In this waveforms are shown with respect to different inputs respective outputs are shown. Figure 6: DSCH design of SIPO Working of SIPO in DSCH software is shown in below Figure 7. When clock signal is given and corresponding inputs are given then their corresponding LEDs will glow. Figure 10: Voltage vs Time graph Figure 7: DSCH design of working SIPO Waveform generated in DSCH during its operation is shown in Figure 8. Serial data is given and parallel output is achieved by the circuit which is shown below. Figure 11: Voltage vs Current graph Figure 8: Waveform of SIPO Below shown in figure 9 is the result in Microwind software which is taken after compiling in Microwind. It gives the Layout structure. In DSCH software it deals with graphical or circuit diagram where focus is to draw circuit diagram and apply inputs and outputs respectively. As shown below the circuit diagram of PIPO having clock and clear along with inputs and outputs. From DSCH verilog file is generated. 485 IJREAMV04I0339123 DOI : 10.18231/2454-9150.2018.0367 2018, IJREAM All Rights Reserved.

Figure 14: Fully-automatic PIPO Figure 11: DSCH design of PIPO Working of PIPO in DSCH software is shown in below Figure 7. When clock signal is given and corresponding inputs are given then their corresponding LEDs will glow. Below shown are simulation result of layout structure in Microwind. In this waveforms are shown with respect to different inputs respective outputs are shown. Figure 15: Voltage vs Time graph Figure 12: DSCH design of working PIPO Waveform generated in DSCH during its operation is shown in Figure 8. Parallel data is given and parallel output is achieved by the circuit which is shown below. Figure 16: Voltage Vs Current graph Figure 17 shows semi-custom design of SIPO shifter where different D flip-flops are used to complete the circuit. D flip-flops are built using NAND gates. Overall area of this layout is reduced. Figure 13: Waveform of PIPO Below shown in figure 14 is the result in Microwind software which is taken after compiling in Microwind. It gives the Layout structure. Figure 17:Semi-custom SIPO. 486 IJREAMV04I0339123 DOI : 10.18231/2454-9150.2018.0367 2018, IJREAM All Rights Reserved.

Figure 18: Voltage vs Time graph Figure 21: Voltage vs Time graph Figure 18,19 shows the simulation result of semi-custom layout design of SIPO shifter. Different waveforms are shown with respect to different inputs their respective outputs are shown. Figure 22: Voltage vs Current graph Figure 19: Voltage Vs Current graph Figure 20 shows semi-custom design of PIPO shifter where different D flip-flops are used to complete the circuit. D flip-flops are built using NAND gates. Overall area of this layout is reduced. Table 1: Area and Power consideration. Serial In Parallel Out Method Technology(nm) Area (µm 2 ) Power (µw) Fullyautomatic 90 228.4 9.85 Semi-custom 90 117.5 9.136 Parallel In Parallel Out Method Technology(nm) Area (µm 2 ) Power (µw) Fullyautomatic 90 248.5 6.211 Semi-custom 90 117.5 6.052 Figure. 20: Semi-custom PIPO. Figure 21,22 shows the simulation result of semi-custom layout design of SIPO shifter. Different waveforms are shown with respect to different inputs their respective outputs are shown. The parameters under consideration are area and power. Table 1 shows area and power consumption of 4 bit Serial In Parallel Out and Parallel In Parallel Out shift register. V.CONCLUSION The analysis of two different shifters with same technologies is done in this paper. As shown Fullyautomatic and Semi-custom layout design are generated for 4 bit SIPO and PIPO to analyze area and power consumption. In semi-custom method, SIPO area is reduced by 110.9 µm 2 whereas in PIPO area is reduced by 131 µm 2. In semi-custom method, SIPO power is reduced by 0.69 µw whereas in PIPO power is reduced by 0.159 µw. It is well known that as computation point of view PIPO is used. Because it consumes less power as compared to SIPO. From the above simulation it can be analyze that semi custom design is more efficient in terms of area and power. Where area minimization is essential in those applications semi-custom design can be implemented. 487 IJREAMV04I0339123 DOI : 10.18231/2454-9150.2018.0367 2018, IJREAM All Rights Reserved.

VI. ACKNOWLEDGEMENT The authors would like to thank the Director, National Institute of Technical Teachers Training & Research, Chandigarh, India for continuous support throughout this research work. REFRENCES [1] Borivoje Nikolic, Design in the Power Limited Scaling Regime, IEEE Transactions on Electron Devices, Vol.55, No. 1, pp.71-83, 2008. [2] International Technology : Roadmap for Semiconductors:www.itrs.net/Links/2005ITRS/Design 2005.pdf. [3] N. A. Whitaker, Jr, M. C. Gabriel, H.Avramopoulos, and A. Huang All-optical, all-fiber circulating shift register with an inverter, Optics Letters, Vol. 16, Issue 24, pp. 1999-2001,1991 [4] Davida, G.I. and Rodrigues, Data Compression Using Linear Feedback Shift Registers, Proceedings of the IEEE Data Compression Conference, Los Alamitos, 1994 [5] Moon, T. K. and Veeramachaneni. S. Linear Feedback Shift Registers as Vector Quantisation Codebooks, Electronics Letters, Vol. 35, No. 22, pp. 1919-1920,1999 [6] Deepak subramanyan, B.S. and Adrian Nunez, Analysis of Sub-threshold Leakage Reduction in CMOS Digital Circuits, Proceedings of the 13th NASA VLSI Symposium, USA, June 5-6,2007 [7] Wayne Wolf, Modern VLSI Design (System on chip Design), Pearson Education, pp. 319-321. [8] Akhilesh Verma, Rajesh Mehra, Design and Analysis of Conventional and Ratioed Cmos Logic Circuit IOSR Journal of VLSI and Signal Processing Vol.2, pp. 25-29, April 2013 [9] Harmeet Singh Efficient Layout Design of CMOS Full Subtractor Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015). [10] Monikashree T.S,Usharani.S, Dr.J.S.Baligar Design and Implementation of Full Subtractor using CMOS 180nm Technology International Journal of Science, Engineering and Technology Research (IJSETR), pp 1421-1426, Vol. 3, Issue 5, May 2014. 488 IJREAMV04I0339123 DOI : 10.18231/2454-9150.2018.0367 2018, IJREAM All Rights Reserved.

2024 © artsdocbox.com Privacy Policy | Terms of Service | Feedback