Microprocessor Design

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Transcription:

Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004

To my wife and children Windy, Jonathan and Michelle

Contents 1. Designing a Microprocessor... 2 1.1 Overview of a Microprocessor... 2 1.2 Design Abstraction Levels... 4 1.3 Examples for a 2-input Multiplexer... 4 1.3.1 Behavioral Level... 5 1.3.2 Gate Level... 6 1.3.3 Transistor Level... 6 1.4 VHDL... 7 1.5 Synthesis... 8 1.6 Going Forward... 9 1.7 Summary Checklist... 9 Index... 11 2 Digital Circuits... 2 2.1 Binary Numbers... 2 2.2 Binary Switch... 4 2.3 Basic Logic Operators and Logic Expressions... 5 2.4 Truth Tables... 6 2.5 Boolean Algebra and Boolean Function... 6 2.5.1 Boolean Algebra... 6 2.5.2 Duality Principle... 8 2.5.3 Boolean Function and the Inverse... 9 2.6 Minterms and Maxterms... 12 2.6.1 Minterms... 12 2.6.2 Maxterms... 13 2.7 Canonical, Standard, and non-standard Forms... 15 2.8 Logic Gates and Circuit Diagrams... 15 2.9 Example: Designing a Car Security System... 17 2.10 Introduction to VHDL... 19 2.10.1 VHDL code for a 2-input NAND gate... 19 2.10.2 VHDL code for a 3-input NOR gate... 20 2.10.3 VHDL code for a function... 21 2.11 Summary Checklist... 22 2.12 Exercises... 23 Index 27 3 Combinational Circuits... 2 3.1 Analysis of Combinational Circuits... 2 3.1.1 With a Truth Table... 2 3.1.2 With a Boolean Function... 4 3.2 Synthesis of Combinational Circuits... 5 3.3 Technology Mapping... 7 3.4 Minimization of Combinational Circuits... 10 3.4.1 Karnaugh (K) Maps... 10 3.4.2 Don t-cares... 15 3.4.3 * Quine-McCluskey (Tabulation) Method... 16 3.5 * Timing Hazards and Glitches... 17 3.6 7-Segment Decoder Example... 18 3.7 VHDL Code for Combinational Circuits... 20 3.7.1 Structural BCD to 7-Segment Decoder... 21 3.7.2 Dataflow BCD to 7-Segment Decoder... 24 3.7.3 Behavioral BCD to 7-Segment Decoder... 25 3.8 Summary Checklist... 26 - v -

3.9 Exercises... 28 Index... 30 4 Combinational Components... 2 4.1 Signal Naming Conventions... 2 4.2 Adder... 2 4.2.1 Full Adder... 2 4.2.2 Ripple-Carry Adder... 4 4.2.3 Carry-Lookahead Adder... 5 4.3 Two s-complement Representation for Negative Numbers... 6 4.4 Subtractor... 6 4.4.1 Adder-Subtractor Combination... 9 4.5 Arithmetic Logic Unit... 12 4.6 Decoder... 16 4.7 Encoder... 17 4.7.1 Priority Encoder... 18 4.8 Multiplexer... 19 4.8.1 Using Multiplexers to Implement a Function... 22 4.9 Tri-state Buffer... 22 4.10 Comparators... 24 4.11 Shifter-Rotator... 25 4.12 Multiplier... 27 4.13 Summary Checklist... 28 4.14 Exercises... 29 Index... 30 5 Implementation Technologies... 2 5.1 Physical Abstraction... 2 5.2 Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)...3 5.3 CMOS Logic... 4 5.4 CMOS Circuits... 5 5.4.1 CMOS Inverter... 5 5.4.2 CMOS NAND gate... 6 5.4.3 CMOS AND gate... 7 5.4.4 CMOS NOR and OR Gates... 9 5.4.5 Transmission Gate... 9 5.4.6 2-input Multiplexer CMOS Circuit... 9 5.4.7 CMOS XOR and XNOR Gates... 11 5.5 Analysis of CMOS Circuits... 12 5.6 Using ROMs to Implement a Function... 13 5.7 Using PLAs to Implement a Function... 15 5.8 Using PALs to Implement a Function... 19 5.9 Complex Programmable Logic Device (CPLD)... 21 5.10 Field-Programmable Gate Array (FPGA)... 23 5.11 Summary Checklist... 24 5.12 References... 24 5.13 Exercises... 25 Index... 26 6 Latches and Flip-Flops... 2 6.1 Bistable Element... 2 6.2 SR Latch... 4 6.3 SR Latch with Enable... 6 6.4 D Latch... 7 6.5 D Latch with Enable... 7 6.6 Clock... 8 - vi -

6.7 D Flip-Flop... 10 6.8 D Flip-Flop with Enable... 12 6.9 Asynchronus Inputs... 13 6.10 Description of a Flip-Flop... 13 6.10.1 Characteristic Table... 13 6.10.2 Characteristic Equation... 14 6.10.3 State Diagram... 14 6.10.4 Excitation Table... 14 6.11 Timing Issues... 15 6.12 Example: Car Security System Version 2... 16 6.13 VHDL for Latches and Flip-Flops... 16 6.13.1 Implied Memory Element... 16 6.13.2 VHDL Code for a D Latch with Enable... 17 6.13.3 VHDL Code for a D Flip-Flop... 18 6.13.4 VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear... 21 6.14 * Flip-Flop Types... 22 6.14.1 SR Flip-Flop... 22 6.14.2 JK Flip-Flop... 23 6.14.3 T Flip-Flop... 23 6.15 Summary Checklist... 25 6.16 Exercises... 26 Index... 27 7 Sequential Circuits... 2 7.1 Finite-State-Machine (FSM) Model... 2 7.2 Analysis of Sequential Circuits... 3 7.2.1 Excitation Equation... 4 7.2.2 Next-state Equation... 5 7.2.3 Next-state Table... 5 7.2.4 Output Equation... 6 7.2.5 Output Table... 6 7.2.6 State Diagram... 6 7.2.7 Example: Analysis of a Moore FSM... 7 7.2.8 Example: Analysis of a Mealy FSM... 9 7.3 Synthesis of Sequential Circuits... 11 7.3.1 State Diagram... 11 7.3.2 Next-state Table... 12 7.3.3 Implementation Table... 13 7.3.4 Excitation Equation and Next-state Circuit... 14 7.3.5 Output Table and Equation... 14 7.3.6 FSM Circuit... 15 7.3.7 Examples: Synthesis of Moore FSMs... 15 7.3.8 Example: Synthesis of a Mealy FSM... 20 7.4 Unused State Encodings... 22 7.5 Example: Car Security System Version 3... 22 7.6 VHDL for Sequential Circuits... 24 7.7 * Optimization for Sequential Circuits... 29 7.7.1 State Reduction... 29 7.7.2 State Encoding... 30 7.7.3 Choice of Flip-Flops... 31 7.8 Exercises... 33 7.9 Selected Answers... 35 Index... 39 8 Sequential Components... 2 8.1 Registers... 2 - vii -

8.2 Shift Registers... 3 8.2.1 Serial to Parallel Shift Register... 3 8.2.2 Serial-to-Parallel and Parallel-to-Serial Shift Register... 5 8.3 Counters... 6 8.3.1 Binary Up Counter... 7 8.3.2 Binary Up-Down Counter... 9 8.3.3 Binary Up-Down Counter with Parallel Load... 11 8.3.4 BCD Up-Down Counter... 11 8.4 Register Files... 13 8.5 Static Random Access Memory... 15 8.6 Larger Memories... 18 8.6.1 More Memory Locations... 18 8.6.2 Wider Bit Width... 19 Index... 20 9 Datapaths... 2 9.1 General Datapath... 3 9.2 Using a General Datapath... 5 9.3 Timing Issues... 7 9.4 A More Complex General Datapath... 9 9.5 VHDL for the Complex General Datapath... 12 9.6 Dedicated Datapath... 17 9.6.1 Selecting Registers... 17 9.6.2 Selecting Functional Units... 18 9.6.3 Data Transfer Methods... 18 9.7 Examples: Designing Dedicated Datapaths... 20 9.8 Using a Dedicated Datapath... 25 9.9 VHDL for a Dedicated Datapath... 25 9.10 * Optimization for Datapaths... 27 9.10.1 Functional Unit Sharing... 27 9.10.2 Register Sharing... 27 9.10.3 Bus Sharing... 27 9.11 Summary Checklist... 27 Index... 28 10 Control Units... 2 10.1 Constructing the Control Unit... 3 10.2 Generating Status Signals... 11 10.3 Timing Issues... 13 10.4 ASM Charts and State Action Tables... 16 10.4.1 ASM Charts... 17 10.4.2 State Action Tables... 20 10.5 Summary Checklist... 22 10.6 Exercises... 23 Index... 24 11 Dedicated Microprocessors... 2 11.1 Manual Construction of a Dedicated Microprocessor... 3 11.2 FSM + D Model Using VHDL... 6 11.3 FSMD Model... 11 11.4 Behavioral Model... 13 11.5 Examples... 15 Index... 22 12 General-Purpose Microprocessors... 2 12.1 Overview of the CPU Design... 2 - viii -

12.2 Instruction Set... 2 12.2.1 Two Operand Instructions... 3 12.2.2 One Operand Instructions... 3 12.2.3 Instructions Using a Memory Address... 3 12.2.4 Jump Instructions... 3 12.3 Datapath... 5 12.3.1 Input multiplexer... 6 12.3.2 Conditional Flags... 6 12.3.3 Accumulator... 6 12.3.4 Register File... 6 12.3.5 ALU... 6 12.3.6 Shifter / Rotator... 7 12.3.7 Output Buffer... 7 12.3.8 Control Word... 7 12.3.9 VHDL Code for the Datapath... 8 12.4 Control Unit... 9 12.4.1 Reset... 10 12.4.2 Fetch... 10 12.4.3 Decode... 10 12.4.4 Execute... 10 12.4.5 VHDL Code for the Control Unit... 11 12.5 CPU... 20 12.6 Top-level Computer... 22 12.6.1 Input... 22 12.6.2 Output... 22 12.6.3 Memory... 22 12.6.4 Clock... 23 12.6.5 VHDL Code for the Complete Computer... 23 12.7 Examples... 24 Appendix A VHDLSummary... 2 A.1 Basic Language Elements... 2 A.1.1 Comments... 2 A.1.2 Identifiers... 2 A.1.3 Data Objects... 2 A.1.4 Data Types... 2 A.1.5 Data Operators... 5 A.1.6 ENTITY... 5 A.1.7 ARCHITECTURE... 6 A.1.8 GENERIC... 7 A.1.9 PACKAGE... 8 A.2 Dataflow Model Concurrent Statements... 9 A.2.1 Concurrent Signal Assignment... 9 A.2.2 Conditional Signal Assignment... 9 A.2.3 Selected Signal Assignment... 10 A.2.4 Dataflow Model Example... 10 A.3 Behavioral Model Sequential Statements... 10 A.3.1 PROCESS... 10 A.3.2 Sequential Signal Assignment... 11 A.3.3 Variable Assignment... 11 A.3.4 WAIT... 11 A.3.5 IF THEN ELSE... 12 A.3.6 CASE... 12 A.3.7 NULL... 13 A.3.8 FOR... 13 A.3.9 WHILE... 13 - ix -

A.3.10 LOOP... 13 A.3.11 EXIT... 14 A.3.12 NEXT... 14 A.3.13 FUNCTION... 14 A.3.14 PROCEDURE... 15 A.3.15 Behavioral Model Example... 16 A.4 Structural Model Statements... 16 A.4.1 COMPONENT Declaration... 16 A.4.2 PORT MAP... 17 A.4.3 OPEN... 17 A.4.4 GENERATE... 17 A.4.5 Structural Model Example... 18 A.5 Conversion Routines... 19 A.5.1 CONV_INTEGER()... 19 A.5.2 CONV_STD_LOGIC_VECTOR(,)... 19 Index... 21 Appendix B MAX+plus II Tutorial 1... 2 B.1 Getting Started... 2 B.1.1 Preparing a Folder for the Project... 2 B.1.2 Starting MAX+plus II... 2 B.1.3 Creating a Project... 3 B.1.4 Editing the VHDL Source Code... 4 B.2 Synthesis for Functional Simulation... 4 B.3 Circuit Simulation... 5 B.3.1 Selecting Input Test Signals... 5 B.3.2 Customizing the Waveform Editor... 6 B.3.3 Assigning Values to the Input Signals... 7 B.3.4 Saving the Waveform File... 7 B.3.5 Starting the Simulator... 8 Appendix C MAX+plus II Tutorial 2... 2 C.1 Getting Started... 2 C.1.1 Preparing a Folder for the Project... 2 C.1.2 Creating a Project... 2 C.1.3 Editing the VHDL Source Code... 2 C.2 Synthesis for Functional Simulation... 3 C.3 Circuit Simulation... 3 C.4 Using the Floorplan Editor... 4 C.4.1 Selecting the Target Device... 4 C.4.2 Maping the I/O Pins with the Floorplan Editor... 5 C.5 Synthesis for Programming the PLD... 6 C.5.1 Bringing Up the Compiler Window... 6 C.6 Programming the FPGA... 7 C.6.1 Connecting and Configuring the UP2 Board... 7 C.6.2 I/O Connections for the Circuit... 8 C.6.3 Programming the PLD... 8 C.7 Testing the Hardware... 8 - x -

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