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E2O2-27-X3 Semiconductor MSM2C55A-2RS/GS/VJS This version: Jan. 99 Previous version: Aug. 996 CMOS PROGRAMMABLE PERIPHERAL INTERFACE This product is not available in Asia and Oceania. GENERAL DESCRIPTION The MSM2C55A-2 is a programmable universal I/O interface device which operates as high speed and on low power consumption due to 3m silicon gate CMOS technology. It is the best fit as an I/O port in a system which employs the -bit parallel processing MSMC5AH CPU. This device has 24-bit I/O pins equivalent to three -bit I/O ports and all inputs/outputs are TTL interface compatible. FEATURES High speed and low power consumption due to 3m silicon gate CMOS technology 3 V to 6 V single power supply Full static operation Programmable 24-bit I/O ports Bidirectional bus operation (Port A) Bit set/reset function (Port C) TTL compatible Compatible with 255A-5 4-pin Plastic DIP (DIP4-P-6-2.54): (Product name: MSM2C55A-2RS) 44-pin Plastic QFJ (QFJ44-P-S65-.27): (Product name: MSM2C55A-2VJS) 44-pin Plastic QFP (QFP44-P-9-.-2K): (Product name: MSM2C55A-2GS-2K) /26

CIRCUIT CONFIGURATION V CC GND D - D 7 RD WR RESET CS Data Bus Buffer Read/ Write Control Logic Group A Control Group B Control Internal Bus Line 4 4 Group A Port A () Group A Port C (High Order 4 Bits) Group B Port C (Low Order 4 Bits) Group B Port B () 4 4 PA - PA 7 PC 4 - PC 7 PC - PC 3 PB - PB 7 A A 2/26

PIN CONFIGURATION (TOP VIEW) 4 pin Plastic DIP CS GND A A PC 7 PC 6 PC 5 PC 4 PC PC PC 2 2 3 4 5 6 7 9 44 pin Plastic QFP 33 32 3 3 29 2 27 26 25 24 23 RESET D D D 2. D 3 D 4 D 5 D 6 D 7 V CC PB 7 PA 3 PA 2 PA PA RD CS GND A A PC 7 PC 6 PC 5 PC 4 PC PC PC 2 PC 3 PB PB PB 2 2 3 4 5 6 7 9 2 3 4 5 6 7 9 2 44 pin Plastic QFJ 4 PA 4 39 PA 5 3 PA 6 37 PA 7 36 WR 35 RESET 34 D 33 D 32 D 2 3 D 3 3 D 4 29 D 5 2 D 6 27 D 7 26 V CC 25 PB 7 24 PB 6 23 PB 5 22 PB 4 2 PB 3 CS 7 GND A 9 A PC 7 NC 2 PC 6 3 PC 5 4 PC 4 5 PC 6 PC 7 39 RESET 3 D 37 D 36 D 2. 35 D 3 34 NC 33 D 4 32 D 5 3 D 6 3 D 7 29 V CC PC2 PC3 PB PB PB2 NC PB3 PB4 PB5 PB6 PB7 9 2 2 22 23 24 25 26 27 2 6 5 4 3 2 44 43 42 4 4 NC PC3 PB PB PB2 VCC PB3 RD PA PA PA2 PA3 NC PA4 PA5 RD PA PA PA2 PA3 VCC PA4 PA6 PA7 WR 44 43 42 4 4 39 3 2 3 4 5 6 7 PA5 37 PB4 PB5 9 PA6 36 2 2 22 PB6 NC PA7 WR 35 34 3/26

ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions MSM2C55A-2RS Rating Unit MSM2C55A-2GS MSM2C55A-2vJS Supply Voltage V CC Ta = 25 C.5 to +7 V Voltage V IN with respect.5 to V CC +.5 V Voltage V OUT to GND.5 to V CC +.5 V Storage Temperature T STG 55 to +5 C Power Dissipation P D Ta = 25 C..7. W OPERATING RANGE Parameter Symbol Range Unit Supply Voltage V CC 3 to 6 V Operating Temperature T op 4 to 5 C RECOMMENDED OPERATING RANGE Parameter Symbol Min. Typ. Max. Unit Supply Voltage V CC 4.5 5 5.5 V Operating Temperature T op 4 +25 +5 C "L" Voltage V IL.3 +. V "H" Voltage V IH 2.2 V CC +.3 V DC CHARACTERISTICS Parameter Symbol Conditions MSM2C55A-2 Min. Typ. Max. Unit "L" Voltage V OL I OL = 2.5 ma.4 V "H" Voltage V OH I OH = 4 ma 4.2 V I OH = 2.5 ma 3.7 V Leak Current I LI V IN V CC V CC = 4.5 V to 5.5 V ma Leak Current I LO V OUT V CC Ta = 4 C to +5 C ma (C L = pf) Supply Current CS V CC.2 V (Standby) I CCS V IH V CC.2 V V IL.2 V. ma Average Supply Current (Active) I CC I/O Wire Cycle 2C55A-2... MHzCPU Timing ma 4/26

AC CHARACTERISTICS (V CC = 4.5 V to 5.5 V, Ta = 4 to +5 C) Parameter Symbol MSM2C55A-2 Min. Max. Unit Setup Time of Address to the Falling Edge of RD t AR 2 ns Hold Time of Address to the Rising Edge of RD t RA ns RD Pulse Width t RR ns Delay Time from the Falling Edge of RD to the of Defined Data Delay Time from the Rising Edge of RD to the Floating of Data Bus Time from the Rising Edge of RD or WR to the Next Falling Edge of RD or WR t RD 2 ns t DF 75 ns t RV 2 ns Setup Time of Address before the Falling Edge of WR t AW ns Hold Time of Address after the Rising Edge of WR t WA 2 ns WR Pulse Width t WW 5 ns Setup Time of Bus Data before the Rising Edge of WR t DW 5 ns Hold Time of Bus Data after the Rising Edge of WR t WD 3 ns Delay Time from the rising Edge of WR to the of Defined Data t WB 2 ns Setup Time of Port Data before the Falling Edge of RD t IR 2 ns Hold Time of Port Data after the Rising Edge of RD t HR ns ACK Pulse Width t AK ns STB Pulse Width t ST ns Setup Time of Port Data before the rising Edge of STB t PS 2 ns Hold Time of Port Bus Data after the rising Edge of STB t PH 5 ns Delay Time from the Falling Edge of ACK to the of Defined Data Delay Time from the Rising Edge of ACK to the Floating of Port (Port A in Mode 2) Delay Time from the Rising Edge of WR to the Falling Edge of OBF Delay Time from the Falling Edge of ACK to the Rising Edge of OBF Delay Time from the Falling Edge of STB to the Rising Edge of IBF Delay Time from the Rising Edge of RD to the Falling Edge of IBF Delay Time from the the Falling Edge of RD to the Falling Edge of INTR Delay Time from the Rising Edge of STB to the Rising Edge of INTR Delay Time from the Rising Edge of ACK to the Rising Edge of INTR Delay Time from the Falling Edge of WR to the Falling Edge of INTR t AD 5 ns t KD 2 25 ns t WOB 5 ns t AOB 5 ns t SIB 5 ns t RIB 5 ns t RIT 2 ns t SIT 5 ns t AIT 5 ns t WIT 25 ns Remarks Load 5 pf Note: Timing measured at V L =. V and V H = 2.2 V for both inputs and outputs. 5/26

TIMING DIAGRAM Basic Operation (Mode ) RD Port t IR t RR t HR t AR t RA CS, A, A D 7 - D t RD t DF Basic Operation (Mode ) WR t WW t DW t WD D 7 - D t AW t WA CS, A, A Port t WB Strobe Operation (Mode ) STB t ST IBF INTR t SIB t SIT t RIT t RIB RD Port t PH t PS 6/26

Strobe Operation (Mode ) WR OBF t AOB INTR ACK Port t WIT t WOB t AK t AIT t WB Bidirectional Bus Operation (Mode 2) WR OBF t AOB INTR t WOB t AK ACK t ST STB IBF Port A t SIB t PS t AD t KD RD t PH t RIB 7/26

OUTPUT CHARACTERISTICS (REFERENCE VALUE) "H" Voltage (V OH ) vs. Current (I OH ) 5 "H" Voltage VOH (V) 4 3 2 Ta = 4 to + 5 C V CC = 5. V 2 3 4 5 Current I OH (ma) 2 "L" Voltage (V OL ) vs. Current (I OL ) 5 "L" Voltage VOL (V) 4 3 2 V CC = 5. V Ta = 4 to +5 C 2 3 4 5 Current I OL (ma) Note: The direction of flowing into the device is taken as positive for the output current. /26

PIN DESCRIPTION Pin No. Item / Function D 7 - D Bidirectional Data Bus and These are three-state -bit bidirectional buses used to write and read data upon receipt of the WR and RD signals from CPU and also used when control words and bit set/reset data are transferred from CPU to MSM2C55A-2. RESET Reset This signal is used to reset the control register and all internal registers when it is in high level. At this time, ports are all made into the input mode (high impedance status). all port latches are cleared to. and all ports groups are set to mode. CS Chip Select When the CS is in low level, data transmission is enabled with CPU. When it is in high level, the data bus is made into the high impedance status where no write nor read operation is performed. Internal registers hold their previous status, however. RD Read WR Write When RD is in low level, data is transferred from MSM2C55A-2 to CPU. When WR is in low level, data or control words are transferred from CPU to MSM2C55A-2. A, A Port Select (Address) By combination of A and A, either one is selected from among port A, port B, port C, and control register. These pins are usually connected to low order 2 bits of the address bus. PA 7 - PA Port A and These are universal -bit I/O ports. The direction of inputs/ outputs can be determined by writing a control word. Especially, port A can be used as a bidirectional port when it is set to mode 2. PB 7 - PB Port B and These are universal -bit I/O ports. The direction of inputs/outputs ports can be determined by writing a control word. PC 7 - PC Port C and These are universal -bit I/O ports. The direction of inputs/outputs can be determined by writing a control word as 2 ports with 4 bits each. When port A or port B is used in mode or mode 2 (port A only), they become control pins. Especially, when port C is used as an output port, each bit can set/reset independently. V CC +5V power supply. GND GND 9/26

BASIC FUNCTIONAL DESCRIPTION Group A and Group B When setting a mode to a port having 24 bits, set it by dividing it into two groups of 2 bits each. Group A: Port A ( bits) and high order 4 bits of port C (PC 7 ~PC 4 ) Group B: Port B ( bits) and low order 4 bits of port C (PC 3 ~PC ) Mode,, 2 There are 3 types of modes to be set by grouping as follows: Mode : Basic input operation/output operation (Available for both groups A and B) Mode : Strobe input operation/output operation (Available for both groups A and B) Mode 2: Bidirectional bus operation (Available for group A only) When used in mode or mode 2, however, port C has bits to be defined as ports for control signal for operation ports (port A for group A and port B for group B) of their respective groups. Port A, B, C The internal structure of 3 ports is as follows: Port A: One -bit data output latch/buffer and one -bit data input latch Port B: One -bit data input/output latch/buffer and one -bit data input buffer Port C: One -bit data output latch/buffer and one -bit data input buffer (no latch for input) Single bit set/reset function for port C When port C is defined as an output port, it is possible to set (to turn to high level) or reset (to turn to low level) any one of bits individually without affecting other bits. /26

OPERATIONAL DESCRIPTION Control Logic Operations by addresses and control signals, e.g., read and write, etc. are as shown in the table below: Operaiton A A CS WR RD Operation Port A Æ Data Bus Control Others Port B Æ Data Bus Port C Æ Data Bus Data Bus Æ Port A Data Bus Æ Port B Data Bus Æ Port C Data Bus Æ Control Register Illegal Condition Data bus is in the high impedance status. Setting of Control Word The control register is composed of 7-bit latch circuit and -bit flag as shown below. Group A Control Bits Group B Control Bits D 7 D 6 D 5 D 4 D 3 D 2 D D Definition of input/ output of low order 4 bits of port C. Definition of input/ output of bits of port B. Mode definition of group B. Definition of input/ output of high order 4 bits of port C. Definition of input/ output of bits of port A. Mode definition of group A. = = = = = Mode = Mode = = = = Control word Identification flag Be sure to set for the control word to define a mode and input/output. When set to, it becomes the control word for bit set/ reset. D 6 D 5 Mode Mode Mode Mode 2 /26

Precaution for Mode Selection The output registers for ports A and C are cleared to f each time data is written in the command register and the mode is changed, but the port B state is undefined. Bit Set/Reset Function When port C is defined as output port, it is possible to set (set output to ) or reset (set output to ) any one of bits without affecting other bits as shown below. D 7 D 6 D 5 D 4 D 3 D 2 D D Definition of set/reset for a desired bit. = Reset = Set Definition of bit wanted to be set or reset. Dont's Care Control word Identification flag Be sure to set to for bit set/reset When set to, it becomes the control word to define a mode and input/output. Port C PC PC PC2 PC3 PC4 PC5 PC6 PC7 D 3 D 2 D Interrupt Control Function When the MSM2C55A-2 is used in mode or mode 2, the interrupt signal for the CPU is provided. The interrupt request signal is output from port C. When the internal flip-flop INTE is set beforehand at this time, the desired interrupt request signal is output. When it is reset beforehand, however, the interrupt request signal is not output. The set/reset of the internal flip-flop is made by the bit set/reset operation for port C virtually. Bit set Æ INTE is set Æ Interrupt allowed Bit reset Æ INTE is reset Æ Interrupt inhibited Operational Description by Mode. Mode (Basic input/output operation) Mode makes the MSM2C55A-2 operate as a basic input port or output port. No control signals such as interrupt request, etc. are required in this mode. All 24 bits can be used as two--bit ports and two 4-bit ports. Sixteen combinations are then possible for inputs/ outputs. The inputs are not latched, but the outputs are. 2/26

Control Word Group A Group B Type High Order 4 Bits Low Order 4 Bits Port A Port B D 7 D 6 D 5 D 4 D 3 D 2 D D of Port C of Port C 2 3 4 5 6 7 Ouput 9 2 3 4 5 6 Notes: When used in mode for both groups A and B 2. Mode (Strobe input/output operation) In mode, the strobe, interrupt and other control signals are used when input/output operations are made from a specified port. This mode is available for both groups A and B. In group A at this time, port A is used as the data line and port C as the control signal. Following is a description of the input operation in mode. STB (Strobe input) When this signal is low level, the data output from terminal to port is fetched into the internal latch of the port. This can be made independent from the CPU, and the data is not output to the data bus until the RD signal arrives from the CPU. IBF ( buffer full flag output) This is the response signal for the STB. This signal when turned to high level indicates that data is fetched into the input latch. This signal turns to high level at the falling edge of STB and to low level at the rising edge of RD. INTR (Interrupt request output) This is the interrupt request signal for the CPU of the data fetched into the input latch. It is indicated by high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the STB (IBF = at this time) and low level at the falling edge of the RD when the INTE is set. INTE A of group A is set when the bit for PC 4 is set, while INTE B of group B is set when the bit for PC 2 is set. Following is a description of the output operation of mode. 3/26

- - - - OBF ( buffer full flag output) This signal when turned to low level indicates that data is written to the specified port upon receipt of the WR signal from the CPU. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) This signal when turned to low level indicates that the terminal has received data. INTR (Interrupt request output) This is the signal used to interrupt the CPU when a terminal receives data from the CPU via the MSM2C55A-5. It indicates the occurrence of the interrupt in high level only when the internal INTE flip-flop is set. This signal turns to high level at the rising edge of the ACK (OBF = at this time) and low level at the falling edge of WR when the INTE B is set. INTE A of group A is set when the bit for PC 6 is set, while INTE B of group B is set when the bit for PC 2 is set. Mode (Group A) (Group B) PA 7 PB 7 INTE A PA INTE B PB PC 4 STB A PC 2 STB B PC 5 IBF A PC IBF B RD RD PC 3 INTR A PC INTR B Note: Although belonging to group B, PC 3 operates as the control signal of group A functionally. Mode (Group A) (Group B) PA 7 PB 7 INTE A PA INTE B PB PC 7 OBF A PC OBF B PC 6 ACK A PC 2 ACK B WR WR PC 3 INTR A PC INTR B 4/26

Port C Function Allocation in Mode Port C Combination of / PC PC PC 2 PC 3 PC 4 PC 5 PC 6 Group A: Group B: Group A: Group B: Group A: Group B: Group A: Group B: INTR B INTR B INTR B INTRB IBF B OBF B IBF B OBF B STB B ACK B STB B ACK B INTR A INTR A INTR A INTR A STB A STB A I/O I/O IBF A IBF A I/O I/O I/O I/O ACK A ACK A PC 7 I/O I/O OBF A OBF A Note: I/O is a bit not used as the control signal, but it is available as a port of mode. Examples of the relation between the control words and pins when used in mode are shown below: (a) When group A is mode output and group B is mode input. D 7 D 6 D 5 D 4 D 3 D 2 D D Control Word / Selection of I/O of PC 4 and PC 5 when not defined as a control pin. = = As all of PC - PC 3 bits become a control pin in this case, this bit is "Don't Care". WR PA 7 - PA PC 7 PC 6 PC 3 2 PC 4, PC 5 PB 7 - PB OBF A ACK A INTR A I/O Group A: Mode Group B: Mode RD PC 2 PC PC STB B IBF B INTR B 5/26

(b) When group A is mode input and group B is mode output. D 7 D 6 D 5 D 4 D 3 D 2 D D / RD WR PA 7 - PA PC 4 PC 5 PC 3 2 PC 6, PC 7 PB 7 - PB PC PC 2 PC Selection of I/O of PC 6 and PC 7 when not defined as a control pin. = = STB A IBF A INTR A I/O OBF B ACK B INTR B Group A: Mode Group B: Mode 3. Mode 2 (Strobe bidirectional bus I/O operation) In mode 2, it is possible to transfer data in 2 directions through a single -bit port. This operation is akin to a combination between input and output operations. Port C waits for the control signal in this case, too. Mode 2 is available only for group A, however. Next, a description is made on mode 2. OBF ( buffer full flag output) This signal when turned to low level indicates that data has been written to the internal output latch upon receipt of the WR signal from the CPU. At this time, port A is still in the high impedance status and the data is not yet output to the outside. This signal turns to low level at the rising edge of the WR and high level at the falling edge of the ACK. ACK (Acknowledge input) When a low level signal is input to this pin, the high impedance status of port A is cleared, the buffer is enabled, and the data written to the internal output latch is output to port A. When the input returns to high level, port A is made into the high impedance status. STB (Strobe input) When this signal turns to low level, the data output to the port from the pin is fetched into the internal input latch. The data is output to the data bus upon receipt of the RD signal from the CPU, but it remains in the high impedance status until then. IBF ( buffer full flag output) This signal when turned to high level indicates that data from the pin has been fetched into the input latch. This signal turns to high level at the falling edge of the STB and low level at the rising edge of the RD. 6/26

- INTR (Interrupt request output) This signal is used to interrupt the CPU and its operation in the same as in mode. There are two INTE flip-flops internally available for input and output to select either interrupt of input or output operation. The INTE is used to control the interrupt request for output operation and it can be reset by the bit set for PC6. INTE2 is used to control the interrupt request for the input operation and it can be set by the bit set for PC4. Mode 2 I/O Operation PC 3 PA 7 INTR A PA PC 7 INTE PC6 OBF A ACK A WR RD INTE 2 PC 4 STB A PC 5 IBF A Port C Function Allocation in Mode 2 Port C PC PC Function Confirmed to the Group B Mode PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 INTR A STBA IBF A ACK A OBF A Following is an example of the relation between the control word and the pin when used in mode 2. When input in mode 2 for group A and in mode for group B. 7/26

D 7 D 6 D 5 D 4 D 3 D 2 D D As all of bits of port C become control pins in this case, D 3 and D bits are treated as "Don't Care". No I/O specification is required for mode 2, since it is a bidirectional operation. This bit is therefore treated as "Don't Care". When group A is set to mode 2, this bit is treated as "Don't Care". PC 3 PA 7 - PA INTR A PC 7 OBF A PC 6 ACK A PC 4 PC 5 STB A IBF A Group A: Mode 2 Group B: Mode RD WR PB7 - PB PC 2 PC PC STB B IBF B INTR B /26

4. When Group A is Different in Mode from Group B Group A and group B can be used by setting them in different modes each other at the same time. When either group is set to mode or mode 2, it is possible to set the one not defined as a control pin in port C to both input and output as port which operates in mode at the 3rd and th bits of the control word. (Mode combinations that define no control bit at port C) Group A Group B Port C PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC PC Mode input Mode I/O I/O IBF A STB A INTR A I/O I/O I/O 2 Mode Mode OBF A ACK A I/O I/O INTR A I/O I/O I/O 3 Mode Mode I/O I/O I/O I/O I/O STB B IBF B INTR B 4 Mode Mode I/O I/O I/O I/O I/O ACK B OBF B INTR B 5 Mode Mode I/O I/O IBF A STB A INTR A STB B IBF B INTR B 6 Mode Mode I/O I/O IBF A STB A INTR A ACK B OBF B INTR B 7 Mode Mode OBF A ACK A I/O I/O INTR A STB B IBF B INTR B Mode Mode OBF A ACK A I/O I/O INTR A ACK B OBF B INTR B 9 Mode 2 Mode OBF A ACK A IBF A STB A INTR A I/O I/O I/O Controlled at the 3rd bit (D 3 ) of the Control Word Controlled at the th bit (D ) of the Control Word When the I/O bit is set to input in this case, it is possible to access data by the normal port C read operation. When set to output, PC 7 -PC 4 bits can be accessed by the bit set/reset function only. Meanwhile, 3 bits from PC 2 to PC can be accessed by normal write operation. The bit set/reset function can be used for all of PC 3 -PC bits. Note that the status of port C varies according to the combination of modes like this. 9/26

5. Port C Status Read When port C is used for the control signal, that is, in either mode or mode 2, each control signal and bus status signal can be read out by reading the content of port C. The status read out is as follows: Group A Group B Status Read on the Data Bus D 7 D 6 D 5 D 4 D 3 D 2 D D Mode Mode I/O I/O IBF A INTE A INTR A I/O I/O I/O 2 Mode Mode OBF A INTE A I/O I/O INTR A I/O I/O I/O 3 Mode Mode I/O I/O I/O I/O I/O INTE B IBF B INTR B 4 Mode Mode I/O I/O I/O I/O I/O INTE B OBF B INTR B 5 Mode Mode I/O I/O IBF A INTE A INTR A INTE B IBF B INTR B 6 Mode Mode I/O I/O IBF A INTE A INTR A INTE B OBF B INTR B 7 Mode Mode OBF A INTE A I/O I/O INTR A INTE B IBF B INTR B Mode Mode OBF A INTE A I/O I/O INTR A INTE B OBF B INTR B 9 Mode 2 Mode OBF A INTE IBF A INTE 2 INTR A I/O I/O I/O Mode 2 Mode OBF A INTE IBF A INTE 2 INTR A INTE B IBF B INTR B Mode 2 Mode OBF A INTE IBF A INTE 2 INTR A INTE B OBF B INTR B 6. Reset of MSM2C55A-2 Be sure to keep the RESET signal at power ON in the high level at least for 5 ms. Subsequently, it becomes the input mode at a high level pulse above 5 ns. Note: Comparison of MSM2C55A-5 and MSM2C55A-2 MSM2C55A-5 After a write command is executed to the command register, the internal latch is cleared in PORTA PORTC. For instance, H is output at the beginning of a write command when the output port is assigned. However, if PORTB is not cleared at this time, PORTB is unstable. In other words, PORTB only outputs ineffective data (unstable value according to the device) during the period from after a write command is executed till the first data is written to PORTB. MSM2C55A-2 After a write command is executed to the command register, the internal latch is cleared in All Ports (PORTA, PORTB, PORTC). H is output at the beginning of a write command when the output port is assigned. 2/26

NOTICE ON REPLACING LOW-SPEED DEVICES WITH HIGH-SPEED DEVICES The conventional low speed devices are replaced by high-speed devices as shown below. When you want to replace your low speed devices with high-speed devices, read the replacement notice given on the next pages. High-speed device (New) Low-speed device (Old) Remarks MC5AH MC5A/MC5A-2 bit MPU MC6A- MC6A/MC6A-2 6bit MPU MCA- MCA/MCA-2 bit MPU M2C4A-2 M2C4A/M2C4A-5 Clock generator MC55-5 MC55 RAM.I/O, timer M2C37B-5 M2C37A/M2C37A-5 DMA controller M2C5A-2 M2C5A USART M2C53-2 M2C53-5 Timer M2C55A-2 M2C55A-5 PPI 2/26

Differences between MSM2C55A-5 and MSM2C55A-2 ) Manufacturing Process These devices use a 3 m Si-Gate CMOS process technology. The MSM2C55A-2 is about 7% smaller in chip size than the MSM2C55A-5 as the MSM2C55A- 2 changed its output characteristics. 2) Function Item MSM2C55A-5 MSM2C55A-2 Internal latch during writing into the command register Only ports A and C are cleared. Port B is not cleared. All ports are cleared. The above function has been improved to remove bugs and other logics are not different between the two devices. 3) Electrical Characteristics 3-) DC Characteristics ''L'' Voltage Parameter Symbol MSM2C55A-5 MSM2C55A-2 VOL.45 V (IOL = +2.5 ma).4 V (IOL = +2.5 ma) ''H'' Voltage VOH 2.4 V (IOH = -4 ma) 3.7 V (IOH = -2.5 ma) Average Operating Current ICC 5 ma maximum (I/O Cycle = ms) ma maximum (I/O Cycle = 375 ns) As shown above, the DC characteristics of the MSM2C55A-2 satisfies the DC characteristics of the MSM2C55A-5. 3-2) AC Characteristics Parameter Symbol MSM2C55A-5 MSM2C55A-2 Address Hold Time for RD Rising tra 2 ns minimum ns minimum RD Pulse Width trr 3 ns minimum ns minimum Difined Data Delay Time From RD Falling trd 2 ns maximum 2 ns maximum Data Floating Delay Time From RD Rising trf ns maximum 75 ns maximum RD/WR Recovery Time trv 5 ns minimum 2 ns minimum 22/26

Parameter Symbol MSM2C55A-5 MSM2C55A-2 Address Hold Time for WR Rising twa 3 ns minimum 2 ns minimum WR Pulse Width tww 3 ns minimum 5 ns minimum Data Setup Time for WR Rising tdw ns minimum 5 ns minimum Data Hold Time for WR Rising twd 4 ns minimum 3 ns minimum Defined Data Time From WR Rising twb 35 ns maximum 2 ns maximum Port Data Hold Time for RD Rising thr 2 ns minimum ns minimum ACK Pulse Width tak 3 ns minimum ns minimum STB Pulse Width tst 3 ns minimum ns minimum Port Data Hold Time for STB Falling tph ns minimum 5 ns minimum ACK Falling to Defined Data tad 3 ns maximum 5 ns maximum WR Falling to OBF Falling Delay Time twob 65 ns maximum 5 ns maximum ACK Falling to OBF Rising Delay Time taob 35 ns maximum 5 ns maximum STB Falling to IBF Rising Delay Time tsib 3 ns maximum 5 ns maximum RD Rising to IBF Falling Delay Time trib 3 ns maximum 5 ns maximum RD Falling to INTR Falling Delay Time trit 4 ns maximum 2 ns maximum STB Rising to INTR Rising Delay Time tsit 3 ns maximum 5 ns maximum ACK Rising to INTR Rising Delay Time tait 35 ns maximum 5 ns maximum WR Falling to INTR Falling Delay Time twit 5 ns minimum 25 ns maximum As shown above, the MSM2C55A-2 satisfies the characteristics of the MSM2C55A-5. 23/26

PACKAGE DIMENSIONS (Unit : mm) DIP4-P-6-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6. TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 24/26

QFJ44-P-S65-.27 (Unit : mm) Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin Cu alloy Solder plating 5 mm or more 2. TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 25/26

QFP44-P-9-.-2K (Unit : mm) Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more.4 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 26/26