An Industrial Case Study for X-Canceling MISR

An Industrial Case Study for X-Canceling MISR Joon-Sung Yang, Nur A. Touba Coputer Engineering Research Center University of Texas, Austin, TX 7872 {jsyang,touba}@ece.utexas.edu Shih-Yu Yang, T.M. Mak Intel Corporation Portland, OR 9724 {shih-yu.yang,t..ak}@intel.co Abstract An X-tolerant ultiple-input signature register (MISR) copaction ethodology that copacts output streas containing unknown (X) values was described in [Touba 7]. Unlike conventional approaches, it does not use X- asking logic at the input of the MISR. Instead it uses sybolic siulation to express each bit of the MISR signature as a linear equation in ters of the X s. Linearly dependent cobinations of the signature bits are identified with Gaussian eliination and XORed together to cancel out all X values and yield deterinistic values. This new X-canceling approach was applied to soe industrial designs under the constraints iposed by an industrial test environent. Practical issues for ipleenting X-canceling are discussed, and a new architecture for ipleenting X-canceling based on using a shadow register with ultiple selective XORs is presented. Experiental results are shown for industrial designs coparing the perforance of X-canceling with X-copact.. Introduction can copact an output strea that contains X s without the need for X-asking. X-tolerant copactors have been developed based on linear cobinational copactors [Mitra 4a], [Patel 3], [Shara 5], convolutional copactors [Rajski 5], and circular registers [Rajski 6b]. While ultiple-input signature registers (MISRs) are the ost efficient for copacting output streas without X s, they present difficulties when X s are present because the X s quickly spread and corrupt the signature bits [Mitra 4b]. In [Touba 7], the concept of canceling out X s fro MISR signatures was proposed. An X-canceling MISR ethodology was described which can achieve arbitrarily high error coverage very efficiently where error coverage is the percentage of scan cells that are observed in the presence of X s. Sybolic siulation is used to express each bit of the MISR signature as a linear equation in ters of the X s. Linearly dependent cobinations of MISR signature bits are identified with Gaussian eliination and are XORed together to cancel out all X values thereby yielding deterinistic values that are invariant of what the final values of the X s end up being during the test. In this paper, a case study using an X-canceling MISR for two industrial designs is presented. The contributions of this paper include the following: Unknown X values cause issues in copacting output streas for test copression and BIST. Uninitialized eory eleents, bus contention, floating tri-states, and other sources introduce unknown values. X values - A discussion of the practical issues in ipleenting an corrupt the final signature aking it unknown. A nuber X-canceling ethod for industrial designs. of schees have been developed to deal with the proble - A new architecture for ipleenting an X-canceling of X s in the output response. MISR using a shadow register with ultiple selective One way of handling X s is to odify the circuitunder-test XORs. (CUT) so that it does not generate X values. - Experiental results based on industrial test cases to This approach is called X-bounding and requires adding copare the perforance of X-canceling with X- design-for-testability (DFT) logic to prevent X value copact (X tolerance), and a coparison of the actual propagation to scan cells [Wang 6]. Another approach, results obtained with the theoretical equations given in which does not require odifying the CUT, is X-asking [Touba 7]. which asks out X s at the input to the copactor. Mask control data is used to specify which scan chain outputs This paper is organized as follows: Sec. 2 gives a should be asked during which clock cycles. Many description of a concept of X-canceling and explains the schees for X-asking hardware design and ask control sybolic siulation process to identify X-canceled data copression have been developed [Barnhart ], cobinations. Sec. 3 discusses soe of the issues that [Wohl, 3, 4], [Poeranz 2], [Chickerane 4], arose in the case study. In Sec. 4, the proposed X- [Volkerink 5], [Chao 5], [Tang 6], [Rajski 6a]. A canceling MISR architectures are described and analyzed. third approach is to design an X-tolerant copactor which Sec. 5 presents the industrial design details. The Paper 7.2 INTERNATIONAL TEST CONFERENCE 978--4244-4867-8/9/$25. 29 IEEE

evaluation and the coparison with other techniques are shown in Sec. 6. Sec. 7 is a conclusion. 2. Overview of X-Canceling MISR This section gives a brief overview of the operation of an X-canceling MISR. A ore detailed explanation can be found in [Touba 7]. Assue the output response has been captured in the scan chains after applying a test vector. The value in each scan cell is represented with a sybol. An exaple is shown in Fig.. Once the output response has been shifted in to the MISR, the final MISR signature can be expressed in ters of the sybols through sybolic siulation. Each MISR bit is represented by a linear equation of the scan cell sybols. Fig. illustrates this sybolic representation. The final value of the top bit of the MISR is X O 3 O 8 O 3, where X i denotes an X value and O i indicates a non-x value. O 3 O 4 O 5 X 3 O 8 O 9 O 6 O O 7 O X 4 O 2 X O 2 O 3 X 2 O 5 O 6 M = X O 3 O 8 O 3 M2 = X O2 X2 X3 O9 O4 M 3 = O 2 O 5 X 3 O O 5 M 4 = X O 6 O O 6 M 5 = X O 2 X 3 O 2 O 7 M 6 = O 2 X 3 X 4 Figure. Exaple of Sybolic Siulation of MISR The focus here is on the unknown values, so each MISR bit equation can be reduced to a linear cobination of the X values by assigning to each non-x values without loss of generality. These linear cobinations can be expressed in the for of a atrix as shown in Fig. 2. Each entry in the atrix has a if the MISR bit corresponding to the row depends of the X corresponding to the colun. M = X M 2 = X X 2 X 3 M 3 = X 3 M 4 = X M 5 = X X 3 M 6 = X 3 X 4 Figure 2. Linear Equations for MISR in Fig. If the nuber of coluns is less than the nuber of rows, i.e., the nuber of X s is less than the MISR size, then soe row cobinations will be linearly dependent. Gauss-Jordan eliination [Cullen 97] can be perfored on the atrix in Fig. 2 to identify the linearly dependent cobinations of rows as illustrated in Fig. 3. The last two rows in Fig. 3 have all s and this indicates cobinations of MISR bits in which all the X s cancel out. The first all- row corresponds to M M 3 M 5. This iplies that XORing MISR bits M, M 3, and M 5 generates an Xcanceled signature bit which depends only on scan cells that captured non-x values as shown below: M M 3 M 5 = O 3 O 5 O 8 O O 2 O 3 O 5 O 7 Gaussian Eliination M M M 2 M 3 M 3 M 3 M 6 M M 3 M 5 M M 4 Paper 7.2 INTERNATIONAL TEST CONFERENCE 2 M M 2 M 3 M 4 M 5 M 6 Figure 3. Gauss-Jordan Eliination of MISR Equations The values of these X-canceled MISR bit cobinations are deterinistic and can be predicted through siulation. Therefore, during test, they can be copared with their fault-free values in order to detect errors. The MISR is operated across any clock cycles and ay span ultiple test vectors until the MISR fills up with X s. The MISR signature is then processed by selectively XORing linearly dependent cobinations of MISR bits in ters of the X s to generate X-free output response to send to the tester. The error coverage can be ade arbitrarily high by generating and checking a sufficient nuber of X-canceled output responses. The probability of not detecting an error drops by a factor of 2 for each X-canceled cobination that is checked. Note that the error coverage does not depend on the actual distribution of the X s in the output response, i.e., it doesn t atter how any X s there are in any particular scan slice. 3. Issues for Case Study This case study involved investigating the application of an X-canceling MISR to two industrial designs. When using X-copact [Mitra 4a] for these two designs, the fault coverage dropped significantly fro the case where the output response was not copressed. While X- copact is guaranteed to be able to tolerate one X per scan slice, the distribution of X s in these designs was such that any scan slices had too any X s to be efficiently copacted with X-copact. One way to

iprove the fault coverage would be to partition the outputs to ultiple saller X-copact networks, however, that would result in less copaction and hence increase the nuber of tester channels needed for output response as well as the aount of test data. The idea of this study was to see whether an X-canceling MISR could provide better results since its error coverage does not depend on the distribution of X s in each scan slice. The X-canceling MISR architecture described in [Touba 7] requires only a single tester channel for the output response thus freeing up the reaining tester channels for providing input stiulus. Details of this architecture are given in Sec. 4.. This architecture is very good for ulti-site testing and other applications where it is desirable to have ore tester channels for input stiulus and fewer channels for output response. However, in the application considered in this case study, there were soe issues for using this architecture:. It was preferred to have ore output response channels to aid in debug/diagnosis. 2. The ipleentation in Sec. 4. requires a scan architecture that is able to pause the scan load/unload operation during the processing of the MISR signature. This requires the ability to retain the values in the scan cells which requires soe for of clock gating. 3. Since the cycle count of each load/unload procedure is different, it ight be difficult to validate/debug patterns. To address these issues, a new architecture for efficiently ipleenting an X-canceling MISR was developed which is based on having ultiple selective XORs operating in parallel at the output. Details of this architecture are given in Sec. 4.2. It separates the control of the scan load/unload operation fro the MISR signature processing operation which resolves the issues listed above. In this case study, experients were perfored for both architectures to see how the results copared. 4. X-Canceling MISR Architectures The two X-canceling MISR architectures that were investigated in this case study are described in this section. 4. X-Canceling with Tie Multiplexing Fig. 4 shows the architecture for X-canceling with tie ultiplexing. The key idea is that two phases are alternated over tie: a test vector application phase and a signature processing phase. During the test vector application phase, tester channels are used to load the scan vectors through a decopressor. After the capture cycle, the output response is shifted into an -bit MISR through a phase-shifter as the next test vector is loaded. This proceeds across ultiple clock cycles and even ultiple scan vectors until the MISR fills up with X s. At that point, the scan shifting is stopped, and the signature processing phase begins. Linearly dependent cobinations of MISR bits are coputed via sybolic siulation as described in Sec. 2. The X-canceled cobinations are generated using a selective XOR network. In the signature processing phase, the tester channels are used to drive the control inputs to the selective XOR. The tester channels are used to generate the X-canceled cobinations by selecting which of the -bits in the MISR should be XORed together. Once the MISR signature has been processed (i.e., a sufficient nuber of X-canceled cobinations have been generated), then the MISR is reset and the test vector application phase resues. Note that the tester channels are fully utilized at all ties to drive the scan vector decopressor during the test application phase and to drive the selective XOR during the signature processing phase. Tester Channels Paper 7.2 INTERNATIONAL TEST CONFERENCE 3 Decopressor n s MISR control signal Phase Shifter -bit M I S R & & & XOR Selective XOR Figure 4. X-Canceling with Tie Multiplexing Table. Error Coverage versus Nuber of X-Canceled Cobinations (q) X-Canceled Cobinations (q) Error Coverage 5% 2 75% 3 87.5% 4 93.75% 5 96.88% 6 98.44% 7 99.2% 8 99.6% 9 99.8% 99.9% The error coverage that is provided depends on the nuber of X-canceled cobinations that are checked. Since the MISR with a priitive polynoial has a pseudo-rando property, each X-canceled cobination will depend on roughly half of the scan cells capturing X-Free

non-x values. Therefore, if q X-canceled cobinations are checked, the error coverage will be theoretically equal to -2 -q. If an -bit MISR is used, it can store up to -q X s and obtain a -2 -q error coverage by checking q linearly dependent cobinations of MISR signature bits obtained via Gauss-Jordan eliination. For exaple, if 7 X-canceled cobinations are checked, the error coverage is equal to -2-7 = 99.2%. Table shows the theoretical error coverage with q X-canceled cobinations. Additional test tie is required to stop the test vector application phase and perfor the signature processing phase. The nuber signature processing phases that are required depends on the X density (percentage of output response bits that are X s), MISR size, and target error coverage. The nuber of signature processing phases can be predicted. Assue that the X density is x%, there are n scan chains, and q X-canceled cobinations are checked to get -2 -q target error coverage. Based on the given inforation, the theoretical test tie can be calculated. In one scan slice, assuing a Gaussian X distribution, there would be n*x X s. The MISR can tolerate up to -q X s to achieve the target test coverage. It takes (-q)/(n*x) cycles to fill up the MISR with -q X s. Hence, the signature needs to be processed at every (-q)/(n*x) cycles. In the signature processing phase, q cycles are needed to provide the control data for generating the q X- canceled cobinations. Therefore, if the total nuber of cycles needed to apply the test patterns without stopping scan shifting is c, then the nuber of additional cycles added for canceling out the X s is [c / (-q)/(n*x)]*q. Hence, the total test tie and noralized test tie with respect to the test tie with no copaction is equal to: Total Test Tie = c [(c*n*x*q) / (-q)] Cycles Noralized Total Test Tie = [(n*x*q)/(-q)] While the test tie goes up, note that only one tester channel is needed for the output response, so all the other tester channels could be used for providing test stiulus thereby peritting the use of ore scan chains and thereby lowering c. This actually results in a lower overall test tie. The other benefit of this schee is that the sae tester channels are used for both test vector decopression and MISR signature processing via tie ultiplexing. Hence, no additional control tester channels are needed other than one channel to stop and resue MISR operation. For the output response, a single tester channel can be used for transferring the X-canceled bits. The requireents can thus be suarized as follows: Input Tester Channels: Decopressor Channels Output Tester Channels: 4.2 X-Canceling with Shadow Register If it is not desirable to halt scan shifting to process the interediate MISR signatures, an alternate approach would be to use a shadow register. Fig. 5 shows the X- canceling with shadow register architecture. The shadow register is placed after the ain MISR and retains the interediate signature for further processing. This allows the MISR to continue to copress the scan data without interruptions. Additional control inputs fro the tester are used to provide the control signals to one or ultiple selective XOR networks. Tester Channels Paper 7.2 INTERNATIONAL TEST CONFERENCE 4 Decopressor n s MISR control signal *k X-canceling control signals Phase Shifter -bit M I S R -bit S H A D O W Selective XOR # Selective XOR #k Figure 5. X-Canceling with Shadow Register When the MISR fills up with X s, the contents of the MISR are transferred to a shadow register, and the MISR is iediately reset so that scan shifting can continue uninterrupted. The saved interediate signature in the shadow register is then processed to extract the X- canceled cobinations as the next signature is being generated in a ain MISR. Control signals need to be transferred while both the MISR and shadow register are operating. Therefore, extra tester channels are used to provide the control data that selects the X-canceled cobinations. In this schee, because the shadow register gets rid of the additional test cycles for X-canceling, there is no additional test tie penalty. As shown earlier, the error coverage depends on how any X-canceled cobinations (q) are checked. X-canceling with tie ultiplexing requires q cycles to reach -2 -q error coverage during each signature processing phase. However, X-canceling with a shadow register only allows extracting X-canceled cobinations before the next interediate signature is transferred fro the MISR to the shadow register. Calculating the theoretical error coverage is different in this case fro what was done in Sec. 4.. Fig. 5 shows k selective XOR gates after the shadow register. This allows k X-canceled cobinations to be checked each clock cycle. However, the nuber of clock cycles over which the signature can be processed is liited by the tie it takes for the MISR to fill up with X s again. Let the signature transfer period be defined as the nuber of clock cycles fro when one interediate signature is k X-Free

transferred fro the MISR to the shadow register until the next one is transferred. The nuber of X-canceled cobinations that are checked is deterined by the nuber of selective XOR gates that are used ties the nuber of cycles over which the signature is processed which is the signature transfer period. For k selective XOR gates, the error coverage is -2 -k after the first cycle. In the second cycle, the reaining errors that have not been covered yet are (-(-2 -k )), so the error coverage for the is again -2 -k, hence the resulting error coverage after the second cycle is (-(-2 -k ))*(-2 -k ) plus the error coverage after the first cycle. This is illustrated below: Cov = 2 -k (Coverage at st cycle) Cov 2 = Cov ( - Cov ) * (-2 -k ) (Coverage at 2 nd cycle) : : Cov s = Cov s- ( - Cov s- ) * (-2 -k ) (Coverage at s th cycle) Table 2 shows the error coverage for different values of k and the signature transfer period, s. Table 2. Error Coverage for X-Canceling with Shadow Register Schee k XOR Gates (k Check/Cycle) 2 3 4 s cycle (signature transfer Error Coverage cycle) 5.% 2 75.% 3 87.5% 4 93.75% 75.% 2 93.75% 3 98.43% 4 99.6% 87.5% 2 98.43% 3 99.8% 4 99.97% 93.75% 2 99.6% 3 99.97% 4 99.99% Unlike X-canceling with tie ultiplexing, X- canceling with a shadow register dedicates tester channels to provide control signals to the selective XORs. Hence, if k XOR gates (k Checks/Cycle) are used, *k input tester channels are needed for driving the where is the size of the MISR. And one input tester channel needs to be assigned to control when the MISR signature is transferred to the shadow register and reset. For the output response, k tester channels are required. The requireents can thus be suarized as follows: Input Tester Channels: Decopressor Channels (MISR_size * Checks/Cycle) Output Tester Channels: Checks/Cycle 5. Details of Industrial Designs Two industrial designs fro Intel were analyzed in detail for the experients. 5. The First Test Case The first test case (Ckt) has 33 input and output tester channels respectively. Ckt has a x copression ratio. 33 inputs are expanded into 33 scan chains using Illinois scan [Hazaoglu 99]. Ckt has three subblocks (A, B, and C). 62, 38, and 3 output tester channels are assigned to Ckt-A, Ckt-B, and Ckt-C respectively and 2 output channels are used for bypass ode. Ckt-A has 5 scan chains, Ckt-B has 23 chains and Ckt-C has 75 scan chains as shown in Fig. 6. The longest scan chain length is 48. 3 autoatic test pattern generation (ATPG) patterns were analyzed to deterine the X density of each block in Ckt. Ckt-A has the least X density aong three units. The X density is.7% and the average nuber of X s per each scan slice is.73 (5 *.7%), i.e,.73 X s arrive at the copactor inputs every cycle. Ckt-B has 3.35% X density and the average nuber of X s per scan slice is 6.8. 3.28% X density is found in Ckt-C and this generates 2.46 X s per scan slice. 33 Decopressor 33 s Ckt-A Ckt-A 5 Ckt-B Ckt-B 23 Ckt-C Ckt-C 75 Copactor Figure 6. First Test Case 5.2 The Second Test case 33 The second test case (Ckt2) has relatively fewer test channels than the first test case in Sec. 5.. Ckt2 has 6 input and output tester channels. There are three partitions (A, B and C) in the design which are connected in a daisy chain anner. Ckt2-A, Ckt2-B, and Ckt2-C all Paper 7.2 INTERNATIONAL TEST CONFERENCE 5

have 64 scan chains. Ckt2 has a 4x copression ratio. 6 inputs are expanded to fill 64 scan chains. Ckt2-A has a 2.% X density and the average X s per scan slice is.28. Ckt2-B has.5% X density which gives.67 average X s in a scan slice. 2.74% X density is found in Ckt2-C and.76 X s are in a scan slice, on average. 6 Decopressor Ckt2-A Ckt2-A 64 64 s Ckt2-B Ckt2-B 64 Ckt2-C Ckt2-C 64 64 s 64 s Figure 7. Second Test Case 6. Experiental Results Experients were perfored for these two test cases described in Sec. 5. The X-canceling with tie ultiplexing and X-canceling with shadow register schees are analyzed and copared with X-copact [Mitra 4a] which is widely used. 6. X-Canceling with Tie Multiplexing Table 3 shows the results for X-canceling with tie ultiplexing. A 32-bit MISR is used for each of the three blocks in Ckt to copact the responses fro the scan chains and to generate X-canceled cobinations. The outputs of the scan chains are fed into a phase shifter before going to the MISR to reduce shift correlation [Touba 7]. The first colun shows the circuits, and the second colun shows the types of copactors. As shown in Sec. 4., the error coverage depends on how any X- canceled cobinations (q) are checked. Results were generated for values of q ranging fro 4 to 8. The third colun shows the nuber of input and output tester channels used. The forula for the required nuber of input and output channels was given in Sec. 4.. The nuber of two input XOR gates is shown in the fourth colun. X-canceling with tie ultiplexing requires (fanout * scan_chain ) XOR gates when an -bit MISR is used. For Ckt-A, a 32-bit MISR where each scan chain output fans out to 7 XOR gates in a phase shifter is used, so the nuber of two input XOR gates is 7,38 (7*5 3) for Ckt-A. The fifth colun shows the test tie for each schee. The results are noralized with respect to the results for X-copact. The additional test tie for control signal transfer (as described in Sec. 4.) is also noralized and shown in the fifth colun. The last colun shows the error coverage. Unlike other schees, the error coverage for an X-canceling MISR can Copactor 6 be estiated based on the nuber of X-canceled cobinations that are observed. The experiental results show what the theory would estiate the coverage and test tie to be for purposes of coparison with the actual values. For Ckt2, a 64-bit MISR and a phase shifter with 5 fanouts per scan chain were used. Larger MISRs can hold ore X s before needing to be processed, however, they also require ore data to process each signature, so the net effect is that test tie and storage is relatively constant regardless of the MISR size. The ain issue with the MISR size is the nuber of X s in a single scan slice that it can handle. The MISR size should not be saller than the axiu nuber of X s in any scan slice. As can be seen fro Table 3, the proposed ethod achieves an error coverage and test tie very close to that predicted by the theoretical forula. The reason for the slight deviation is that the forulas assue the MISR can stop when it takes exactly the full nuber of X s values that it can hold. However, in practice, the X s are entering the MISR in clusters scan slice by scan slice, so if the next scan slice puts the nuber of X s over the liit, the MISR signature ust first be processed before it can copact that scan slice. This results in soe extra test tie in coparison to that predicted by the theoretical forulas. In coparing the results for X-canceling with X- copact, any fewer output tester channels are required while arbitrarily higher error coverage can be achieved to whatever the desired level is. For Ckt, less overhead is required for X-canceling. For Ckt2, the overhead is very low for both ethods. X-canceling with tie ultiplexing does have higher test tie in this scenario because the output tester channels that have been reduced have not be used for providing test stiulus. Effectively, the tester bandwidth allocated for X-canceling here is less than that for X-copact. Looking at the individual partitions, it can be seen that Ckt-A has very low X-density, and both X-copact and X-canceling perfor very well. X-canceling requires any fewer output tester channels and less overhead with a bit ore test tie. For Ckt-B and Ckt-C, the X- density is over 3% in both cases, and the error coverage provided by X-copact is low. This occurs because soe scan slices have any X s. Note that even though Ckt-B and Ckt-C have siilar X-densities, the X-copact coverage for Ckt-B is uch lower. This is because the distribution of X s in Ckt-B is such that coverage is lost for a larger percentage of scan slices than in Ckt-C. The X s in Ckt-C are ore clustered in fewer scan slices, so the percentage of scan slices where coverage is lost is less. X-canceling can achieve high error coverage for any distribution of X s, so it perfors very well in ters of error coverage. The cost of achieving the higher error coverage is additional test tie, but again fewer output Paper 7.2 INTERNATIONAL TEST CONFERENCE 6

Table 3. Results for X-Canceling MISR with Tie ultiplexing Copared with X-Copact Circuit Copactor Estiated Actual Estiated Actual Tester Channels Nu. Test Tie Test Tie Error Error XORs Input Output (Noralized) (Noralized) Coverage Coverage X-Copact 33 62 3,865 N/A N/A 99.4% Ckt-A q = 4 34 7,38..2 93.7% 93.7% q = 5 34 7,38.3.6 96.8% 96.8% X-density X-Canceling q = 6 34 7,38.6.9 98.4% 98.4% =.7% q = 7 34 7,38.2.22 99.2% 99.2% q = 8 34 7,38.24.25 99.6% 99.6% X-Copact 33 38 4,35 N/A N/A 36.9% Ckt-B q = 4 34,452.97 2.42 93.7% 93.7% q = 5 34,452 2.25 2.78 96.8% 96.8% X-density X-Canceling q = 6 34,452 2.56 3.3 98.4% 98.4% = 3.35% q = 7 34,452 2.9 3.49 99.2% 99.2% q = 8 34,452 3.26 3.85 99.6% 99.6% X-Copact 33 3,3 N/A N/A 86.8% Ckt-C q = 4 34 556.35.45 93.7% 93.5% q = 5 34 556.45.57 96.8% 96.6% X-density X-Canceling q = 6 34 556.56.68 98.4% 98.2% = 3.28% q = 7 34 556.68.8 99.2% 99.% q = 8 34 556.82.9 99.6% 99.3% X-Copact 6 6 92 N/A N/A 95.4% Ckt2-A q = 4 7 447.34.35 93.7% 93.6% q = 5 7 447.43.44 96.8% 96.7% X-density X-Canceling q = 6 7 447.52.54 98.4% 98.3% = 2.% q = 7 7 447.62.64 99.2% 99.% q = 8 7 447.73.74 99.6% 99.5% X-Copact 6 6 92 N/A N/A 97.9% Ckt2-B q = 4 7 447.7.8 93.7% 93.6% q = 5 7 447.22.23 96.8% 96.7% X-density X-Canceling q = 6 7 447.27.28 98.4% 98.3% =.67% q = 7 7 447.32.33 99.2% 99.% q = 8 7 447.38.39 99.6% 99.5% X-Copact 6 6 92 N/A N/A 92.7% Ckt2-C q = 4 7 447.46.48 93.7% 93.5% q = 5 7 447.59.6 96.8% 96.6% X-density X-Canceling q = 6 7 447.72.74 98.4% 98.2% = 2.74% q = 7 7 447.86.87 99.2% 99.% q = 8 7 447 2. 2. 99.6% 99.4% tester channels are required. For Ckt2, X-copact is using 32 tester channels, while X-canceling is using only 8 tester channels. If the 4 tester channels that are reduced with X-canceling were to be eployed in providing test stiulus, then X-canceling would have lower test tie in all cases while providing greater error coverage. 6.2 X-Canceling with Shadow Register Results for X-canceling with shadow registers are shown in Table 4. The control signals for generating the X- canceled cobinations are provided by dedicated tester channels rather than through tie ultiplexing, so the test tie is exactly the sae for both X-copact and X- canceling. The first colun shows the circuits and the second colun shows the types of copactors with different nubers of checks/cycle. The nuber of required input and output tester channels and the nuber of two input XOR gates are shown in the third and fourth colun respectively. The last colun shows the error coverage. As before, the error coverage for X-canceling can be ade arbitrarily high. In this case, iproving the error coverage coes at the cost of requiring ore checks/cycle which requires ore input tester channels, however, the test tie reains constant. Paper 7.2 INTERNATIONAL TEST CONFERENCE 7

Table 4. Results for X-Canceling MISR with Shadow Register Copared with X-Copact (for the Sae Test Tie) Circuit Copactor Checks/Cycle Estiated Actual Tester Channels Nu. Error Error XORs Input Output Coverage Coverage X-Copact N/A 33 62 3,865 N/A 99.4% 46 5,26 93.7% 93.7% Ckt-A X-Canceling 2 58 2 5,272 99.6% 98.2% 2-Bit MISR 3 7 3 5,283 99.9% 99.% 4 82 4 5,294 99.9% 99.4% X-Copact N/A 33 38 4,35 N/A 36.9% 48,845 75.% 74.4% Ckt-B X-Canceling 2 62 2,863 93.7% 9.2% 9-Bit MISR 3 76 3,88 98.4% 97.9% 4 9 4,899 99.6% 98.9% X-Copact N/A 33 3,3 N/A 86.8% 43,28 87.5% 87.3% Ckt-C X-Canceling 2 52 2,4 98.4% 95.8% 4-Bit MISR 3 6 3,54 99.8% 97.6% 4 7 4,67 99.9% 98.8% X-Copact N/A 6 6 92 N/A 95.4% 33 463 93.75% 93.6% Ckt2-A X-Canceling 2 49 2 478 99.6% 98.% 6-Bit MISR 3 65 3 493 99.97% 98.92% 4 8 4 58 99.99% 99.2% X-Copact N/A 6 6 92 N/A 97.9% 33 463 93.75% 93.67% Ckt2-B X-Canceling 2 49 2 478 99.6% 98.7% 6-Bit MISR 3 65 3 493 99.97% 98.96% 4 8 4 58 99.99% 99.24% X-Copact N/A 6 6 92 N/A 92.7% 33 463 93.75% 93.63% Ckt2-C X-Canceling 2 49 2 478 99.6% 98.2% 6-Bit MISR 3 65 3 493 99.97% 99.% 4 8 4 58 99.99% 99.39% 6.3 Fault Coverage Results Fault grading was perfored on Ckt to see the actual fault coverage that is achieved by the X-canceling ethods and X-Copact. For each block in Ckt, a 32-bit MISR with q = 8 configuration is used for X-canceling with tie ultiplexing. For X-canceling with shadow registers, a configuration was selected which has a siilar nuber of tester channels to X-Copact for a fair coparison. The following is used: 2-bit MISR with 4 checks/cycle for Ckt-A, 9-bit MISR with 2 checks/cycle for Ckt-B, and 4-bit MISR with 2 checks/cycle for Ckt-C. This configuration requires 268 tester channels and X-Copact needs 266 channels. The fault coverage for 3 ATPG patterns is shown in Fig. 8. Without any copression, slightly over 9% fault coverage is obtained. As shown in Table 3 and Table 4, the X-canceling MISR schees achieve high error coverage which translates to fault coverage which is very close to what is obtained without any copression. The fault coverage for X- Copact, however, is 2~3% lower. Paper 7.2 INTERNATIONAL TEST CONFERENCE 8

9. Test Coverage (%) 85. 8. 75. W/O Copression X-Canceling with Tie Multiplexing 7. X-Canceling with Shadow Register X-Copact 65. 64 576 88 6 22 2624 3 Nu. of Test Patterns Figure 8. Fault Grading Results for Ckt with Different Schees 7. Conclusions This industrial case study shows the benefits of X- canceling in ters of its scalability and ability to systeatically achieve high fault coverage regardless of the distribution of X s. Two different architectures were presented for X-canceling which can be used based on what the tester channel and test tie requireents are for a particular design. It was also shown the theoretical equations for estiating the error coverage for X- canceling atched closely with the actual error coverage achieved in the experients. References [Barnhart ] Barnhart, C., V. Brunkhorst, F. Distler, O. Farnsworth, B. Keller, and B. Koeneann, OPMISR: the Foundation for Copressed ATPG Vectors, Proc. of International Test Conference, pp. 748-757, 2. [Chao 5] Chao, M. C.-T., S. Wang, S.T. Chakradhar, and K.-T. Cheng, Response Shaper: A Novel Technique to Enhance Unknown Tolerance for Output Response Copaction, Proc. of International Conference on Coputer-Aided Design, pp. 8-87, 25. [Chickerane 4] Chickerane, V., B. Foutz, and B. Keller, Channel Masking Synthesis for Efficient On-Chip Test Copression, Proc. of International Test Conference, pp. 452-46, 24. [Cullen 97] Cullen, C.G., Linear Algebra with Applications, Addison-Wesley, ISBN -673-99386-8, 997. [Garg 8] Garg, R., R. Putan, and N.A. Touba, Increasing Output Copaction in Presence of Unknowns Using an X- Canceling MISR with Deterinistic Observation, Proc. of IEEE VLSI Test Syposiu, pp. 35-42, 28. [Hazaoglu 99] Hazaoglu, I., and J.H. Patel, Reducing Test Application Tie for Full Scan Ebedded Cores, Digest of Papers 29th Ann. Int l Syp. Fault Tolerant Coputing, IEEE Press, pp. 26-267, 999. [Mitra 4a] Mitra, S., and K.S. Ki, X-Copact: An Efficient Response Copaction Schee, IEEE Trans. on Coputer-Aided Design, Vol. 23, No. 3, pp. 42-432, Mar. 24. [Mitra 4b] Mitra, S., S.S. Luetta, and M. Mitzenacher, X- Tolerant Signature Analysis, Proc. of International Test Conference, pp. 432-44, 24. [Patel 3] Patel, J.H., S.S. Luetta, and S.M. Reddy, Application of Saluja-Karpovsky Copactors to Test Responses with Many Unknowns, Proc. of VLSI Test Syposiu, pp. 7-2, 23. [Poeranz 2] Poeranz, I., S. Kundu, and S.M. Reddy, On Output Response Copression in the Presence of Unknown Output Values, Proc. of Design Autoation Conference, pp. 255-258, 22. [Rajski 5] Rajiski, J., J. Tyszer, C. Wang and S.M. Reddy, Finite Meory Test Response Copactors for Ebedded Test Applications, IEEE Trans. on Coputer-Aided Design, Vol. 24, No. 4, pp. 622-634, Apr. 25. Paper 7.2 INTERNATIONAL TEST CONFERENCE 9

[Rajski 6a] Rajski, J., J. Tyszer, G. Mrugalski, W.-T. Cheng, N. Mukherjee, and M. Kassab, X-Press Copactor for x Reduction of Test Data, Proc. of International Test Conference, Paper 8., 26. [Rajski 6b] Rajski, W., and J. Rajski, Modular Copactor of Test Responses, Proc. of VLSI Test Syposiu, pp. 242-25, 26. [Patel 3] Patel, J.H., S.S. Luetta, and S.M. Reddy, Application of Saluja-Karpovsky Copactors to Test Responses with Many Unknowns, Proc. of VLSI Test Syposiu, pp. 7-2, 23. [Shara 5] Shara M. and W.-T. Cheng, X-Filter: Filtering Unknowns fro Copacted Test Responses, Proc. of International Test Conference, Paper 42., 25. [Tang 6] Tang, Y., H.-J. Wunderlich, P. Engelke, I. Polian, B. Becker, J. Scholöffel, F. Hapke, and M. Wittke, X- Masking During Logic BIST and Its Ipact on Defect Coverage, IEEE Trans. on VLSI, Vol. 4, No. 2, Feb. 26. [Volkerink 5] Volkerink, E.H., and S. Mitra, Response Copaction with Any Nuber of Unknowns Using a New LFSR Architecture, Proc. of Design Autoation Conference, pp. 7-22, 25. [Wang 6] L.T. Wang, C.-W. Wu, X. Wen, VLSI Test Principles and Architectures, Morgan Kaufann, 26. [Wohl ] Wohl, P., J.A. Waicukauski, and T.W. Willias, Design of Copactors for Signature-Analyzers in Built-In Self-Test, Proc. of International Test Conference, pp. 54-63, 2. [Wohl 3] Wohl, P., J.A. Waicukauski, S. Patel, and M.B. Ain, X-Tolerant Copression and Application of Scan-ATPG Patterns in a BIST Architecture, Proc. of International Test Conference, pp. 727-736, 23. [Wohl 4] Wohl, P., J.A. Waicukauski, and S. Patel, Scalable Selector Architecture for X-Tolerant Deterinistic BIST, Proc. of Design Autoation Conference, pp. 934-939, 24. [Touba 7] Touba, N.A., X-Canceling MISR An X-Tolerant Methodology for Copacting Output Responses with Unknowns Using a MISR, Proc. of International Test Conference, paper 6.2, 27 Paper 7.2 INTERNATIONAL TEST CONFERENCE