Software Engineering 2DA4 Slides 3: Optimized Implementation of Logic Functions Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital Logic with Verilog Design, 3rd Ed. c 1999-2018 R.J. Leduc, M. Lawford 1
Motivation: Cost What is the cost of a circuit? x 1 x 2 f 1 0 0 0 0 1 1 1 0 0 1 1 1 f 1 = x 1 x 2 +x 1 x 2 Real cost depends on technology: 7400 chips: takes part of one or more chips CPLD: takes 1 macrocell Custom chip: takes 20 transistors (CMOS) A simple cost metric (ignore cost of inverters): Cost = # gates + # inputs For f 1 : Cost = 3 + 6 = 9. Need a method for synthesizing circuits of minimal cost. So far have used algebra. c 1999-2018 R.J. Leduc, M. Lawford 2
Karnaugh Maps We need a systematic method of optimization. Karnaugh maps were used in past to do optimization by hand. Now CAD tools do this automatically using more sophisticated techniques. Def: A K-map is a type of truth table, organized so that it shows product-terms that can be combined to reduce cost. All minterms that are adjacent in the map can be combined. Two cells are adjacent if the valuation of the input variables for each differ by only 1 bit! Cells labelled xy = 00 and xy = 01 are adjacent but cells labelled xy = 10 and xy = 01 are not. Thus in 3 variable tables, the columns are labeled such that only one variable changes in adjacent columns. c 1999-2018 R.J. Leduc, M. Lawford 3
Two Variable K-Maps c 1999-2018 R.J. Leduc, M. Lawford 4
Three Variable K-Maps c 1999-2018 R.J. Leduc, M. Lawford 5
Four Variable K-Maps c 1999-2018 R.J. Leduc, M. Lawford 6
Five Variable K-Maps c 1999-2018 R.J. Leduc, M. Lawford 7
Rules for K-maps (Sum-of-Products) 1. Must cover all squares containing 1s 2. Form largest group of 1s but group must be power of 2 (e.g. 1, 2, 4, 8 groups). Groups contain adjacent cells of ones only (ie. rectangles and squares of 1s). 3. Write Product term for group. Only include variables with constant value in group. 4. It is OK to cover a 1 multiple times. Why largest grouping and as a few groups as possible? To keep cost (#gates + #inputs) down. c 1999-2018 R.J. Leduc, M. Lawford 8
What if non-unique soln? Literal: Variable in complemented or uncomplemented form. ie. x 1, x 1 Implicant: A product term that indicates an input valuation for when given function equals 1. Most basic implicants are minterms of the function. Prime Implicant: An implicant that can t be combined into another implicant with fewer variables. Cover: Collection of implicants that account for all valuations where f = 1. Canonical sum-of-products an example. Essential Prime Implicant: A prime implicant that contains a 1 square in k-map that is not covered by any other prime implicant. c 1999-2018 R.J. Leduc, M. Lawford 9
Optimization Method 1. Find set of essential prime implicants. 2. If cover all 1-squares of k-map, then stop. 3. Determine non-essential prime implicants until all 1-squares covered, and minimum cost solution found. May have several variations to select from. c 1999-2018 R.J. Leduc, M. Lawford 10
Optimization Example c 1999-2018 R.J. Leduc, M. Lawford 11
Product-of-Sum Optimization Rules for K-maps: 1. Must cover all squares containing 0s 2. Form largest group of 0s but group must be power of 2 (e.g. 1, 2, 4, 8 groups). Groups contain adjacent cells of zeros only (ie. rectangles and squares of 0s). 3. Write sum term for group. Only include variables with constant value in group, and complement input variables. 4. It is OK to cover a 0 multiple times. If asked to find lowest cost circuit, do k-map for both sum-of-product and product-of-sums and choose lowest cost. c 1999-2018 R.J. Leduc, M. Lawford 12
Don t Care Conditions In a circuit with n inputs, we sometimes know that certain input patterns will never occur. E.g. 1 Circuit with cross-coupled switches that are impossible to simultaneously close (i.e. set to 1) x 1 x 2 f 0 0 0 0 1 1 1 0 1 1 1 d Here d = don t care (it will never happen). We can arbitrarily make d a 0 or 1. If d = 0, f = x 1 x 2 +x 1 x 2 (cost=9) If d = 1, f = x 1 +x 2 (cost=3) c 1999-2018 R.J. Leduc, M. Lawford 13
Don t Care Conditions - II We choose the value of d (0 or 1) to minimize the circuit. For k-maps, include a d in a group if can create a larger group, ignore otherwise. You do not have to cover all d items. When circling 1s, including a d in a group sets the function output to 1 for that input combination (i.e. you are choosing d= 1 for that item). Not including the d in some group of 1s, sets the function to zero for that input combination. When circling 0s, including a d in a group sets the function output to 0 for that input combination, else 1. c 1999-2018 R.J. Leduc, M. Lawford 14
Don t Care Conditions - e.g. 2 For 7-Segment Display, assume we only want to display numbers 0-9. We need 4 inputs. (why?) Also assume that we can guarantee that only 10 input patterns will ever occur. Synthesize a function for segment f. a a f g b f g b e c e c d d decimal point c 1999-2018 R.J. Leduc, M. Lawford 15
Don t Care Conditions - e.g. 2 - II f e a g d b c f e a g d decimal point b c x 1 x 2 x 3 x 4 Display f 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 1 0 1 0 1 5 1 0 1 1 0 6 1 0 1 1 1 7 0 1 0 0 0 8 1 1 0 0 1 9 1 1 0 1 0 d 1 0 1 1 d 1 1 0 0 d 1 1 0 1 d 1 1 1 0 d 1 1 1 1 d c 1999-2018 R.J. Leduc, M. Lawford 16
Introduction to D Flip-Flops A flip-flop is a storage device. A positive edge triggered D Flip-Flop stores whatever value is at its D input on the rising edge of the clock (when the clock input transitions from low to high). The stored value is assigned to its Q output. A positive edge-triggered D flip-flop ONLY stores a new value on the rising edge of the clock, and ignores changes on its D input otherwise. A negative edge-triggered D Flip-Flop behaves the same except it only stores a value on the negative edge of the clock (when the clock transitions from high to low). c 1999-2018 R.J. Leduc, M. Lawford 17
Introduction to D Flip-Flops - II Figure shows, from top to bottom, a D latch (ignore for now), a positive edge-triggered D Flip-Flop, and a negative edge-triggered D Flip-Flop. c 1999-2018 R.J. Leduc, M. Lawford 18
D Flip-Flops with Reset Sometimes want to ensure the D flip-flop has a known value. A RESET (CLEAR) input added to the flip-flop allows us to force stored output to go to zero. Example below has an active high RESET. Reset is asynchronous as it doesn t wait for clock edge to set Q to zero; it takes effect immediately. c 1999-2018 R.J. Leduc, M. Lawford 19
Data Registers If we combine 4 D flip-flops with reset, we can create a 4 bit data register with reset. c 1999-2018 R.J. Leduc, M. Lawford 20