SignalTap Analysis in the Quartus II Software Version 2.0

SignalTap Analysis in the Quartus II Software Version 2.0 September 2002, ver. 2.1 Application Note 175 Introduction As design complexity for programmable logic devices (PLDs) increases, traditional methods of system verification need to be supplemented by efficient methods of board-level verification. The SignalTap Embedded Logic Analyzer, available in the Altera Quartus II software version 2.0, helps reduce verification times by allowing engineers to conduct real-time board-level tests of Altera devices. You can access internal nodes within a design that would otherwise be inaccessible using more traditional verification techniques. SignalTap analysis can eliminate the need to use external probes to access and capture signals. The Quartus II software interface allows signal selection, event trigger setup, memory configuration, and display of captured waveforms. This application note gives an overview of how to set up and run the SignalTap analyzer and explains how to use the various SignalTap logic analyzer options. The SignalTap II embedded logic Analyzer is available in the Quartus II software version 2.1 and higher. The SignalTap II embedded logic analyzer provides enhanced functionality including support for multiple instantiations and multiple trigger levels. Background SignalTap analysis helps verify device functionality by capturing and displaying internal and I/O signals at system clock speeds. SignalTap analysis requires the SignalTap logic analyzer megafunction included in the Quartus II software and a communication cable. The SignalTap embedded analyzer works within the Quartus II software for design development, debugging, and verification. SignalTap Embedded Logic Analyzer The SignalTap embedded logic analyzer captures signals from internal device nodes while the device is running, giving non-intrusive access to signals from device nodes and I/O pins. Altera Corporation 1 AN-175-2.1

Quartus II Software The Quartus II software allows you to select which signals to capture, when signal capture starts, and how many data samples to capture. You can also select whether the data is routed to the device s embedded system blocks (ESBs) for use by the SignalTap analyzer or the I/O pins for use by external logic analysis equipment. Internal nodes for capture are selected using the Quartus II Node Finder. Once the SignalTap analyzer is configured, it is compiled in the Quartus II software along with the rest of the design. Communication Cable You can use either a MasterBlaster TM or ByteBlasterMV TM communication cable to download configuration data to the device. These cables are also used to upload captured signal data from the device s ESBs to the Quartus II software, which displays data acquired by the SignalTap analyzer as waveforms. f SignalTap Analyzer Configuration See the MasterBlaster Serial/USB Communications Cable Data Sheet and the ByteBlasterMV Parallel Port Download Cable Data Sheet for more information. You can configure the SignalTap embedded analyzer in internal RAM or debug port configurations. The analyzer can use trigger input and trigger output signals. The SignalTap configuration best suited for a design is primarily based on the availability of device memory resources and I/O pins, and whether the SignalTap analyzer will be used in conjunction with external test equipment. Table 1 shows the LE resource usage. Table 1. SignalTap Logic Element (LE) Utilization Signals LEs Used 1 136 2 144 4 160 8 192 16 256 32 384 64 640 128 1,152 2 Altera Corporation

Internal RAM Configuration In the internal RAM configuration, acquired data is saved to the device s internal RAM and then streamed off-device via the IEEE Std. 1149.1 Joint Test Action Group (JTAG) port. This setup requires the most memory resources, but the fewest number of I/O pins. The Quartus II software automatically assigns internal memory for acquisition data storage, which is automatically stored in the ESBs of APEX TM II, APEX 20K, APEX 20KE, APEX 20KC, Mercury, or ARM -based Excalibur TM devices. Table 2 shows the SignalTap ESB resource usage. Table 2. SignalTap ESB Utilization Note (1) Signals Samples (Depth) (Width) 128 256 512 1,024 2,048 1 1 2 1 2 4 1 2 4 8 1 2 4 8 16 1 2 4 8 16 32 2 4 8 16 32 64 4 8 16 32 64 128 8 16 32 64 128 Note to Table 2: (1) This table provides only a sample of ESB resource utilization; you can specify up to 128 channels with a maximum of 128,000 samples for each signal. Debug Port Configuration When device RAM is limited, the software can route internal signals to unused I/O pins for capture by an external analyzer or oscilloscope. The debug port configuration conserves ESBs at the expense of I/O pins. It is useful for data-intensive applications in which the amount of saved data exceeds the available sample buffer depth provided by the device s RAM. In the debug port configuration, the Quartus II software automatically generates pins for signals selected for output via the debug port. To assign pins manually to a specific pin, use the Quartus II Floorplan Editor. Altera Corporation 3

Trigger Input & Trigger Output Configuration The SignalTap analyzer can use a trigger input in which it is triggered by an external source. The analyzer can also be operated in the trigger output configuration in which it supplies an external signal to trigger other devices. Performing Logic Analysis Using SignalTap The Quartus II software includes the SignalTap analyzer user interface, the trigger setup, sample depth selection, run controls, programming interface, data log, and filter controls. The SignalTap analyzer captures and stores data in a SignalTap File (.stp) and displays it in the SignalTap waveform window. See Figure 1. Figure 1. SignalTap Window in Quartus II Software Version 2.0 1 The SignalTap analyzer can also open Embedded Logic Analyzer (.ela) files created by previous versions of the SignalTap analyzer. 4 Altera Corporation

Setting Up the SignalTap Analyzer To set up SignalTap analysis in the Quartus II software, follow these steps, which are described in more detail below: 1. Create or open an.stp file. 2. Assign signals to the SignalTap file. 3. Select a SignalTap clock signal. 4. Set the sample buffer depth. 5. Set the trigger position. 6. Set the trigger pattern. 7. Configure the communication cable. 8. Compile the Quartus II project with the.stp file selected. 9. Download the programming file to the device. 10. Run the SignalTap analyzer. f For more detailed information on setting up the SignalTap analyzer, go to Overview: Using the SignalTap Logic Analyzer in the Quartus II Help. Creating or Opening a SignalTap File To set up and modify the SignalTap analyzer, first create, name, and save an.stp file or open an existing.stp file. Figure 2 shows the dialog box for creating a new SignalTap file. Altera Corporation 5

Figure 2. Creating a SignalTap File Saving, Copying & Renaming a SignalTap File Once an.stp file is created or edited, changes can be saved to the same file or a new file. Assigning a Signal to the SignalTap File The SignalTap analyzer can capture signals from any internal device node, including I/O pins. Before capturing signals, you must assign the internal nodes to SignalTap analyzer input channels. Signals can be assigned to the.stp file with the use of the Quartus II Node Finder. Once the signal is displayed in the Node Finder, drag and drop it into the.stp file. The Node Finder can be accessed by selecting Insert Node or Bus in the right button pop-up menu from the SignalTap waveform window. f For more information on the Node Finder, use the Quartus II Help. The SignalTap analyzer can capture up to 128 internal nodes or I/O signals. The allowed number of captured signals is rounded to the nearest power of two (1, 2, 4, 8, etc.). As more signals are captured, the SignalTap analyzer uses more LEs. 6 Altera Corporation

Deleting Signals from the SignalTap File To delete signals from an.stp file, follow these steps: 1. Open an.stp file. 2. Select the node or group to remove. 3. Choose Delete (Edit menu or right button pop-up menu). Filter Control The Filter Control dialog box allows you to select signals from a specific instance in the design to be displayed in the SignalTap window. You can manage the signals that are displayed in the.stp file with the Filter Control option. Figure 3 shows the Filter Control dialog box. Figure 3. Filter Control Dialog Box Selecting an Acquisition Clock Signal The SignalTap acquisition clock must be a device signal. All input channels are sampled on the rising edge of the acquisition clock signal. Altera recommends using a global clock signal as the acquisition signal. Use the Node Finder to select the acquisition clock signal. f For more information on selecting the SignalTap acquisition clock, go to Assigning the SignalTap Logic Analyzer Clock in the Quartus II Help. Altera Corporation 7

Setting the Sample Buffer Depth When using the internal RAM configuration, the sample buffer depth governs the amount of data the SignalTap analyzer captures. As more signals are captured and the sample buffer depth is increased, more ESBs are used. See Figure 4. Figure 4. Setting the Sample Buffer Depth Setting the Trigger Position The trigger position specifies how much data is acquired before and after the trigger. Acquired data is placed into a circular buffer with new samples replacing old samples. Table 3 describes the ratios of pre-trigger to post-trigger data saved in the buffer for each trigger position choice. Table 3. Trigger Positions Name Description Pre-trigger Captures signals immediately after triggering (12% pre-trigger, 88% post-trigger) Center Captures signals before and after triggering (50% pretrigger, 50% post-trigger) Post-trigger Captures signals that occur immediately before triggering (88% pre-trigger, 12% post-trigger) Continuous trigger Captures signals indefinitely until stopped manually (Useful when using the Trigger Out feature) Setting the Trigger Pattern The SignalTap analyzer uses signal pattern recognition for triggering. The logic condition for each input signal to specify the trigger pattern is set within the Quartus II software. The SignalTap analyzer is triggered when the input signal matches the trigger pattern. 8 Altera Corporation

To define the trigger pattern, a logic condition for each input channel must be assigned. By default, all bits of a trigger pattern are set to the don't care setting, masking them from trigger recognition. The bits can be set to high, low, rising edge, falling edge, or either edge. f See the SignalTap Embedded Logic Analyzer Megafunction Data Sheet and Defining the Trigger Pattern in the Quartus II Help for more information on trigger patterns. Configuring the Communication Hardware Use the SignalTap logic analyzer interface to specify the communication cable hardware. Available communication cables include the MasterBlaster and ByteBlaster download cables, which transfer signal data to the Quartus II software. Figure 5 shows the communication hardware configuration box. Figure 5. Configuring the Communication Hardware Compiling the Project For the analyzer to capture and transmit data, the current project must be compiled with the.stp file. Specify the.stp file for compilation in the SignalTap Controls window. To open the SignalTap Controls window, go to Auxiliary Windows (View menu) and select SignalTap Controls. Figure 6 shows the SignalTap Controls window. Figure 6. SignalTap Controls Window Altera Corporation 9

SignalTap configuration changes, such as adding channels, changing the SignalTap clock signal, changing the buffer sample depth, or enabling the debug port, require recompilation of the design. Changing the trigger pattern or starting and stopping the analyzer does not require design recompilation. Table 4 shows the.stp file changes that require design recompilation. Table 4. Requirements for.stp File Changes Design Change Changing the trigger pattern Changing the trigger position Running or stopping the logic analyzer Changing the number of signals Assigning signals Changing the acquisition buffer depth Enabling trigger input or output Enabling the debug port Recompilation Required No No No Yes Yes Yes Yes Yes Once the project is successfully compiled, download the configuration information to the Altera device. To download data to the Altera device, use the Quartus II programmer or the download button in the SignalTap interface. SignalTap in a Multi-Device JTAG Chain The SignalTap analyzer can be used on any APEX or other supported device that is part of a multi-device JTAG chain. To use SignalTap in a multi-device JTAG chain, follow these steps: 1. Open the Quartus II Programmer 2. Create a Chain Description File (.cdf) that describes the device chain that is physically on the board. 3. Program the devices in the JTAG chain. 4. Open the Quartus II project for the device that requires SignalTap analysis. 5. Open the.stp file. 6. Select the SRAM Object File (.sof) for the device that requires analysis in the SignalTap JTAG dialog box. 10 Altera Corporation

f For more information on adding a device to the JTAG chain, see Adding or Replacing a Device in a JTAG Chain in Quartus II Help. Running the SignalTap Analyzer When the Run or Run-Continuous button is selected, data is continuously sampled on the rising edge of the acquisition clock. The acquisition data is placed in a circular buffer with new samples replacing old samples. When the SignalTap analyzer recognizes the trigger pattern, the analyzer either stops immediately or samples indefinitely, depending on the Run setting. Setting Up Debug Ports The debug port setting determines the routing of a SignalTap input signal to a spare I/O pin for capture by an external logic analyzer. When a SignalTap input signal is assigned to the debug port, the Quartus II software automatically generates a pin in the device design. The debug port pin is named stp_debug_out_1_<n>, where n is a number representing the order in which the debug port pin occurs in the signal list. By default, no input signals are routed to the debug port. Assign the debug port nodes to device pins and the design compiled after adding or deleting debug port signals. To add or remove a signal from the debug port, follow these steps: 1. Open an.stp file. 2. Select the signal in the Out field of the SignalTap window. 3. Choose Debug Port (right button pop-up menu). f Trigger Input & Trigger Output Go to Assigning a Signal to the Debug Port in the Quartus II Help for information on using the debug port. Trigger input and output signals synchronize the SignalTap embedded analyzer with external equipment, such as an oscilloscope or logic analyzer, which synchronizes the capture of internal and external events. Setting the Trigger Input Any I/O pin can trigger the SignalTap analyzer. The trigger input can be set to recognize a high, low, rising edge, falling edge, either edge, or don't care condition on the I/O pin. Altera Corporation 11

When a signal condition is assigned to the trigger input signal, the design generates the auto_stp_trigger_in_0 pin. This signal must then be assigned to a device pin and the design compiled. Changing the trigger signal condition after assigning the node does not require recompilation. To enable the trigger input signal, perform the following steps: 1. Open an.stp file. 2. In the Trigger In list, select the appropriate input condition. See Figure 7. Figure 7. Setting the Trigger Input Setting the Trigger Output A spare I/O pin set as a trigger output signal indicates when a trigger pattern occurs. The output pulse polarity is specified as either active high or active low. Enabling the trigger output signal generates the auto_stp_trigger_out_0 pin in the design. This signal must then be assigned to a device pin and the design compiled. Changing the trigger output settings does not require recompilation. To enable the trigger output signal, perform the following steps: 1. Open an.stp file. 2. In the Trigger Out list, select the appropriate output condition. See Figure 8. 12 Altera Corporation

Figure 8. Setting the Trigger Output Data Log The data log shows a history of captured data that is acquired with the SignalTap analyzer. The analyzer acquires data and then stores it in a log and displays it as a waveform. The default name for the log is a timestamp based on when the data was acquired, and the data is organized in a hierarchical manner. Similar logs of captured data are grouped together in Trigger Sets. To recall a data log from a given trigger set, double click on the data log. Trigger Sets Trigger sets represent the group of data logs that are acquired with identical signals in the.stp file. When signals are added or removed, a new trigger set is created. Subsequently, newly acquired data is stored in the new trigger set. The default for the trigger set is trigger_<timestamp>, where timestamp represents the time the trigger set is created. The engineer has the ability to disable the data log feature by de-selected the check box on the SignalTap interface. Figure 9 shows the Data Log window. Figure 9. The Data Log Window Conclusion With SignalTap analysis, internal device signals can be monitored in a variety of ways. The Quartus II software and either the MasterBlaster or ByteBlasterMV communication cable control analyzer configuration and triggering and system resource management. Data may be routed externally to unused I/O pins or to a JTAG port. SignalTap analyzer data is useful for debugging designs and optimizing system performance. Altera Corporation 13

Revision History The information contained in version 2.1 of AN 175: SignalTap Analysis in the Quartus II Software Version 2.0 supersedes information published in previous versions. Version 2.1 Version 2.1 of AN 175: SignalTap Analysis in the Quartus II Software Version 2.0 contains the following changes: Added text to page 1. 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Literature Services: lit_req@altera.com Copyright 2002 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 14 Altera Corporation