Image Generation in Microprocessor-based System with Simutaneous Video Memory Read/rite Access Mountassar Maamoun 1, Bouaem Laichi 2, Abdehaim Benbekacem 3, Daoud Berkani 4 1 Department o Eectronic, Bida University, Bida, Ageria 2 Department o Computer Science, USTHB, Agiers, Ageria. 3 LSIC Laboratory, (ENS Kouba, Agiers, Ageria 4 Signa & Communications Laboratory, (ENP, Agiers, Ageria Abstract: In this paper we present a new architecture o video memory data handing in microprocessorbased systems. This architecture is a soution or the rea time image processing systems which requires a signiicant recording time. The soution is based on a simutaneous video memory read/write. This operation is ensured by hardware spits o video memory in separate capacities and by association o a seecting circuit. This ater oers a state port and two communication ports. The irst communication port is used or reading and the second or writing. Key words: Video image generation, simutaneous video memory read/write, sotware/hardware System, microprocessor-based systems. 1 Introduction The video image generation in microprocessor-based systems is ensured by the video card or the graphic card. A video card is composed o severa unction units working in coordination. The starting point o any image is aways om the video RAM. This atter is a memory RAM that is on the video card and contains the image irmation to be dispayed. To generate a video image on the basis o a video RAM, the dierent components o the video card shoud compete the reading o its entire memory with a equency being abe to reach 75 cyces per second [1] igure 1. During this reading process, simutaneous access is authorized. This gives the possibiity o a writing process ony during the time o the return ine and ame. Under these operating conditions, the reaization o a dispay device or rea time image processing systems, which requires a signiicant recording time, remains very compicated. In this paper, we present a hardware/sotware soution [2] to enarge the recording access time. This soution consists in designing a dispay system which aows a simutaneous reading/writing access. VIDEO RAM DATA BUS ADDRESS BUS CONTROL BUS GENERATOR SYNCHRONIZING GENERATOR Figure 1. Graphic card bock diagram VIDEO SYNCHRONIZING The suggested architecture is composed o a hardware part and a sotware part. The hardware part is based on the memory capacity part o the video RAM with separate buses and on the association o a simutaneous seecting circuit. The sotware part ensures the data transer to the dispay system and the recording synchronization with the video RAM reading cyce.
2 Image generation in the video card The image, which represents the video card output signas, is the resut o repeated readings o the video RAM with a Digita-to-Anaog conversion (DAC [3] o the enabed data. The maximum time or the writing on this RAM during the ame is given by the oowing reation. T = T + T (1 w T Fr : The time o return ame. T Lr : The time o return ine N L : The number o ines within the ame r The ratio o the writing time over the tota time o the video ame generay varies om 10% to 15% and can be written in the oowing orm: The hardware part o our system is composed o our units: Interace Unit, Seection Unit, Reading Unit and Digita-to-Anaog Conversion (DAC Unit. The Interace Unit can use two types o addressing: the Extended Physica Addressing [4] or the Fast Physica Addressing [5]. The Seection Unit is connected to a the units and the video RAM. The Connection to the interace is made up o a state bus, a contro bus, an address bus and a data bus. The ink to the reading unit is made up o a contro bus and an address bus. The connection to the conversion unit is ensured by a one-way data bus which transers the seection unit data to the conversion unit. In this architecture o simutaneous access, the ratio o the writing time over the tota time o the video ame varies om 100% to a minima vaue r2. The ratio r2 is given by the oowing reation. r ( T + Tr = (2 T 1 r r 2 = + (3 2 2 T F : The tota time o the ame. 3 Image generation with simutaneous access by two eves The image generation system with simutaneous access by two eves represents the basic architecture o our system. This architecture o visuaization uses a video RAM made up o two RAMs. Both RAMs can be seected separatey; one can be seected in reading and the second in writing and vice versa. Figure 2 represents the bock diagram o the hardware part o this system. By using the reation (2, the expression o r2 coud be written in the oowing orm: r 2 1 ( T + Tr = + (4 2 2T Using the vaues o R o section 2, the ratio r2 varies om 55% to 57,5%. Reading Unit DAC Unit RAM 1 Interace Unit Seection Unit RAM 2 Fig 2. Two eves system bock diagram
Start Spit o Image Fie End o 1 RAM1 Read Cyce 1 data End o 1 2 End End o 2 Fig 3. Two eves system ow chart The sotware part is designed to carry out a process o permanent recording on the video RAM o this architecture. In the case o a simutaneous RAM2 Read Cyce 2 data access by two eves, the image ie is spit up into two parts: 1 and 2. Fie 1 represents the higher part o the image and ie 2 the ower part. The sotware aows the switching between data o ie 1 and ie 2. The synchronization o data is reated to the seection state o RAMs in our system. Figure 3 iustrates the main ow chart o the sotware part. 4 Image generation with simutaneous access by severa eves The principe o the image generation with simutaneous access by severa eves is simiar to the principe o construction in two eves. In this structure o visuaization, our system uses a video RAM made up o severa RAMs. The igure represents the bock diagram o the hardware part o this system. This is made up o our units: Interace Unit, Seection Unit, Reading Unit and Digita-to- Anaog Conversion (DAC Unit. The connection between the units uses the same structure o the two eves system. The size o the state bus depends on the number o the used RAMs. The ink between the seection unit and the used RAMs is ensured by severa buses: each bus is composed o a data bus, an address bus and a contro bus. Reading Unit DAC Unit RAM 1 Interace Unit Seection Unit RAM 2 RAM N Fig 4. N eves system bock diagram
This architecture gives a ratio o the writing time over the tota time o the video ame varies om 100% to a minima vaue RN. The ratio RN is given by the oowing orm: 1 r = ( 1 (5 N N rn + N: Represent the number o the RAMs used in our system. By using the reation (2, the expression o RN is written in the oowing orm: rn 1 ( T + Tr = ( 1 + (6 N T By using the ormua (6 and a vaue o R equas to 10%, RN can take severa vaues according to N. Tabe 1 presents the vaues RN or N varies om 1 to 100. The sotware part o the simutaneous access by severa eves spits up the image ie into severa parts. The resut gives N ies (1, 2, 3..., F N. The switching o data is done by N ies. The synchronization o the o data is reated to the state o seection o the N RAMs, which compose the video RAM o our system. Figure 5 presents the principa ow chart o the sotware part o the system at severa eves. Tabe 1: RN vaues N 1 2 3 4 5 6 7 8 9 RN 10% 55% 70% 77,5% 82% 85% 87,1% 88,75% 90% N 20 30 40 50 60 70 80 90 100 RN 95,5% 97% 97,75% 98,2% 98,5% 98,7% 98,87% 99% 99,1% Start Spit o Image Fie End o 1 End o 2 End o 3 End o N RAM1 Read Cyce RAM2 RAM3 RAMN Read Cyce Read Cyce Read Cyce 1 data 2 data 3 data N data End o 1 2 3. N Fig 5. N eves system ow chart End
5 Concusion The generation o the images in the video cards connected to the microprocessor-based systems uses repeated readings o the video memory contents. In this paper, we have exposed the main principes o the simutaneous access. e have presented the structure at two eves and then the structure at severa eves. The irst practica tests have given a recording rate o 95% or the two eves system and a rate o 98% or the three eves system. Structures higher than three eves have given rates ower than that o three and two eves. This characteristic is due to the compexity o the circuitry and the sotware processing time that is signiicant or the severa eves systems. Reerences: [1] M.Tischer. LA BIBLE PC. EDITIONS MICRO APPLICATION. France. 1997. [2] G.F.Marchiro. Découpage Transormationne pour a Conception de Systèmes Mixtes Logicie/Matérie. Thèse de Doctorat. Institut Nationa Poytechnique de Grebe. France. 1998. [3] Vijay K. Madisetti and Dougas B. iiams, Digita Signa Processing Handbook, CRC Press, 1999. [4] M.Maamoun and G.Zerari, Adressage Matérie dans es Systèmes à Microprocesseur avec un Adressage Physique Etendu, 2001 IEEE Canadian Conerence on Eectrica and Computer Engineering (CCECE01. IEEE Canada. Toronto, Ontario, Canada. 2001. [5] M.Maamoun, A.Benbekacem, D.Berkani, A.Guessoum, Interacing in Microprocessor-based Systems with a Fast Physica Addressing, The 3rd IEEE Internationa orkshop on System-on-Chip or Rea-Time Appications. Cagary, Aberta, Canada. 2003.