Representative Block Diagram. Outputs. Sound Trap/Luma Filter/Luma Delay/ Chroma Filter/PAL and NTSC Decoder/Hue and Saturation Control

Order this document by MC44/D The Motorola MC44, a member of the MC44 Chroma 4 family, is designed to provide RGB or YUV outputs from a variety of inputs. The inputs can be composite video (two inputs), S VHS, RGB, and color difference (R Y, B Y). The composite video can be PAL and/or NTSC as the MC44 is capable of decoding both systems. Additionally, R Y and B Y outputs and inputs are provided for use with a delay line where needed. Sync separators are provided at all video inputs. In addition, the MC44 provides a sampling clock output for use by a subsequent triple A/D converter system which digitizes the RGB/YUV outputs. The sampling clock (6. to 4 MHz) is phase locked to the horizontal frequency. Additional outputs include composite sync, vertical sync, field identification, luma, burst gate, and horizontal frequency. Control of the MC44, and reading of status flags, is via an I2C bus. Accepts NTSC and PAL Composite Video, S VHS, RGB, and R Y, B Y Includes Luma and Chroma Filters, Luma Delay Lines, and Sound Traps Digitally Controlled via I2C Bus R Y, B Y Inputs for Alternate Signal Source Line Locked Sampling Clock for A/D Converters Burst Gate, Composite Sync, Vertical Sync and Field Identification Outputs RGB/YUV Outputs can Provide 3. Vpp for A/D Inputs Overlay Capability Single Power Supply: V, ±5%, 55 mw (Typical) 44 Pin PLCC and QFP Packages 44 Device MC44FN MC44FB BUS CONTROLLED MULTISTANDARD VIDEO PROCESSOR SEMICONDUCTOR TECHNICAL DATA FB SUFFIX PLASTIC PACKAGE CASE 824E (QFP) ORDERING INFORMATION Operating Temperature Range TA = to +7 C FN SUFFIX PLASTIC PACKAGE CASE 777 (PLCC) 44 Package PLCC 44 QFP VCC Gnd Representative Block Diagram Outputs Y R Y B Y 4 R Y B Y Inputs Y2 R G B Fast Comm Comp Video Comp Video 2 Input Select Sound Trap/Luma Filter/Luma Delay/ Chroma Filter/PAL and NTSC Decoder/Hue and Saturation Control Color Difference Stage R/V G/Y B/U Outputs Vertical Output Field ID 7.7 MHz Sync Separator Vertical Decoder Select Sync Separator 4 MC44 Data Bus Contrast, Brightness, Saturation Control DACs I2C Data Interface/ Registers VCC2 Gnd2 SDL SCL To µp 4.3 MHz Filter Oscillator PLL PLL # Horizontal PLL/VCO PLL #2 Pixel Clock PLL/VCO VCC3 Gnd3 Burst Gate 6Fh/ CSync Filter Switch H Filter Quiet Gnd Fh Ref 5 k Ret PLL Filter Frequency Divider Clock To A/D Converters This document contains information on a new product. Specifications and information herein are subject to change without notice. Motorola, Inc. 996 Rev

MC44 Y Clamp Y B Y R Y R Y B Y Y2 B G R FC Comp Video Comp Video 2 ACC Filter 3 2 44 38 36 7 Ident Filter System Select Clock 4 37 9 4 39 Gnd2 V CC2 ( V) SCL SDL 2 3 35 8 4 7 9 5 6 8 To A/D Converters PLL #2 Filter 5 k Ret Gnd3 V CC3 ( V) Fh Ref 6Fh/ S/C Burst C Sync Gate 24 25 28 27 26 29 3 3 42 4 33 32 43 34 4.4/4.8/5.2 5.5/6./6.5 MHz Select Luma Delay Chroma Trap & Luma Peaking Sound Trap C C Ident PAL/NTSC Decoder ACC PAL/NTSC/S VHS Decoder Adaptive Sync Separator & Selector PLL Sync Separator & Selector From RGB & Y2 Inputs C Oscillator Sync Separator Vertical Decoder Comp Sync 2Fh Field ID Line Counter & Decoder 525, 625 Coincidence Vert. Sync Counter Separator 6Fh PLL #2 C 2Fo Voltage Monitor Calibration Circuit Fo U 2 2 4 MHz VCO Charge Pump D Phase & Frequency Comparator Phase Det VCO 64 23 Figure. Representative Block Diagram Inputs Outputs To Sync Sep X, X2, X8 Fs Notch Clamp Clamp Clamp Adj. Luma Delay Burst Gate Clamp Clamp Clamp C B Y R Y C Signal Selection Saturation/ Hue DACs B Y R Y Chroma Filter Y B Y R Y B G R Blank Color Matrix and Controls Saturation Contrast Blue Gain Red Gain Brightness Red DC Blue DC Bus Control & Flag Status Read 2 C Data Interface/ Registers 2 2 22 5 R/V G/Y B/U To µp Outputs H Fil Quiet GND H Filt Switch Frequency Divider 6 I DACs Color Difference Stage PLL # 6Fh Blank 2Fh Chroma PLL Filter 7.7 MHz Xtal Xtal 2 4.3 MHz Field ID V Vertical Sync NC I ref V CC ( V) Gnd Figure. 2

MC44 ELECTRICAL CHARACTERISTICS (The tested electrical characteristics are based on the conditions shown in Table and 2. Composite Video input signal =. Vpp, composed of:.7 Vpp Black to White;.3 Vpp Sync to Black;.3 Vpp Color Burst. VCC = VCC2 = VCC3 = V, Iref = 32 µa (Pin 9), unless otherwise noted.) Table. Control Bit Test Settings Control Bit Name Value Function $77 7 S VHS Y Composite Video input selected. $77 6 S VHS C Composite Video input selected. $77 5 FSI 5 Hz Field Rate selected. $77 4 L2 GATE PLL #2 Gating enabled. $77 3 BLCP Clamp Pulse Gating enabled. $77 2 L GATE Vertical Gating enabled. $77, CB, CA, Vertical section Auto Countdown mode $78 7 36/68 µs Time from beginning of Line 4 to Vertical Sync is 36 µs. $78 6 CalKill Horizontal Calibration Loop enabled. $79 7, 6 HI, VI, Normal $7A 7 Xtal = 7.7 MHz crystal selected, = 4.3 MHz crystal selected. $7A 6 SSD Normal $7B 7, 6 T, T2, Sound Trap Notch filter set to 5.5 MHz (with 7.7 MHz crystal). $7C 7 SSC Permits PAL and NTSC selection. $7C 6, $7D 6 SSA, SSB, = PAL decoding,, = NTSC decoding $7D 7, $7E 7, 6 P, P3, P2,, Sets Luma Peaking at db. $7F 7, 6, $8 6 D3, D, D2,, Set Luma Delay to minimum $8 7 RGB EN Fast Commutate input can enable RGB inputs. $8 7 Y2 EN Y2 input (Pin 29) deselected $8 6 Y EN Y luma path from PAL/NTSC decoder selected. $82 7 YUV EN RGB output mode selected $82 6 YX EN Disable luma matrix from RGB inputs. $83 7 L2 Gain Set PLL #2 Phase/Frequency detector gain high. $83 6 L Gain Set PLL # Phase Detector gain high. $84 7 H Switch Set Horizontal Phase Detector filter switch open. $84 6 525/625 = 625 lines (PAL), = 525 lines (NTSC) $85 7 Fosc 2 Select direct VCO output from PLL #2. $85 6 CSync 6 Fh output selected at Pin 3. $86 7 Vin Sync Composite Video inputs (Pin or 3) Sync Source selected. $86 6 H EN Enabled Horizontal Timebase. $87 7 Y2 Sync Y2 sync source not selected. $88 7 V2/V Select Video input (Pin ). $88 6 RGB Sync RGB inputs Sync Source not selected. Table 2. DAC Test Settings DAC Value Function DAC Value Function $78 32 R Y/B Y Gain $82 32 Red Contrast Trim $79 32 Sub Carrier Phase $83 32 Blue Brightness Trim $7D Blue Output DC Bias $84 32 Main Brightness $7E Red Output DC Bias $85 32 Red Brightness Trim $7F 63 Pixel Clock VCO Gain $86 32 Saturation (Color Diff.) $8 32 Blue Contrast Trim $87 6 Saturation (Decoder) $8 32 Main Contrast $88 32 Hue NOTE: Currents out of a pin are designated, and those into a pin are designated +. 3

MC44 MAXIMUM RATINGS Rating Symbol Value Unit Power Supply Voltage VCC.5 to +6. Vdc VCC2.5 to +6. VCC3.5 to +6. Power Supply Difference (Between any two VCC pins) ±.5 Vdc Input Voltage: Video, 2, SCL, SDL Vin.5, VCC +.5 Vdc Input Voltage: 5 khz Return.5, VCC3 +.5 Input Voltage: R Y, B Y, Y2, RGB, FC.5, VCC2 +.5 Junction Temperature (Storage and Operating) TJ 65 to +5 C NOTES:. Devices should not be operated at these limits. The Recommended Operating Conditions table provides for actual device operation. 2. ESD data available upon request. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit Power Supply Voltage VCC, 2, 3 4.75 5.25 Vdc Power Supply Difference (Between any two VCC pins) VCC.5.5 Vdc Input Voltage: Video, 2 (Sync White) Vin.7..4 Vpp Input Voltage: Chroma (S VHS Mode).2 Input Voltage: Y2.7..4 Input Voltage: RGB.5.7. Input Voltage: R Y, B Y (Pins 3, 3).8 Input Voltage: 5 khz Return VCC3 Vdc Input Voltage: SCL, SDL VCC Input Voltage: FC VCC2 Input Voltage: Burst Signal 3 28 56 mvpp Input Voltage: Sync Amplitude 6 3 VCC mvpp Output Load Impedance to Ground: RGB (Pull Up = 39 Ω) RLRGB. kω Output Load Impedance to Ground: B Y, R Y RLCD Output Load Impedance to Ground: Y RLY. Pull Up Resistance at Vertical Sync (Pin 4) RVS. kω Source Impedance: Video, 2. kω Source Impedance: Pins 26 to 3. Pixel Clock Frequency (Pin 8, see PLL #2 Electrical Characteristic) fpx 2. to 45 MHz 5 khz Return Pulse Width (Low Time) PW5k.2 45 µs I2C Clock Frequency fi 2 C khz Reference Current (Pin 9) Iref 32 µa Operating Ambient Temperature TA 7 C NOTE: All limits are not necessarily functional concurrently. ELECTRICAL CHARACTERISTICS (TA = 25 C, VCC = VCC2 = VCC3 = V, unless otherwise noted.) Characteristics Min Typ Max Unit POWER SUPPLIES Power Supply Current (VCC = V) Pin 4 75 95 5 ma Pin 23 6. 9. 2 Pin 9 3.5 6. 8. Total 85 35 4

MC44 ELECTRICAL CHARACTERISTICS (continued) (TA = 25 C, VCC = VCC2 = VCC3 = V, unless otherwise noted.) Characteristics Min Typ Max Unit PAL/NTSC/S VHS DECODER Video, 2 Inputs Crosstalk Rejection, f =. MHz 2 4 db (Measured at Y output, Luma Peaking = db, $77 7 = ) DC Level: @ Selected Input 2.8 Vdc DC Level: @ Unselected Input.7 Clamp Current 3 2 µa Sound Trap Rejection (See Figures 4 to 23) With 7.7 MHz Crystal: @ 6.5 MHz (T, T2 = ) 5 3 db With 7.7 MHz Crystal: @ 6. MHz (T, T2 = ) 5 3 With 7.7 MHz Crystal: @ 5.5 MHz (T, T2 = ) 43 With 7.7 MHz Crystal: @ 5.74 MHz (T, T2 = ) 5 26 With 4.3 MHz Crystal: @ 4.44 MHz (T, T2 = ) 35 R Y, B Y Outputs (Pins 4, 42) Output Amplitude (with % Saturated Color Bars) Saturation (DAC 87) = <. mvpp Saturation (DAC 87) = 6.6 Vpp Saturation (DAC 87) = 63.8 3. DC Level During Blanking 2.4 Vdc Hue Control Minimum Phase (DAC 88 = ) 3 Deg Hue Control Maximum Phase (DAC 88 = 63) 3 Nominal Saturation (with respect to Y Output, Note ) % R Y/B Y Ratio: Balance (DAC 78) = 63.35.69 2.6 V/V B Y/R Y Ratio: Balance (DAC 78) = 32.98.27.58 B Y/R Y Ratio: Balance (DAC 78) =.6.77.96 Output Amplitude Variation as Burst is varied from 8 mvpp to 6 mvpp 3. db Color Kill Attenuation ($7C 7, 6 and $7D 6 = ) 4 db Crosstalk with respect to Y Output (@. MHz) 27 2 Chroma Subcarrier Residual (Measured at Y Output, with 7.7 MHz Crystal) f = Subcarrier 25 6 mvpp 2nd Harmonic Residual 4. 2 4th Harmonic Residual 2 3 (Measured at R Y, B Y Outputs, with 7.7 or 4.3 MHz Crystal) f = Subcarrier 2 2nd Harmonic Residual 2 4th Harmonic Residual 5 5 Y Luma Output (Pin 33) Clamp Level.4..8 Vdc Output Impedance 3 Ω Composite Video Mode ($77 6, 7 = ) Output Level versus Input Level Delay =, Peaking =, f = khz...2 V/V Delay = Min to Max, Peaking = Min to Max. 3. db Bandwidth (7.7 MHz Crystal, PAL Decoding selected, 2.8 MHz Sound trap at 6.5 MHz, Peaking off) Peaking Range ($7D 7, $7E 6/7 = to, @ 3. MHz, with 7.7 MHz Crystal, 8. db Sound trap at 6.5 MHz) Overshoot with Minimum Peaking % Differential Non linearity (Measured with Staircase) 2. % Delay (Pin or 3 to 33) With 4.3 MHz Crystal: Minimum 69 ns Maximum 4 With 7.7 MHz Crystal: Minimum 594 Maximum 876 NOTE:. This spec indicates a correct output amplitude at Pins 4 and 42, with respect to Y output. For standard color bar inputs, the output amplitude is NOTE:. between.5 and.7 Vpp, with the settings in Tables and 2. 5

MC44 ELECTRICAL CHARACTERISTICS (continued) (TA = 25 C, VCC = VCC2 = VCC3 = V, unless otherwise noted.) Characteristics Min Typ Max Unit PAL/NTSC/S VHS DECODER S VHS Mode ($77 6, 7 = ) Output Level versus Input Level (Delay = Min to Max)...2 V/V 3. db Bandwidth (7.7 MHz crystal, PAL Decoding selected, 4.5 MHz Sound trap at 6.5 MHz) Y/C Crosstalk Rejection 2 4 db Delay (Luma input to Pin 33) 4.3 MHz Crystal: Minimum 395 ns 4.3 MHz Crystal: Maximum 745 7.7 MHz Crystal: Minimum 35 7.7 MHz Crystal: Maximum 632 Crystal Oscillator PLL Pull in range with respect to Subcarrier Frequency (Burst Level 3 mvpp): with 7.7 MHz Crystal ±35 Hz (Burst Level 3 mvpp): with 4.3 MHz Crystal ±3 4fsc Filter (Pin 44) DC Voltage @ 4.3 MHz 2.4 Vdc @ 7.7 MHz 3.5 No Burst present.3 DC Voltages System Select (Pin 34) NTSC Mode (SSA =, SSB =, SSC =, SSD = ).5.75 2. PAL Mode (SSA =, SSB =, SSC =, SSD = ).75.4 Color Kill Mode (SSA =, SSB =, SSC =, SSD = ).75 External Mode (SSA = X, SSB = X, SSC =, SSD = ) 3.7 4. 4.3 Ident Filter (Pin 43) NTSC Mode.6 PAL Mode.2.5.8 No Burst present.2 ACC Filter (Pin 2) No Burst present.25 Threshold for ACC Flag on.8.2.6 Burst = 5 mvpp.4 Burst = 28 mvpp.7 System Select Output Impedance 4 kω COLOR DIFFERENCE SECTION RGB/YUV Outputs Output Swing, Black to White (DAC $8 = 63) 2. 3. Vpp THD (RGB Inputs to RGB Outputs @. MHz,.7 Vpp).5 2. % 3. db Bandwidth 6. MHz Clamp Level RGB Outputs ($7D, 7E = ).4 Vdc UV Outputs ($7D, 7E = 32) 2.3 Red, Blue Clamp Level Change (DACs $7D, 7E varied from to 63).85.8 2.4 Crosstalk Rejection Among RGB Outputs @. MHz 2 4 db Y to Y2 2 4 From RGB Outputs to Y or Y2 2 4 Input Black Clamp Voltage at Y2, B Y, R Y, and RGB 2.4 3. 3.6 Vdc Fast Commutate Input (Pin 25) Switching Threshold Voltage.5 Vdc Input Current @ Vin = V 7.5 µa Input Current @ Vin = V Timing: Input Low to High (RGB Enable) 5 ns Timing: Input High to Low (RGB Disable) 9 Vdc 6

MC44 ELECTRICAL CHARACTERISTICS (continued) (TA = 25 C, VCC = VCC2 = VCC3 = V, unless otherwise noted.) Characteristics Min Typ Max Unit COLOR DIFFERENCE SECTION Contrast (Gain) V/V Y to RGB (DAC $8 = 32, DAC $86 = ).9 2.4 3. Y2 to RGB (DAC $8 = 32, DAC $86 = ).8 2.3 2.8 Green In (Pin 27) to Green Out (Pin 2) with YX Enabled.8 2.3 2.4 ($82 6 =, DAC $8 and DAC $86 = 32) Red to Green and Blue to Green Gain Ratio.8..2 RGB Input to RGB Output with YX Not Enabled 2. 2.6 3.2 ($82 6 =, DAC $8 and DAC $86 = 32) Ratio (DAC $8 = versus 32).2.4 Ratio (DAC $8 = 63 versus 32).5 2. 2.5 Red and Blue Trim Control (DACs $8, 82 varied from to 63) ± ±3 ±6 % Saturation (Average of R, G, B saturation levels with respect to Luma) Inputs at Pins 29 to 3 (DAC $86 = 32) 5 9 3 % Ratio (DAC $86 = versus 32) 5 Ratio (DAC $86 = 63 versus 32) 5 7 9 Inputs at Pins 26 to 28 (DAC $86 = 32, $82 6 = ) 7 25 8 Brightness Black Level Range (Brightness = to 63 with respect to Brightness setting of 32) ±.3 ±.5 ±.7 Vdc Red and Blue Trim Control (DACs $83, 85 varied from to 63) ±.5 ±.3 ±.6 Color Coefficients G Y Matrix Coefficient versus B Y.2.9.7 G Y Matrix Coefficient versus R Y.56.5.46 YX Matrix (Inputs at Pins 26 to 28, $82 6 = ): Y versus R.28.3.32 Y versus G.57.59.6 Y versus B.9..3 HORIZONTAL TIME BASE SECTION (PLL #) Free Running Period (Calibration mode in effect, Bit $86 6 = ) 7.7 MHz Crystal selected ($84 6 = ) 62.5 64. 65.5 µs 4.3 MHz Crystal selected ($84 6 = ) 62.5 63.5 65.5 VCO minimum period (Pin Voltage at.2 V) 56 59.5 62 µs VCO maximum period (Pin Voltage at 2.8 V) 66 69.5 72 VCO Control Gain factor 8.5 2 µs/v Phase Detector Current High Gain ($83 6 = ) 5 5 85 µa Low Gain to High Gain Current Ratio.32.38.44 µa/µa Noise Gate Width ($77 2 =, Low Gain, see Figure 26) 6 µs Horizontal Filter Switch (Pin 2) Saturation Voltage (I2 = 2 µa) mv Dynamic Impendance ($84 7 = ) < kω Parallel Resistance ($84 7 = ).6. MΩ Pins 8, 3, 4 Output Level High (lo = 4 µa) 2.4 4.5 Vdc Low (lo = 8 µa)..8 Burst Gate (Pin 8) Timing (See Figures 25, 27) µs Rising edge from Sync leading edge (Pins, 3) 4.4 5.6 6.8 Rising edge from Sync center (Pins 26 to 29) 2.5 Pulse Width 3. 3.5 4. 6Fh Output (Pin 3) Timing (Bit $85 6 = ) (See Figures 25, 27) Rising edge from Fh rising edge.3 µs Duty Cycle 5 % Composite Sync Output (Pin 3) Timing (Bit $85 6 = ) µs Input Sync center to Output Sync center (Pins, 3).95 Input Sync center to Output Sync center (Pins 26 to 29).4 7

MC44 ELECTRICAL CHARACTERISTICS (continued) (TA = 25 C, VCC = VCC2 = VCC3 = V, unless otherwise noted.) Characteristics Min Typ Max Unit HORIZONTAL TIME BASE SECTION (PLL #) Fh Reference (Pin 4) Timing (See Figures 25, 27) Rising edge from Sync center (Pins, 3).3 µs Rising edge from Sync center (Pins 26 to 29) 65 ns Duty cycle 5 % Sandcastle Output (Pin 35, see Figures 25, 27) Vdc Output Voltage Level 3.7 4. 4.3 Output Voltage Level 2 2.8 3. 3.2 Output Voltage Level 3.55 Output Voltage Level 4.7 Rising edge from Sync center (Pins, 3) 2.6 µs Rising edge from Sync center (Pins 26 to 29) 3.3 High Time 6. Level 2 Time Reference Voltage @ Pin 9 (Iref = 32 µa)..2.4 Vdc PHASE LOCKED PIXEL CLOCK SECTION (PLL #2) VCO Frequency @ Pin 8 Minimum (Pin 6 =.6 V, $85 7 = ) 2. 4. Maximum (Pin 6 = 4. V, $85 7= ) 3 45 6 VCO Up (Flag 9) Threshold Voltage @ Pin 6.5.7.9 Vdc VCO Down (Flag 2) Threshold Voltage @ Pin 6 3. 3.3 3.5 VCO Control Voltage Range @ Pin 6.2 3.8 Vdc VCO Control Gain factor ($7FDAC =, $85 7 = ) 4. 8. 2 MHz/V Charge Pump Current (Pin 6) 25 5 75 µa High Gain ($83 7 = ) Current Ratio.3.4.5 µa/µa Low Gain to High Gain Pixel Clock Output (Pin 8) (Load = 3 FAST TTL loads + pf) Output Voltage High 3.9 Vdc Output Voltage Low.5 Rise Time @ 5 MHz 7. ns Rise Time @ 9. MHz 7 Fall Time @ 5 MHz Fall Time @ 9. MHz 8. 5 khz Return (Pin 5) Input Threshold Voltage.5 Vdc Falling edge from Fh rising edge 6 ns Minimum Input Low Time 2 VERTICAL DECODER Vertical Frequency Range 43.3 22 Hz Vertical Sync Output Saturation Voltage (lo = 8 µa)..8 V Leakage Current @ V (Output high) 4 µa Timing from Sync polarity reversal to Pin 4 falling edge (See Figures 33, 34) µs ($78 7 = ) 32 36 4 ($78 7 = ) 62 68 74 Vertical Sync Pulse Width (Pin 4, NTSC or PAL) 49 5 5 µs Field Ident (Pin 7) Output Voltage High (lo = 4 µa) 2.4 4.5 Vdc Field Ident (Pin 7) Output Voltage Low (lo = 8 µa)..8 Field Ident (Pin 7) Timing Fig. 33, 34 HORIZONTAL SYNC SEPARATOR Sync Slicing Levels (Pins, 3) 2 mv From Black Level (Pins 26 to 29) 5 MHz 8

MC44 PIN FUNCTION DESCRIPTION FB FN QFP PLCC Pin Representative Circuitry (Pin numbers refer to PLCC package) Description (Pin numbers refer to PLCC package) 39, 4, 3 Video Input.47 47 47 pf M 2 k Video Input & 2 Video (Pin ) and Video 2 (Pin 3) are composite video inputs. Either can be NTSC or PAL. Input impedance is high, termination must be external. Also used for the luma and chroma components of an S VHS signal. Selection of these inputs is done by software. External components protect against ESD and noise. 4 2. 2 ACC Filter A. µf capacitor at this pin filters the feedback loop of the chroma automatic gain control amplifier. Input chroma burst amplitude can be between 3 and 6 mvpp. 42 4 k Vertical Sync 4 Vertical Sync Output An open collector output requiring an external pull up. Output is an active low pulse, 5 µs wide, occurring each field. Timing of this pulse depends on Bit $78 7. 43 5 From MCU 5 k SCL Clock for the I2C bus interface. See Appendix C for specifications. Maximum frequency is khz. 44 6 To/ From MCU 6 8 k SDL Bidirectional data line for the I2C bus interface. As an output, it is an open collector. (Write Address $8A, Read Address $8B) 7 k Field ID TTL level output indicating Field or Field 2. Polarity depends on state of Bit $78 7 (Vertical Sync Delay). See Table and Figure 33 and 34. Field ID 7 2 k 2 8 (Same as Pin 7) Burst Gate TTL level output used for external clamps, as well as internally. Pulse is active high, 3.5 µs wide, with the rising edge 3. µs after center of selected incoming sync pulse. 3 9 k 2.2 µf / /. 9 2 k 8. k Reference Current Input Current supplied to this pin, typically 32 µa from V through a kω resistor, is the reference current for the calibration circuit. Noise filtering should be done at the pin. Voltage at this pin is typically.2 V. 4 (See power distribution diagram at the end of this section.) Quiet Ground Ground for the horizontal PLL filter (PLL #) at Pin. 9

MC44 PIN FUNCTION DESCRIPTION (continued) FB FN QFP PLCC Pin 5 Representative Circuitry (Pin numbers refer to PLCC package) k 68 pf. Description (Pin numbers refer to PLCC package) H Filter Components at this pin filter the output of the phase detector of PLL #. This PLL becomes phase locked to the selected incoming horizontal sync. External component values are valid for NTSC and PAL systems. 6 2 47 pf 2 k 2. M H Filter Switch An internal switch to ground which permits altering the filtering action of the components at Pin. 7 3 (Same as Pin 7) 6 Fh/CSync A TTL level output from PLL #. This pin provides either a square wave equal to Fh x 6 ( 25 khz), or composite sync, depending on the setting of Bit $85 6. 8 4 (Same as Pin 7) Fh Reference A TTL square wave output which is phase locked to the selected incoming horizontal sync. The rising edge occurs.3 µs after sync center. 9 5 5 khz Return 5 k 2 k 5 khz Return This TTL input receives the output of an external frequency divider which is part of PLL #2 (Pixel Clock PLL). This signal will be phase and frequency locked to the Fh signal at Pin 4. If PLL #2 is not used, this pin should be connected to a V supply. 6. k 6.47 k 47 pf 6 Down. k 6. k Gain Up Vert Gate PLL #2 Filter Components at this pin filter the output of the phase detector of PLL 2. This PLL becomes phase locked to the Fh signal at Pin 4. Recommended values for filter components are shown. External components should be connected to ground at Pin 7. If PLL #2 is not used, this pin should be grounded. 7 (See power distribution diagram at the end of this section.) Gnd3 Ground for the high frequency PLL #2. Signals at Pins 5 to 9 should be referenced to this ground. 2 8 2 Pixel Clock Output Sampling clock output (TTL) for external A/D converters, and for the external frequency divider. Frequency range at this pin is 6. to 4 MHz. Pixel Clock Output 8

MC44 PIN FUNCTION DESCRIPTION (continued) FB FN QFP PLCC Pin 3 9 4 2 Representative Circuitry (Pin numbers refer to PLCC package) (See power distribution diagram at the end of this section.) Color & Gain Brightness 36 k 2 V 39 Output Description (Pin numbers refer to PLCC package) VCC3 A V supply (±5%), for the high frequency PLL #2. Decoupling must be provided from this pin to Pin 7. Ripple on this pin will affect pixel clock jitter. R/V Output Red (in RGB mode), or R Y (in YUV mode), output from the color difference stage. A pull up (39 Ω) to V is required. Blank level is.4 Vdc. Maximum amplitude is 3. Vpp, black to white. 5 2 6 22 7 23 8 24 9 25 (Same as Pin 2) (Same as Pin 2) (See power distribution diagram at the end of this section.) (See power distribution diagram at the end of this section.) 25 G/Y Output Green (in RGB mode), or Y (in YUV mode), output from the color difference stage (same as Pin 2). B/U Output Blue (in RGB mode), or B Y (in YUV mode), output from the color difference stage (same as Pin 2). VCC2 A V supply (±5%), for the color difference stage. Decoupling must be provided from this pin to Pin 24. Gnd2 Ground for the color difference stage. Signals at Pins 2 to 3 should be referenced to this pin. FC Fast Commutate switch. Taking this pin high (TTL level) connects the RGB inputs (Pins 26 to 28) to the RGB outputs (Pins 2 to 22), permitting an overlay function. The switch can be disabled in software (Bit $8 7). 2, 2, 22 26, 27, 28 R, G, B Inputs Vref k Blue (26), Green (27), Red (28) Inputs Inputs to the color difference stage. Designed to accept standard analog video levels, these input pins have a clamp and sync separator. They are selected with Pin 25 or in software (Bit $8 7). 23 29 Y2 Input 29 Vref k Y2 Input Luma #2/Composite sync input. This luma input to the color difference stage is used in conjunction with auxiliary color difference inputs, and/or as a sync input. Clamp and sync separator are provided. 24, 25 3, 3 R Y, B Y Inputs Vref k B Y (3), R Y (3) Inputs Inputs to the color difference stage. Designed for standard color difference levels, these inputs can be capacitor coupled from the color difference outputs, from a delay line, or an auxiliary signal source. Input clamp is provided. 26 32 Y Clamp A.47 µf capacitor at this pin provides clamping for the Luma # output..47 32

MC44 PIN FUNCTION DESCRIPTION (continued) FB FN QFP PLCC Pin 27 33 Representative Circuitry (Pin numbers refer to PLCC package) Y Output 33 Description (Pin numbers refer to PLCC package) Y Output Luma # output. This output from the PAL/NTSC/S VHS decoder is the luma component of the decoded composite video at Pin or 3. It is internally directed to the color difference stage. 28 34 System Select 34 System Select A multi level dc output which indicates the color decoding system to which the PAL/NTSC detector is set by the software. This output is used by the MC444 chroma delay line. 29 35 Sandcastle Pulse 35 Sandcastle Pulse A multi level timing pulse output used by the MC444 chroma delay line. This pulse encompasses the horizontal sync and burst time. 3, 32 36, 38 R = 4 Ω at Pin 38 R = 3 Ω at Pin 36 4.3 MHz 7.7 MHz 2 µa R Xtal 2 (36), Xtal (38) Designed for connection of 4x subcarrier color crystals. Selection is done in software. The selected frequency is used by the PAL/NTSC detector; system identifier; all notches and traps; delay lines; and the horizontal calibration circuit. The crystal frequency should be: 4.3 MHz at Pin 36 for NTSC, 7.7 MHz at Pin 38 for PAL. (See Table 7 for crystal specifications) 3 37 No Connect This pin is to be left open. 33 39 (See power distribution diagram at the end of this section.) Ground Ground for all sections except PLL #2 and the color difference stage. 34 4 35 4 (See power distribution diagram at the end of this section.) B Y 4 VCC A V (±5%), supply to all sections except PLL #2 and the color difference stage. B Y Output Output from the PAL/NTSC decoder, it is typically capacitor coupled to a delay line or to the B Y input. This pin is clamped, and filtered at the color subcarrier frequency, 2x, and 8x that frequency. 36 42 (Same as Pin 4) R Y Output Output from the PAL/NTSC decoder. 37 43 Ident Filter A. µf capacitor filters the system identification circuit in the NTSC/PAL decoder.. 43 2

MC44 PIN FUNCTION DESCRIPTION (continued) FB FN QFP PLCC Pin 38 44 Representative Circuitry (Pin numbers refer to PLCC package) Description (Pin numbers refer to PLCC package) Crystal PLL Filter Components at this pin filter the PLL for the crystal chroma oscillator circuit. 47 k. 44 22 pf 4,, 3, 7, 8, 33, 34, 7, 9, 23, 24, 39, 4 7. V VCC VCC2 7. V 7. V (Dashed lines indicate substrate connection.) VCC3 Power Distribution The three VCC pins must be externally connected to V (±5%) supply. The four grounds must be externally tied together, preferably to a ground plane. 3

MC44 db GAIN AT Y RELATIVE TO VIDEO 2 3 4 5. Luma Frequency Response (4.3 MHz) Crystal, (4.5 MHz) Sound Trap Figure 2. Composite Video Mode Peaking Sound Trap =, db GAIN AT Y RELATIVE TO VIDEO Figure 3. S VHS Mode Sound Trap =, All Peaking Settings 5. 3. 7... 3. 7. f, FREQUENCY (MHz) f, FREQUENCY (MHz) 2 3 4 db GAIN AT Y RELATIVE TO VIDEO 2 3 4 5. Luma Frequency Response (7.7 MHz) Crystal, (5.5 MHz) Sound Trap Figure 4. Composite Video Mode Peaking db GAIN AT Y RELATIVE TO VIDEO Figure 5. S VHS Mode Sound Trap =, All Peaking Settings Sound Trap =, 5. 3. 7... 3. 7. f, FREQUENCY (MHz) f, FREQUENCY (MHz) 2 3 4 db GAIN AT Y RELATIVE TO VIDEO 2 3 4 5. Luma Frequency Response (7.7 MHz) Crystal, (5.5/5.75 MHz) Sound Trap Figure 6. Composite Video Mode Sound Trap =, Peaking db GAIN AT Y RELATIVE TO VIDEO Figure 7. S VHS Mode Sound Trap =, All Peaking Settings 5. 3. 7... 3. 7. f, FREQUENCY (MHz) f, FREQUENCY (MHz) 2 3 4 4

MC44 Luma Frequency Response (7.7 MHz) Crystal, (6. MHz) Sound Trap db GAIN AT Y RELATIVE TO VIDEO 2 3 4 Figure 8. Composite Video Mode f, FREQUENCY (MHz) Peaking Sound Trap =, db GAIN AT Y RELATIVE TO VIDEO Figure 9. S VHS Mode f, FREQUENCY (MHz) Sound Trap =, All Peaking Settings 5 5.. 3. 7... 3. 7. 2 3 4 db GAIN AT Y RELATIVE TO VIDEO 2 3 4 5. Luma Frequency Response (7.7 MHz) Crystal, (6.5 MHz) Sound Trap Figure. Composite Video Mode Peaking Sound Trap =, f, FREQUENCY (MHz) f, FREQUENCY (MHz) db GAIN AT Y RELATIVE TO VIDEO Figure. S VHS Mode Sound Trap =, All Peaking Settings 5. 3. 7... 3. 7. 2 3 4 db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 3. Figure 2. (3.58 MHz) Chroma Notch Gain at Peaking = Sound Trap =, 4.3 MHz Crystal db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 Gain at Peaking = Figure 3. (4.43 MHz) Chroma Notch Sound Trap =, 7.7 MHz Crystal 4 3.5 4. 4. 4.5 f, FREQUENCY (MHz) f, FREQUENCY (MHz) 5

MC44 db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 45 4. Figure 4. Composite Video Mode Sound Trap =, Peaking = 4.3 MHz Crystal f, FREQUENCY (MHz) (4.5 MHz) Sound Trap db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 Figure 5. S VHS Mode Sound Trap =, 35 Peaking = 4.3 MHz Crystal 4 4.5 4. 4.5 f, FREQUENCY (MHz) db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 45 Figure 6. Composite Video Mode Sound Trap =, Peaking = 7.7 MHz Crystal (5.5 MHz) Sound Trap Sound Trap =, Peaking = 7.7 MHz Crystal 45 5.5 6. 5.5 6. f, FREQUENCY (MHz) f, FREQUENCY (MHz) db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 Figure 7. S VHS Mode db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 Figure 8. Composite Video Mode Sound Trap =, Peaking = 7.7 MHz Crystal (5.5 + 5.75 MHz) Sound Trap db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 Figure 9. S VHS Mode Sound Trap =, Peaking = 7.7 MHz Crystal 45 5.4 5.8 6.2 6.6 5.4 5.8 6.2 6.6 f, FREQUENCY (MHz) f, FREQUENCY (MHz) 6

MC44 db GAIN AT Y RELATIVE TO VIDEO db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 5.5 5 2 25 3 35 4 45 6. Figure 2. Composite Video Mode f, FREQUENCY (MHz) Sound Trap =, Peaking = 7.7 MHz Crystal Figure 22. Composite Video Mode Sound Trap =, Peaking = 7.7 MHz Crystal (6. MHz) Sound Trap db GAIN AT Y RELATIVE TO VIDEO db GAIN AT Y RELATIVE TO VIDEO 5 2 25 3 35 4 Figure 2. S VHS Mode f, FREQUENCY (MHz) Figure 23. S VHS Mode Sound Trap =, Peaking = 7.7 MHz Crystal 45 6. 6.5 5.5 6. 6.5 (6.5 MHz) Sound Trap 5 2 25 3 35 4 Sound Trap =, Peaking = 7.7 MHz Crystal 45 6.5 7. 6. 6.5 7. f, FREQUENCY (MHz) f, FREQUENCY (MHz) Figure 24. FC Input Current µ A) 2 INPUT CURRENT l in, ( 4 6 8 VCC = V. 2. 3. 4. PIN 25 VOLTAGE (V) 7

MC44 Figure 25. Horizontal PLL Timing/Composite Video Inputs Video Input (@ Pins or 3) LC Burst Gate (Pin 8) 3. µs 3.5 µs 4.5 V 4.5 V Fh Ref (Pin 4).3 µs /2Fh 6Fh Out (Pin 3).3 µs 4.5 V /6Fh Comp Sync Out (Pin 3).7 µs 3.3 µs (.4 µs during vertical interval) 4.5 V 2.6 µs 4. V Sandcastle Out (Pin 35) 5.9 µs µs 3. V.55 V V NOTE: In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin or 3. Above timings based on a 4.6 µs wide sync pulse. Lower two levels of Sandcastle output alternate, based on video system in effect. All timings are nominal, and apply to both PAL and NTSC signals. Figure 26. Horizontal PLL Noise Gate and Filter Pin Video Input (@ Pins or 3) Noise Gate 6 µs Charge Pump Current (Pin ) Voltage Waveform (Pin ) 7 mvpp with High Gain 25 mvpp with Low Gain 8

MC44 Figure 27. Horizontal PLL Timing/R, G, B and Y2 Inputs C L Video Input (@ Pins 26 to 29) Burst Gate (Pin 8) 2.5 µs 3.5 µs 4.5 V 4.5 V Fh Ref (Pin 4) 65 ns /2Fh 6Fh Out (Pin 3).3 µs 4.5 V /6Fh Comp Sync Out (Pin 3) 2. µs 4.7 µs (.4 µs during vertical interval) 4.5 V 3.3 µs 4. V Sandcastle Out (Pin 35) 5.9 µs µs 3. V.55 V V R, G, B Outputs (@ Pins 2 to 22) C L 7 ns NOTE: In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin 26 to 28, or 29. Above timings based on a 4.6 µs wide sync pulse. Lower two levels of Sandcastle output alternate, based on video system in effect. 9

MC44 Figure 28. System Timing/Video Inputs to RGB Outputs 5% Video Input (@ Pins or 3) 7 ns 5% R Y, B Y Outputs (@ Pins 4, 42) 85 ns 5% R, G, B Outputs (@ Pins 2 to 22) Figure 29. Fast Commutate Timing Input @ Pin 25.5 V.5 V 5 ns 9 ns R, G, B Outputs (@ Pins 2 to 22) 5% 5% Color Difference Inputs Enabled RGB Inputs Enabled Color Difference Inputs Enabled 2

MC44 Figure 3. Horizontal Outputs versus Fields (NTSC System) Line Field 2 Field Composite Input (@ Pins, 3, 26 to 29) Fh Ref (Pin 4) Burst Gate (Pin 8) Composite Sync (Pin 3) Field Field 2 Composite Input (@ Pins, 3, 26 to 29) Fh Ref (Pin 4) Burst Gate (Pin 8) Composite Sync (Pin 3) 2

MC44 Figure 3. Horizontal Outputs versus Fields (PAL System) Line Composite Input (@ Pins, 3, 26 to 29) Field 2/4 Field /3 Fh Ref (Pin 4) Burst Gate (Pin 8) Composite Sync (Pin 3) Composite Input (@ Pins, 3, 26 to 29) Field /3 Field 2/4 Fh Ref (Pin 4) Burst Gate (Pin 8) Composite Sync (Pin 3) Figure 32. Horizontal PLL2 Timing Fh Ref (Pin 4) 6 ns 5 khz Return (Pin 5) Determined by External Circuit (Must be > 2 ns) 22

MC44 Figure 33. Vertical Timing (NTSC System) A) Bit $78 7 = Line Video Input Vert Sync Out (Pin 4) Field 2 Field 36 µs 5 µs Field Ident Out (Pin 7) µs Video Input Vert Sync Out (Pin 4) Field Field 2 36 µs 5 µs Field Ident Out (Pin 7) 68 µs B) Bit $78 7 = Line Video Input 68 µs Vert Sync Out (Pin 4) Field 2 Field 5 µs Field Ident Out (Pin 7) µs Video Input Vert Sync Out (Pin 4) Field Ident Out (Pin 7) Field Field 2 68 µs 5 µs 44 µs 23

MC44 Figure 34. Vertical Timing (PAL System) A) Bit $78 7 = Line Video Input Vert Sync Out (Pin 4) Field Ident Out (Pin 7) Field 2/4 36 µs Field /3 µs 5 µs Video Input Vert Sync Out (Pin 4) Field Ident Out (Pin 7) Field /3 36 µs Field 2/4 68 µs 5 µs B) Bit $78 7 = Line Video Input Vert Sync Out (Pin 4) 68 µs 5 µs Field 2/4 Field /3 Field Ident Out (Pin 7) µs Video Input Vert Sync Out (Pin 4) Field Ident Out (Pin 7) Field /3 68 µs Field 2/4 44 µs 5 µs 24

Introduction The MC44, a member of the MC44 Chroma 4 family, is a composite video decoder which has been tailored for applications involving multimedia, picture in picture, and frame storage (although not limited to those applications). The first stage of the MC44 provides color difference signals (R Y, B Y, and Y) from one of two (selectable) composite video inputs, which are designed to receive PAL, NTSC, and S VHS (Y,C) signals. The second stage provides either RGB or YUV outputs from the first stage s signals, or from a separate (internally selectable) set of RGB inputs, permitting an overlay function to be performed. Adjustments can be made to saturation; hue; brightness; contrast; brightness balance; contrast balance; U and V bias; subcarrier phase; and color difference gain ratio. The above mentioned video decoding sections provide the necessary luma/delay function, as well as all necessary filters for sound traps, luma/chroma separation, luma peaking, and subcarrier rejection. External tank circuits and luma delay lines are not needed. For PAL applications, the MC444 chroma delay line provides the necessary line by line corrections to the color difference signals required by that system. The MC44 provides a pixel clock to set the sampling rate of external A/D converters. This pixel clock, and other horizontal frequency related output signals, are MC44 FUNCTIONAL DESCRIPTION phase locked to the incoming sync. The VCO s gain is adjustable for optimum performance. The MC44 also provides vertical sync and field identification (Field, Field 2) outputs. Selection of the various inputs, outputs, and functions, as well as the adjustments, is done by means of a two wire I2C interface. The basic procedure requires the microprocessor system to read the internal flags of the MC44, and then set the internal registers appropriately. This I2C interface eliminates the need for manual controls (potentiometers) and external switches. All of the external components for the MC44, except for the two crystals, are standard value resistors and capacitors, and can be non precision. (The DACs mentioned in the following description are 6 bits wide. The settings mentioned for them are given in decimal values of to 63. These are not hex values.) PAL/NTSC/S VHS Decoder A block diagram of this decoder section is shown in Figure 35. This section s function is to take the incoming composite video (at Pins or 3), separate it into luma and chroma information, determine if the signal is PAL or NTSC (for the flags), and then provide color difference and luma signals at the outputs. If the input is S VHS, the luma/chroma separation is bypassed, but the other functions are still in effect. Figure 35. PAL/NTSC/S VHS Decoder Block Diagram Comp Video Comp Video 2 Chroma PLL Filter Xtal Xtal 2 3 ACC Filter 2 44 38 36 Select ($88 7) To Sync Sep 4.4/4.8/5.2 5.5/6./6.5 MHz ($7B 7,6) Sound Trap C ($77 6) Chroma Filter PLL Oscillator Phase Adjust ($79 5/) Switches shown with control bits =. Crystal Select ($7A 7) Chroma Trap and Luma Peaking ($7D 7; $7E 7,6) Flag 23 (ACC Active) C ACC 295/244 ns Luma Delay Flag 24 (PAL) PAL/NTSC Decoder ($77 7) Saturation ($87 5/) Hue ($88 5/) Color Balance ($78 5/) Blanking Color System ($7C 7,6; $7D 6) Ident Circuit To Color Diff Stage Adjustable Luma Delay 33 ($7F 7,6; $8 6) 32 3.6/7.2/28.6/4.4/ 8.8/35.4 MHz Notch C 3.6/7.2/28.6/4.4/ 8.8/35.4 MHz Notch 34 43 42 4 Y Out Y Clamp System Select Ident Filter R Y Out B Y Out 25

Inputs The inputs at Pins and 3 are high impedance inputs designed to accept standard. Vpp positive video signals (with negative going sync). The inputs are to be capacitor coupled so as not to upset the internal dc bias. When normal composite video is applied, the desired input is selected by Bit $88 7. Bits $77 6 and $77 7 must be set to so that their switches are as shown in Figure 35. The selected signal passes through the sound trap, and is then separated by the chroma trap and the chroma (high pass) filter. When S VHS signals (Y,C) are applied to the two inputs, Bit $88 7 is used to direct the luma information to the sound trap, and the chroma information to the ACC circuit (Bit $77 6 must be set to a Logic ). Bit $77 7 is normally set to a Logic in this mode to bypass the first luma delay line and the chroma trap, but it can be left if the additional delay is desired. Sound Trap The sound trap will filter out any residual sound subcarrier at the frequency selected by control bits T and T2 according to Table 3. The accuracy of the notch frequency is directly related to the selected crystal frequency. Crystal Frequency 7.7373 MHZ 4.32 MHz Table 3. Sound Trap Frequency T ($7B 7) T ($7B 6) Notch Frequency 6.5 MHz 5.5 + 5.75 MHz 6. MHz 5.5 MHz 5.25 MHz 4.44 + 4.64 MHz 4.84 MHz 4.44 MHz Code (for T, T2) is used to widen the band rejection where stereo is in use. Typical rejection is 3 db. ACC and PAL/NTSC Decoder The chroma filter bandpass characteristics (3.58 or 4.43 MHz) is determined by the selected crystal. The output of the chroma filter is sent to the ACC circuit which detects the burst signal, and provides automatic gain control once the crystal oscillator has achieved phase lock up to the burst. The dc voltage at Pin 2 is.5 to 2. V. This will occur if the burst amplitude exceeds 3 mvpp, and if the correct crystal is selected (Bit $7A 7). A 7.734472 MHz crystal is required for PAL, and a 4.388 MHz crystal is required for NTSC. When Flag 23 is high, it indicates that the crystal s PLL has locked up, and the ACC circuit is active, providing automatic gain control. A small amount of phase adjustment ( ±5 ) of the crystal PLL, for color correction, can be made with control DAC $79 5/. Pin 2 is the filter for the ACC loop, and Pin 44 is the filter for the crystal oscillator PLL. MC44 The PAL/NTSC decoder then determines if the signal is PAL or NTSC by looking for the alternating phase characteristic of the PAL burst. When Flag 24 is high, PAL has been detected. Bits SSA, SSB, SSC, and SSD (Table 4) must then be sent to the decoder to set the appropriate decoding method. SSA ($7C 6) Table 4. Color System Select SSB ($7D 6) SSC ($7C 7) SSD ($7A 6) Color System Not Used PAL NTSC Color Kill X X External Upon receiving the SSA to SSD bits, the decoder provides the correct color difference signals, and with the Identification circuit, provides the correct level at the System Select output (Pin 34). This output is used by the MC444 delay line. The color kill setting (SSA = SSB = ) should be used when the ACC flag is, when the color system cannot be properly determined, or when it is desired to have a black and white output (the ACC circuit and flag will still function if the input signal has a burst signal). The External setting (SSC = ) is used when an external (alternate) source of color difference signals are applied to the MC444 delay line. (See Miscellaneous Applications Information for more details.) Color Difference Controls and Outputs The color difference signals (R Y, B Y) from the PAL/NTSC decoder are directed to the saturation, hue and color balance controls, and then through a series of notch filters before being output at Pins 4 and 42. Blanking and clamping are applied to these outputs. The saturation control DAC($87 5/) varies the amplitude of the two signals from Vpp (DAC setting = ), to a maximum of.8 Vpp (at a DAC setting of 63). The maximum amplitude (without clipping) is.5 Vpp, but a nominal setting is.3 Vpp at a DAC setting of 5. The hue control ($88 5/) varies the relative amplitude of the two signals to provide a hue adjustment. The nominal setting for this DAC is 32. The color balance control ($78 5/) provides a fine adjustment of the relative amplitude of the two outputs. This provides for a more accurate color setting, particularly when NTSC signals are decoded. The nominal setting for this DAC is 32, and should be adjusted before the hue control is adjusted. The notch filters provide filtering at the color burst frequency, and at 2x and 8x that frequency. Additionally, blanking and clamping (derived from the horizontal PLL) are applied to the signals at this stage. The nominal output dc level is 2. to 2.5 Vdc, and the load applied to these outputs should be > kω. Sync is not present on these outputs. 26

Luma Peaking, Delay Line, and Y Output When composite video is applied, the luma information extracted in the chroma trap is then applied to a stage which allows peaking at 3. MHz with the 7.7 MHz crystal ( 2.2 MHz with the 4.3 MHz crystal). The amount of peaking at Y is with respect to the gain at the minimum peaking value (P, P2, P3 = ), and is adjustable with Bits $7D 7, and $7E 7,6 according to Table 5. The luma delay lines allow for adjustment of that delay so as to correspond to the chroma delay through this section. Table 6 indicates the amount of delay using the D D3 bits ($7F 7,6, and $8 6). The delay indicated is the total delay from Pin or 3 to the Y output at Pin 33. The amount of delay depends on whether Composite Video is applied, or YC signals (S VHS) are applied. The output impedance at Y is 3 Ω, and the black level clamp is at. V. Sync is present on this output. Y is also internally routed to the color difference stage. MC44 P ($7D 7) Table 5. Luma Peaking P2 ($7E 6) P3 ($7E 7) Y Peaking 9.5 db 8.5 7.7 6.5 5.3 3.8 2.2 7.7 MHz Crystal, 6.5 MHz Sound Trap, Composite Video Mode Table 6. Luma Delay 4.3 MHz Crystal 7.7 MHz Crystal D ($7F 6) D2 ($8 6) D3 ($7F 7) Comp. Video ($77 7 = ) S VHS ($77 7 = ) Composite Video ($77 7 = ) S VHS ($77 7 = ) 69 ns 395 ns 594 ns 35 ns 76 465 65 46 83 535 77 463 9 65 763 59 97 675 89 575 4 745 876 632 97 675 89 575 4 745 876 632 Color Difference Stage and RGB/YUV Outputs A block diagram of this section is shown in Figure 36. This section s function is to take the color difference input signals (Pins 3, 3), or the RGB inputs (Pins 26 to 28), and output the information at Pins 2 to 22 as either RGB or YUV. The inputs (on the left side of Figure 36) are analog RGB, or color difference signals (R Y and B Y) with Y or Y2 as the luma component. Pin 25 (Fast Commutate) is a logic level input, used in conjunction with RGB EN (Bit $8 7), to select the RGB inputs or the color difference inputs. The outputs (Pins 2 to 22) are either RGB or YUV, selected with Bit $82 7. The bit numbers adjacent to the various switches and gates indicate the bits used to control those functions. Table 7 indicates the modes of operation. FC RGB EN $8 7 Table 7. Color Difference Input/Output Selection YX EN $82 6 YUV EN $82 7 Function RGB inputs, RGB outputs, no saturation control RGB inputs, RGB outputs, with saturation control RGB inputs, YUV outputs, with saturation control Not usable FC Low and/or RGB EN Hi X R Y, B Y inputs, RGB outputs. Y or Y2 must be selected FC Low and/or RGB EN Hi X R Y, B Y inputs, YUV outputs. Y or Y2 must be selected 27

In addition to Table 7, the following guidelines apply: a. To select the RGB inputs, both FC must be high and RGB EN must be low. Therefore, the RGB inputs can be selected either by the I2C bus by leaving FC permanently high, or by the FC input by leaving Bit $8 7 permanently low. For overlay functions, where high speed, well controlled switching is necessary, the FC pin must be the controlling input. b. When the R Y, B Y inputs are selected, either Y or Y2 must be selected, and the other must be deselected. The YX input is automatically disabled in this mode. MC44 c. In applications where the color difference inputs are obtained from the NTSC/PAL decoder (from a composite video signal), Y is used. The Y2 input is normally used where alternately sourced color difference signals are applied, either through the MC444 delay line, or through other external switching to Pins 3 and 3. In Figure 36, the bit numbers followed by /5 indicate DAC operated controls (contrast, brightness, etc.), which are controlled by the I2C bus. The DACs have 6 bit resolution, allowing 64 adjustment steps. Table 8 provides guidelines on the DAC operation. Table 8. DAC Operation Color Difference Section Function Bits RGB Outputs ($82 7 = ) YUV Outputs ($82 7 = ) Brightness $84 /5 Affects dc black and maximum levels of the three outputs, but not the clamp level, nor the amplitude. Affects dc black and white levels of the Y output only, but not the clamp level, nor the amplitude. DC Red DC Blue $85 /5 $83 /5 Fine tune the Red and Blue brightness levels. Allows a small amount of color tint control (not to be confused with hue). Contrast $8 /5 Provides gain adjustment (black to white) of the three outputs. Provides gain adjustment of the three outputs. Gain Red Gain Blue $82 /5 $8 /5 Fine tune the Red and Blue contrast levels. Fine tune of the U and V gain levels. V DC U DC $7E /5 $7D /5 Must be set to. Should nominally be set to 32. This sets the dc level of the U and V outputs at mid scale. Main Saturation $86 /5 Affects color saturation, except when the RGB inputs bypass this section (YX EN = ). Affects color saturation levels of the UV outputs. Does not affect the Y output. Figure 36. Color Difference Stage and Outputs R Inputs G B R Y B Y Y2 F/C 28 27 26 3 3 29 C C C C C C YX $8 7 $8 6 Y (From Decoder) 25 $8 7 YX Matrix Decoder B Y $82 6 R Y Main Saturation $86 /5 Y R Y B Y G Y R G B Contrast $8 /5 $82 7 $82 /5 Gain Brightness $84 /5 $82 7 DC ($85 /5) V DC ($7E /5) DC ($83 /5) Gain ($8 /5) U DC ($7D /5) NOTES:. C = Clamp Circuit 2. Switches controlled by I 2 C Interface See Text. 2 2 22 39 Ω R/V 39 Ω G/Y 39 Ω B/U Outputs 28

The RGB and Y2 inputs are designed to accept standard. Vpp analog video signals. They are not designed for TTL level signals. The color difference inputs are designed to accept signals ranging up to.8 Vpp. All signals are to be capacitor coupled as clamping is provided internally. Input impedance at these six pins is high. For applications involving externally supplied color difference signals, sync can be supplied on the luma input (Y2), or it can be supplied separately at the RGB inputs. Where the color difference signals are obtained from the NTSC/PAL decoder, sync is provided to this section on the internal Y signal. See Sync Separator section for more details on injecting sync into the MC44. Sync is present on all three outputs in the RGB mode, and on the Y output only (Pin 2) in the YUV mode. The Fast Commutate input (FC, Pin 25) is a logic level input with a threshold at.5 V. Input impedance is 67 kω, and the graph of Figure 24 shows the input current requirements. Propagation delay from the FC pin to the RGB/YUV outputs is 5 ns when enabling the RGB inputs, and 9 ns when disabling the inputs. (See Figure 29 Fast Commutate Timing diagram.) If Pin 25 is open, that is equivalent to a Logic, although good design practices dictate that inputs should never be left open. The voltage on this pin should not be allowed to go more than.5 V above VCC2 or below ground. The three outputs (Pins 2 to 22) are open collector, requiring an external pull up. A representative schematic is shown in Figure 37. The output amplitude can be varied from mvpp to 3. Vpp by use of the contrast and saturation controls. Any output load to ground should be kept larger than. kω. In the RGB mode, DACs $7D and $7E should be set to, which results in clamping levels of.4 Vdc. In the YUV mode, DACs $7D and $7E should be set to, which results MC44 Color or Color Diff Contrast Gain Brightness Figure 37. Output Stage DC 36 k 39 Output in clamping levels of.4 Vdc. In the YUV mode, the DACs should be set to 32 to bias the U and V outputs to 2.3 V. The Y output clamp will remain at.4 V in the YUV mode. Horizontal PLL (PLL) PLL (shown in Figure 38) provides several outputs which are phase locked to the incoming horizontal sync. In normal operation, the two switches at the left side of Figure 38 are as shown, and (usually) the transistor at Pin 2 is off. The phase detector compares the incoming sync (from the sync separator) to the frequency from the 64 block. The phase detector s output, filtered at Pin, controls the VCO to set the correct frequency (. MHz) so that the output of the 64 is equal to the incoming horizontal frequency. The line locked outputs are: ) Fh Ref (Pin 4) A square wave, TTL levels, at the horizontal frequency, and phase locked to the sync source according to the timing diagram of Figures 25 and 27. 2) Burst Gate (Pin 8) This is a positive going pulse, TTL levels, coincident with the burst signal. See the timing diagram of Figures 25 and 27. Figure 38. Horizontal PLL (PLL) 525/625 Calibration Loop ($84 6) Frequency Divider Frequency Comparator fh To PLL #2 4.43 MHz/ 3.58 MHz Up/Down Counter Horiz Sync from Sync Separator Flag 2 (Horizontal not locked) D to A Converter Frame Iref Coincidence Detector SC $78 6 $86 6 VCO. MHz 6Fh From Sync Separator $85 6 Divide By 64 Phase Det Gate $77 2 $84 7 3 8 35 4 2 6Fh/ Burst S/C Fh H Filter CSync Gate Out Ref H Filter Switch L Gain $83 6 29

3) Sandcastle Output (Pin 35) This is a multilevel output, at the horizontal frequency, used by the MC444 delay line. See the timing diagram of Figures 25 and 27. 4) 6Fh/CSync (Pin 3) This is a dual purpose output, TTL levels, user selectable. When Bit $85 6 is set to, Pin 3 is a square wave at 6x the horizontal frequency (25 khz for PAL, 252 khz for NTSC). When Bit $85 6 is set to, Pin 3 is negative composite sync, derived from the internal sync separator. See the timing diagram of Figures 25 and 27. The first three outputs mentioned above, and Pin 3 when set to 6Fh, are consistent, and do not change duty cycle or wave shape during the vertical sync interval. These four outputs will also be present regardless of the presence of a video signal at the selected input. When Pin 3 is set to CSync output, it follows the incoming composite sync format. If there is no video signal present at the selected input, this output will be a steady logic high. Loading on these pins should not be less than 2. kω to either ground or V. Pin is the filter for the PLL, and requires the components shown in Figure 38, and with the values shown in the application circuit of Figure 42. Pin 2 is a switch which allows the filtering characteristics at Pin to be changed. Switching in the additional components (set $84 7 = ) increases the filter time constant, permitting better performance in the presence of noisy signals. The gain of the phase detector may be set high or low, depending on the jitter content of the incoming horizontal frequency, by using Bit $83 6. Broadcast signals usually have a very stable horizontal frequency, in which case the low gain setting ($83 6 = ) should be used. When the video source is, for example, a VCR, the high gain setting may be preferable to minimize instability artifacts which may show up on the screen. The gating function ($77 2) provides additional control where the stability of the incoming horizontal frequency is in question. With this bit set to, gating is in effect, causing the phase detector to not respond to the incoming sync pulses during the vertical interval. This reduces disturbances in this PLL due to the half line pulses and their change in polarity. The gating may be disabled by setting this bit to where the timing of the incoming sync is known to be stable. The gating cannot be enabled if the phase detector gain is set high ($83 6 = ). Calibration Loop The calibration loop (upper left portion of Figure 38) maintains a near correct frequency of this PLL in the absence of incoming sync signals. This feature minimizes re adjustment and lock time when sync signals are re applied. The calibration loop is similar to the PLL function, receiving one frequency from the crystal (either 4.43 MHz or 3.58 MHz) divided down to a frequency similar to the standard horizontal frequency. Bit $84 6 is used to set the frequency divider to the correct ratio, depending on which crystal is selected (see Table 9). The output of the frequency comparator operates an up/down counter, which in turn sets MC44 the D to A converter to drive the VCO through switch Sc. The resulting frequency at the output of the divide by 64 block is then fed to the frequency comparator to complete the loop. When a sync signal is not present at Phase Detector #, and at the Coincidence Detector, as indicated by the coincidence detector s output (Flag 2), Bit $78 6 should be set to. This will cause the switch (Sc) to transfer to the D to A converter for two lines (lines 4, 5) in each vertical field, and will maintain the PLL at a frequency near the standard horizontal frequency (between 4 to 6 khz). When lock to an incoming sync is established, Bit $78 6 may be set to, disabling the periodic recalibration function, or it may be left set to. If a more accurate horizontal frequency is desired in the absence of an input signal, Bit $86 6. can be set to (and Bit $84 6 set according to Table 9). This holds the horizontal frequency to 5.7 khz. In this mode, Flag 2 will stay, as the PLL will not be able to lock up to a newly applied external signal. To reset the system, set $86 6 to, write $ to register $, and then check Flag 2 to determine when the loop locks to an incoming signal. Table 9. Calibration Loop Crystal Set Bit $84 6 to 4.3 MHz 7.7 MHz On initial power up, Bit $86 6 (PLL EN) is automatically set to, engaging the calibration loop continuously. This condition will remain until this bit is set to, and $ is written to register $, as part of the initialization routine. Pixel Clock PLL (PLL2) The second PLL, depicted in Figure 39, generates a high frequency clock which is phase locked to the horizontal frequency. f H from PLL Phase and Frequency Comparator Figure 39. Pixel Clock PLL (PLL2) Up Down 5 5 k Return L2 Gain $83 7 Charge Pump 5625 Hz or 575 Hz Voltage Monitor VCO Gain $7F 5/ VCO Flag 9 (VCO HI) Flag 2 (VCO LO) 2 6 8 PLL2 Filter Frequency Divider $85 7 Pixel Clock 3