MARTIN KOLLÁR nivesity of Technology in Košice Depatment of Theoy of Electical Engineeing and Measuement A TRANSDCER INTERFACE FOR RESISTIVE SENSOR ELEMENTS BASED ON THE SE OF A FLIP-FLOP This pape pesents a new tansduce inteface. This inteface seves the esistive bidges. The A/D convesion is based on the use of an auto-compensatoy system with two digital-to-analog convetes (DACs). A new measuement technique based on the use of a flip-flop cicuit is used to obtain high accuacy. The main advantages of the depicted achitectue ae: a) Calibation accuacy depends only on LSB and maximal diffeential non-lineaity (max(dnl )) of the fist digital-to-analog convete (DAC). b) Resultant accuacy of measuement depends on calibation accuacy and on accuacy of the second DAC. c) Calculation of a coection fomula (o look up table) and input amplifie ae not equied. The expeimental measuement cicuit with flip-flop was constucted and simulated to veify opeation of the measuement. Keywods: Wheatstone bidge, tansduce inteface, self-calibation, flip-flop cicuit, measuement. INTRODCTION Thee is, natually, no such thing as an ideal cicuit and if thee wee, we would quickly find out that its envionment would be fa fom being ideal. As a esult, cicuits may exhibit a vaiety of non-ideal popeties, such as noise, offset, dift, non-linea behaviou, and many othes. At the same time they ae affected by thei ambience: many cicuits show cosssensitivities to othe effects than they ae supposed to sense, and thei bias netwoks and/o leads may pick up noise and intefeence. In ode to be able to classify the cicuit non-idealities, we have to distinguish between time-vaiant and time-invaiant causes fo deviations fom the ideal behaviou, and between deteministic and statistical deviations []. Thee ae diffeent coection stategies fo each of these fou combinations. In odinay measuement systems, the inaccuacies caused by the offset and eo of the gain can be eliminated by using the thee-signal technique [, 3]. To eliminate the eos caused by the non-linea behaviou, seveal efeence signals must be applied to the measuement cicuit [3]. Nowadays, specific testing methods of the ADC ae based on the use of sinusoidal and tiangula efeence signals [4]. Coect elimination of all eos by using these methods depends mainly on the pecision of these efeence signals. In addition, the calculation of the coection fomula o the look up table is still necessay. In high pecision systems, DACs can be used to geneate efeence signals [3, 4]. Howeve, efeence signal geneato and measuement system ae usually in the same envionment. Theefoe, the accuacy of the efeence signal geneato should be at least two odes highe than desied accuacy [4]. In the poposed design, the DAC used in standad solutions fo calibation, has been moved to the feedback and senso signal fom Wheatstone bidge has been pocessed by a flip-flop. It is so-called auto-compensatoy system with a flip-flop [5]. The main advantage is in the use of the flip-flop. The following section shows that all low fequency distubances, which ae pesent within many locations of the flip-flop and Wheatstone bidge and all
mismatches in the elements of the flip-flop ae eflected only in an offset of the flip-flop when the flip-flop is contolled with slow ising slope impulses.. FLIP-FLOP CIRCIT The cicuit in Fig. as the senso based on a flip-flop cicuit has been intoduced in efeence [6]. The standad flip-flop consisting of two tansistos and two esistos (Fig. ) is chaacteized by two stable states, one and zeo. i R K i R N R i i R β β (t) C i i C u u T T Z Fig.. Flip-flop cicuit. W. Lian and S. Middelhoek [6] poved that a flip-flop can be used fo measuement of non-electical quantities in such a way that one element of the flip-flop is eplaced by a senso. Then the pinciple of measuement is based on the fact that the measued nonelectical quantity beaks the value symmety of the invetes of the flip-flop in elation to the mophological symmety axis passing though points K and Z (Fig. ). Howeve, measued quantity can be compensated fo by the voltage N = NE in such a way that the 5% state is estoed by epeated connection to souce. It means that the numbe of ones will be 5 % of the numbe of connections to voltage souce [6]. The magnitude of the measued nonelectical quantity will be eflected in the voltage NE, which we will call the equivalent voltage [6, 7]. Sensing elements, which geneate the voltage, can be placed within many locations of the flipflop cicuit. Wheatstone bidge can be added to the flip-flop. The flip-flop cicuit with Wheatstone bidge is shown in Fig. a and its equivalent cicuit is shown in Fig. b. Thee = s [R D /(R A +R D )-R C /(R B +R C )] and R 3 = R A R D +R B R C. s R A R D R B R C i R K i R N R 3 i R K i R N R i i R β β (t) R i i R β β (t) C i i C u u C i i C u u T T T T Z Z Fig.. Flip-flop cicuit a) with Wheatstone bidge, b) its equivalent cicuit.
It should be noted that in voltage contol we also distinguish between fast and slow-ising slope impulses [8, 9] (Fig. 3). The equivalent voltage can be affected by the mismatches in the capacitances of the flip-flop (Fig. ). This can be used fo measuement of the capacitances [5]. (t) m δ T/ δ t Fig. 3. Voltage contol pulse. The contol by slow-ising slope impulses is chaacteized by such a atio m /δ that the cuents passing though the capacitos ae negligible in compaison to the tansisto cuents of the flip-flop. This condition is met if it is tue that δ, δ >R C is at the same time δ, δ. >R C [8, 9]. In the following text only contol impulses with slowly ising slopes ae analyzed... State desciption The flip-flop senso, accoding to Fig. b, is descibed by the system of diffeential equations [8] du dt du dt ( () φ ) R t u R = Q, () R R C ( ( ) N φ ) R t u R = Q, () R R C whee R =R +R 3 and φ,φ ae defined as and φ I I = I +, φ = I + (3) β β ES u u VT V I i T ES e I = i e, =, (4) whee β, β ae the cuent amplification coefficients, i ES, i ES ae the satuation cuents of bipola tansistos and V T is a themal voltage... Equivalent Voltage When, fo example, one of two esistances is slightly lage than the othe, the flip-flop is foced to go to a cetain stable state. To qualify this effect, a DC voltage was intoduced into the flip-flop senso (as shown in Fig. ). Thee exists a cetain value of this voltage called the equivalent voltage at which the effect of the asymmety in the esistos is fully compensated fo by the addition of this voltage. A deivation of the magnitude of the equivalent voltage is shown in this section.
The chaacteistics of the flip-flop ae shown in Fig. 4a. The tansfe chaacteistic of the fist du invete u (u ) is obtained fom equation () with zeo left side =. The tansfe dt chaacteistic of the second invete u (u ) is obtained fom equation () with zeo left side du =. Stable and unstable states ae epesented by the intesection points of these dt du du chaacteistics. They ae also called singulaities in the state plane as =, =. One dt dt stable state is obseved in Fig. 4a, if value of slowly ising impulse (Fig. 4b) is lowe than cetain value α. Two stable states, and unstable state S ae obseved if value of slowly ising impulse (Fig. 4b) is highe than cetain value α. But so-called neithe stable and neithe unstable tiple point S P [8] is obseved if value of slowly ising impulse (Fig. 4b) is equal to α and flip-flop is balanced by equivalent voltage NE. Region of the stable state zeo u S T j Q = S P S (t)>α Q = Region of the stable state one (t) V S (t)=α (t)<α T/4 t S u Fig. 4 a) Singulaities in the state plane, b) coesponding voltage contol impulse. Pactically, the unstable state neve can be achieved by the flip-flop. But taking into account a theoetical model of flip-flop, the unstable state may be assumed. Then a tansition of the flip-flop into unstable state S is epesented by a tajectoy T j (Fig. 4a). A bounday between the egion of the stable state one and zeo is also epesented by this tajectoy T j. Tajectoy T j is line with a unit slope [8], which leads to du = du. (5) By taking the integals of equation (5) it follows that u = u+ C, (6) whee C is an integating constant. As it can be seen in Fig. 3 the voltage (t) is equal to zeo duing the time inteval (T/, T) of a contol impulse. At this inteval the capacito C is chaged though the impulse geneato and esisto R on potential - NE and capacito C is chaged though the impulse geneato and esisto R on potential -. Howeve, the voltage can change depending on the time, theefoe it must hold fo the fequency of a senso signal f <. Then with the stat of the following contol impulse it can be assumed that RC u (T) = -, u (T) = - NE and fom (6) we have
u = u NE +. (7) Fom the second Kichhoffs law, of the cicuit in Fig. a, it follows that R I du ' I + + C u NE R I C + u dt + + = + + + β β dt I du, (8) whee cuents I, I ae defined by the equation (4). Taking into account that the capacito cuents ae negligible when compaed to the tansisto cuents, by means of (7) it can be deived I I R I+ = R I +. (9) β β It is mentioned above, the existence of the tiple point S P is joined only with the compensation of the asymmety of the flip-flop by equivalent voltage NE. Then the tiple point is neithe stable and unstable [8]. This view of the poblem makes it possible to put the Jacobi matix fo given system (), () elative to the teatment of the stability o instability of the given point. In case of value asymmety let us assume S P = [, ] so that. In ode to deive Jacobi matix fom the system eq. (), (), the deivatives to voltage u and u must be taken into the tiple point. Jacobi matix is given as follows J RC = RI I + ( () t () t ) ( () t () t ) VT β CV T RC u RC u +, () I ( ) ( ) RI T T + CV RC V RC u RC u T T β VT VT whee I = iese, I = ies e. Since the tiple point is neithe stable and unstable, the eigenvalues λ must be equal to. Then fom det J λ E = () ( ) fo λ equal to fom (7) and (9) it can be obtained = + V NE T R ln R R β ies R i ES β. () Dependence of the equivalent voltage on the output voltage fom Wheatstone bidge and on the mismatches in satuation cuents, load esistances and in cuent gains of the flip-flop can be obseved fom the equation (). Note that some influences can be eflected in voltages o cuents and can be found within many locations of the flip-flop cicuit and the Wheatstone bidge.
IN R A R B IN s R D I IN R C Fig. 5. Wheatstone bidge with distubances. The Wheatstone bidge is shown in Fig. 5. Some influences ae eflected in voltage souces IN, IN and in cuent souce I IN. But the Wheatstone bidge is a linea cicuit, which can be solved by using Thevenins theoem. Then still a sum of contibutions of voltage and cuent souces within the solved cicuit is the esult. Theefoe R = + R R I ( ) C D C IN IN IN ( RB + RC), (3) whee is the non-affected voltage of the Wheatstone bidge. Conclusion is that distubing voltage and cuent souces within the Wheatstone bidge ae eflected only in an offset. By using the above pocedue can be shown that R R β i = t + V + t ES () ln () NE T d R i ES R β, (4) whee d (t) epesents low-fequency distubances such as a flicke noise. The esultant equation of equivalent voltage contains voltage (t) of Wheatstone bidge and so-called eo equivalent voltage. In case that the Wheatstone bidge has a distubance, by means of (3) it can be assumed R R β ies RC NE = () + ln T + () ( ) d + D C IN IN IN R i ES ( RB + RC ) R β t V t R R I R R whee () ( ) ln β ies RC T + d + D C IN IN IN R i ES ( RB + RC ) R β V t R R I, (5) is a new eo equivalent voltage. It follows fom eq. (5) that distubing voltage and cuent souces within the Wheatstone bidge also all changes in the paametes of the flip-flop ae eflected only in an offset eo voltage. The equivalent does not depend on the amplitude of voltage contol impulse is main advantage of using the flip-flop in compaison to an amplifie which is used in odinay appoach.
.3. Feedback technique It is beneficial to use a feedback technique in ode to set the value of the equivalent voltage automatically. It woks as follows: The output in the numbe of ones is used to geneate a signal (the feedback signal). This signal is then added to the input of the flip-flop to bing the flip-flop back to the 5% position. The size of this feedback signal is a diect measue of the paamete [7]. An auto-compensatoy system with the flip-flop is descibed in the following section. 3. PROPOSED SOLTION Auto-compensatoy system, shown in Fig. 6, contains the following main pats: - A flip-flop cicuit to convet all causes, which can affect the value symmety of the flipflop, into a seies of ones and zeos. - The Wheatstone bidge as a sensing device of the flip-flop to convet a non-electical quantity to be measued into a senso signal. - A evesible counte and a DAC to compensate fo the time-invaiant deteministic eos and the time vaiant eos. - A evesible counte and a DAC to measue a senso signal of the Wheatstone bidge. - A multiplexe to contol the switching opeations of the system. s i R NE i R R K Wheatstone bidge R i i R β β C i u i C u T T R Φ (t) MX Φ t evesible counte evesible counte N N Φ DAC DAC digital output Fig. 6. Auto-compensatoy system. The idea is simple: Duing the fist phase of a measuing cycle to compensate fo the timeinvaiant deteministic eos and the time vaiant low fequency eos (supply voltage of the Wheatstone bidge is switched off), and duing the second phase to measue senso signal (supply voltage of the Wheatstone bidge is switched on). The peiod of the switching on and off the Wheatstone bidge is T (Fig. 3). To measue diectly the senso signal duing the second phase, an adding cicuit is installed to the system as it can be seen in Fig. 6. The pinciple of functionality, of the cicuit in Fig. 6, is shown in Fig. 7. In the following text the tem distubances and mismatches is used fo the time-invaiant deteministic eos and the time vaiant low fequency eos.
Φ t N T Eo signal LSB Senso signal t N t Fig. 7. The pinciple of system functionality. Inaccuacy of the compensation of distubances and mismatches is equal to RK ±.5 ( LSB + max( DNL )), whee max(dnl ( R + RK ) ) is maximal diffeential non-lineaity [4] of DAC, and does not depend on an integal non-lineaity [4] of DAC. The absolute maximal eo of measuement is given by ν = R.5 LSB + max DNL + max INL +.5LSB ( ( )) ( ) K max ( R + RK ), (6) whee max(inl ) is the maximal integal non-lineaity of DAC. But notice that an eo of esisto-divide R K, R (Fig. 6) is not consideed in (6). The value R K usually anges fom a few Ω to tens of Ω and is at least two odes of magnitude smalle than R. The esisto atio is R K /R (R K << R ) and cannot be influenced by elements of the flip-flop. The value of R K is nomally fou odes of magnitude smalle than R. In addition, in the tiple point (see Section Equivalent voltage) the equivalent esistances of the tansistos of the flip-flop ae a few MΩ [8]. The esisto atio eo can be deived =. (7) RK RK R R R R R R To compensate fo the influence of the tempeatue T h, because a themal coefficient R α = of a esisto R, it is sufficient to use the esistos with identical themal R Th coefficients. Pactically, the initial esisto atio eo is about of.% and esistance-atio tempeatue coefficient anges fom to ppm/ o C []. The esultant absolute eo is given ν R R = +.5( LSB + max ( DNL )) + max ( INL ) +.5LSB K K max R ( R + RK ) (8) Thus, the only dependence of measuement eo on LSB and DNL of DAC, LSB and INL of DAC and on esisto atio eo can be obseved in (8). Since the given paametes of DAC and DAC can be changed by some influences, the eo of measuement can be also
changed. Howeve, the calibation accuacy is changed in such a way also in odinay systems. The othe souce of eo that must be taken into account is eo of an adding cicuit (Fig. 6). But this cicuit is consideed in the stuctue fo bette undestanding of the system functionality. Pactically, the signal of DAC is incopoated to the fist invete of flip-flop. This modification is shown in Fig. 8. i R ir N R R K NE R K R N s Wheatstone bidge R R (t) Fig. 8. Modification of auto-compensatoy system. 3.. Simulated esults The auto-compensatoy system with the flip-flop was simulated in PSPICE. At the beginning, the mismatches in the load esistos of the flip-flop wee assumed. The values of esistos R, R wee changing fom 7. to. kω. The emaining paametes wee set as follows: R k = Ω, R =.8 kω, =. mv, LSB = mv, V T = 6 mv, β = β =, i ES = i ES = -6 A. The flip-flop senso was contolled by a voltage pulse accoding to Fig. 3, while δ, δ = 6µs, m = V and T = 4µs. The simulated esult is shown in Fig. 9a. Coesponding eo suface is shown in Fig. 9b and maximal absolute eo is equal to 5.5 µv. Fig. 9. a) Simulated esult, b) coesponding eo suface. Then a distubance u DIS epesented by a signal u DIS = 35. -6 sin(34t) was found in the flip-flop. A simulated esult is shown in Fig. and maximal absolute eo is equal to 5 µv.
Fig.. Output voltage of DAC and a distubing signal u DIS. 3.. Expeimental esults The complete cicuit was ealized by using the suface montage technology. The compaatos wee installed between the flip-flop outputs and the evesible countes. The Wheatsone bidge as light intensity sensing element was used. The conventional esisto was substituted by photoesisto. Digital data fom the evesible counte wee pocessed in PC by using LabVIEW. To veify the independence of measuement eo on mismatches in the elements of the flip-flop, one of the load esistances was set to 7. kω and othe esistance was subsequently given seveal diffeent (fom 7. to. kω). Simultaneously, the mismatch in satuation cuents was simply ealized by using two tansistos connected in paallel on one side of the flip-flop, while on the othe side, thee was only one tansisto. The emaining paametes wee as follows: R k = Ω, R =.8 kω, LSB = mv. The flip-flop senso was contolled by a voltage pulse accoding to Fig. 3, while δ, δ = 6µs, m = V and T = 4µs. The output voltage of the Wheatstone bidge was measued by a pecise voltmete to define measuement eo of the auto-compensatoy system. In elation to equation (8), the negligible integal and diffeential non-lineaity leads to eo one LSB. In case of this expeiment it should be eo 5.5 µv. But the maximal expeimental eo was equal to 3 µv. The eason was being looked fo in the influence of a themal and shot noise because highfequency eos cannot be compensated fo by using the auto-compensatoy system (see Section Equivalent voltage). The effect of noise put on an output voltage of the DAC is shown in Fig.. Since influence of noise can be makedly eliminated by a ditheing, this technique was used. The eade will find moe detailed infomation about implementation of this method in []. The esultant eo was compensated fom 3 to 7 µv. Remaining deviation (.5 µv) was caused by DAC and DAC. Taking into account this deviation, effective numbe of bits (ENOB) [4] is equal to, because bits DAC was used. In the following expeiment a distubing voltage IN was employed in the Wheatstone bidge (Fig. 5). The esult eo was again equal to 7 µv by using the ditheing.
Fig.. Output signal of DAC. The aim of these expeiments was to show that the eo of measuement by using the autocompensatoy system with the flip-flop depends only on DAC,. And fom this point of view a vey good ageement between expeimental and simulated, theoetical esults could be declaed. In the following pat, dynamical popeties of the auto-compensatoy system will be descibed. Fom a global view, the evesible countes used in the auto-compensatoy system ae digital integatos. Howeve, senso signal of the Wheatstone bidge can be time-vaiant. To avoid a dynamic eo it must hold () d t LSB <, (9) dt T max whee T is peiod of the contol impulses (Fig. 3). Assuming ( t) sin ( π f t) follows that f = it m LSB <, () 4πT whee f is a fequency of the senso signal. Example: fo m =.mv, LSB = mv, T = 4µs, accoding to (), f will be equal to khz. m 4. COMPARISON WITH THE STANDARD SOLTIONS The output of the Wheatstone bidge is a small diffeential voltage supeimposed on a lage common mode voltage. To povide a usable signal, an instumentation amplifie can be used in the standad solution. The standad topology contains thee opeational amplifies and seven esistos []. To make a compaison with the poposed solution, some basic chaacteistics of instumentation amplifie ae descibed in the following text. The common mode ejection depends on esisto matching and oveall gain. The common mode ejection atio (CMRR) of the instumentation amplifie is appoximately equal to half esisto mismatch plus the gain. Fo example, a % esisto mismatch the CMRR is limited to 46 db plus the gain efeed to the input. The CMRR of standad instumentation amplifies anges fom 65 to db. The gain stability and gain lineaity also depend on the esisto matching. The gain lineaity is about of.% but eo of gain can be anged fom. to %. Last chaacteistic that must be taken into account is an offset. Its value is at intevals fom
tenths to ones of mv []. These eos ae not tivial in high pecision system. In addition, they can be makedly changed depending on some influences. Besides, the senso signal can be affected by a time vaiant distubance. A standad measuing system containing the instumentation amplifie, ADC and calibation cicuits is shown in Fig.. DAC Souce of efeence signal ef off Compensation of offset ADC Digital output Micopocesso Regulation of gain Fig.. Instumentation amplifie with ADC. Thee-signal technique can be used to compensate offset and eo of gain. The output voltage is given = ( A+ A ) + INL A+ A +.5LSB, () (( ) ) OT A/ D A/ D whee INL A/D is an integal non-lineaity of ADC and A is an eo of gain. Duing the offset compensation, the inputs ae shot-cicuited, theefoe Then the offset compensation leads to (( ) ) = ( A+ A ) + INL A+ A +.5LSB. () OToff off A/ D off A/ D ' OT INL = " ( A + A) + INLA/ D ( OT ) ( A + ) ( A + A) ) INL ( ) + A/ D off A off (.5LSB ), D / A OToff D / A (3) " whee INL D/A is an integal non-lineaity of DAC and OT = (A+ A) (A+ A) off INL A/D ((A+ A) off ) (INL D/A ( OToff )+.5LSB D/A ). The efeence signal is used to compensate fo eo of gain, theefoe whee ( ) OTef ef = A+ A and " OTef = OTef OToff + INLA / D ( OTef ) ( INL ( ) +.5LSB ) +.5LSB, D / A OToff ( ( ) ) D / A A / D = INL +.5LSB +.5LSB. The eo of gain, in OTef OTef OToff D / A OToff D / A A/ D this case, can be calculated fom equation ( ) = A+ A. Fom (4) it follows that OTef ( ) ( ) ef ( ) + INL / /.5 /.5 OTef A D OTef OToff INLD A OToff + LSBD A + LSBA/ D A = A. (5) ef (4)
The esultant output voltage with compensation of offset and eo of gain is given A A A INL OTef OT = ( + ) A/ D ( OTef ) + ef ef + INLA/ D (( A + A) off ) + ( INLD / A ( OToff ) +.5LSBD / A ) + ef ef + + + ef IV ( A A) off INLA/ D ( OT ), (6) whee A A A INL IV OTef OT = ( + ) A/ D ( OTef ) + ef ef + INLA/ D( ( A + A) off) + ef + ( INLD / A ( OToff ) +.5LSBD / A ) ( A + A) off. ef ef OTef Because ( A+ A) A = A, fo input signal = + off (Fig. ), the ef esultant eo is defined + off + off ν = INLA/ D( OTef) + INLA/ D( ( A + A) off) + ef ef + off + ( INLD / A ( OToff ) +.5LSBD / A ) + ef + + + + ef off IV ( A A) off Aoff INLA/ D ( OT ), (7) whee is senso signal. The dependence of the esultant eo of the standad system on integal non-lineaity of DAC and ADC, ef and on off, accoding to Fig., can be obseved fom equation (7). On the othe hand, the esultant eo of the measuement by using auto-compensatoy system with the flip-flop, accoding to Fig. 6, depends only on integal and diffeential non-lineaity of DACs. In ode to show the popeties of the poposed and standad solution in a moe detailed way let us assume the following example: A =, A = 5. DAC, also ADC, accoding to Fig., ae bits. Thei integal and diffeential non-lineaity chaacteistics ae shown in Fig. 3 and 4. These chaacteistics can be obtained by using standad testing methods [4, ].
.5..5..5 -.5 -. -.5 -. off ef -.5-5 - -5 - -5 5 5 5 Fig. 3. Integal non-lineaity as a function of output codes....8.6 DNL [LSB].4. -. -.4 -.6-5 - -5 - -5 5 5 5 output codes Fig. 4. Diffeential non-lineaity as a function of output codes. Let the values of (A+ A) off and OToff coespond with output code equal to and OTef, OTef coespond with output code equal to 5 (Fig. 3). The esultant eo, accoding to equation (7), is shown in Fig. 5. This eo anges fom - 4 to.7 LSB. 3 eo [LSB] - - -3-4 -5-5 - -5 - -5 5 5 5 output codes Fig. 5. Resultant eo of the standad system. Howeve, on the othe hand, the esultant eo of auto-compensatoy system depends only on integal and diffeential non-lineaity of DACs (Fig. 6). The esultant eo of the poposed
system, accoding to equation (8), is shown in Fig. 6 (max(dnl) =. LSB; Fig. 6). This eo anges fom -.4 to.3 LSB and does not depend on offset and efeence signal. The esisto atio eo was supposed to be equal with.3 %..5.5 eo [LSB] -.5 - -.5-5 - -5 - -5 5 5 5 outpu codes Fig. 6. Resultant eo of the poposed system. 5. CONCLSION A tansduce inteface fo esistive sensos has been pesented. A new concept fo accuate measuement has been implemented in a single cicuit. In compaison to odinay systems the type of a calibation using a pecise DAC is not equied. Instead two DACs ae used in the feedback to compensate inaccuacies and to measue a senso signal fom the Wheatstone bidge. The main acquisition is in the use of a modified flip-flop. All distubances and mismatches in the elements of the flip-flop and some distubances of the Wheatstone bidge ae compensated and accuacy depends only on the pecision of DACs. The expeimental cicuit was made by suface montage technology and its immunity was being tested on exteme mismatches in elements of the flip-flop and on distubances. ENOB of tansduce inteface is bits by using bits DAC is main test esult. ACKNOWLEDGEMENTS This wok has been suppoted by the Gant Agency of the Slovak Republic VEGA gant. No. /8/5. REFERENCES. Hosticka B.J., Bockhede W., Hammeschmidt D.: Silicon sensos systems. Smat senso intefaces-kluwe Academic Publishe, Novembe 997, pp. 99-.. Kiianaki N. V., Yuish S. Y., Shpak N. O., Deynega V. P.: Data Acquisition and Signal Pocessing fo Smat Sensos. John Willey & Sons, Mach, p. 3. 3. Randy F.: ndestanding Smat Sensos. Atech House, Apil, p. 389. 4. IEEE Std. 57-994. IEEE Standad fo digitizing wavefom ecodes. The institute of electical and electonics enginees, Inc. New Yok, SA, 994, p. 8. 5. Kollá M.: Measuement of capacitances based on a flip-flop senso. Sensos&Tansduces e-digest (S&T), Vol. 35, No. 8-9, 3, Toonto, Ontaio Canada, www.sensospotal.com, p. 7.
6. Lian W., Middelhoek S.: A new class of integated sensos with digital output based upon the use of a flipflop. IEEE Electon Device Lettes, Vol. EDL-7, 986, pp. 38-4. 7. Middelhoek S., Audet S.A.: Silicon Sensos: full of pomises and pitfalls. J.Phys. E: Sci. Instum., Vol., 987, pp. 8-86. 8. Kollá, M.: Flip-flop senso contolled by slow-ise contol pulse. Radioengineeing, Vol., No. 3,, pp. 34-38, ISSN -5. 9. Špány V., Pivka L.: Dynamic popeties of flip-flop sensos, Jounal of Electical Engineeing, Vol. 47, No. 7-8, p.69-78.. Aeny P.R., Webste J.G.: Analog signal pocessing, John Wiley and sons, 999, p. 6.. Kollá M.: ncetainty in the system fo measuement of the capacitances by using flip-flop senso. www.electonicslettes.com, Vol. 4, 3, p. 6.. Apia P., Daponte P., Michaeli L.: Analytical a pioi appoach to phase-plane modeling of SAR A/D convetes. IEEE Tansaction on Instumentation and Measuement, Vol. 47, No. 4, 998, pp. 849-857. INTERFEJS PRZETWORNIKA DLA OPORNOŚCIOWYCH ELEMENTÓW CZJNIKOWYCH OPARTY NA ZASTOSOWANI PRZERZTNIKA BISTABILNEGO. Steszczenie Niniejszy atykuł pzedstawia nowy intefejs pzetwonika. Ten intefejs jest używany z mostkami oponościowymi. Pzetwazanie analogowo-cyfowe opiea się na użyciu systemu samokompensacyjnego z dwoma pzetwonikami cyfowo-analogowymi (D/A). Dla uzyskania dużej dokładności zastosowano nowy sposób pomiau opaty na użyciu pzezutnika bistabilnego. Głównymi zaletami opisanej achitektuy są: a) Dokładność kalibacji zależy jedynie od LSB i maksymalnej nieliniowości óżnicowej max(dnl) piewszego pzetwonika cyfowo-analogowego, b) Wypadkowa dokładność pomiau zależy od dokładności kalibacji oaz od dokładności dugiego pzetwonika analogowo-cyfowego, c) Obliczenie wzou koekcyjnego (lub tablicy pzeglądowej) i wzmacniacz wejściowy nie są wymagane. Doświadczalny układ pomiaowy z pzezutnikiem bistabilnym został wykonany i symulowany w celu weyfikacji pomiau.