Improved Industry Standard Serial -Bit Multiplying DACs FEATRES Improved Direct Replacement for AD754 and DAC-84 Low Cost DNL and INL Over Temperature: ±0.5LSB Easy, Fast and Flexible Serial Interface Daisy-Chain -Wire Interface for Multiple DAC Systems (LTC84) LSB Maximum Gain Error Over Temperature Eliminates Adjustment Asynchronous Clear Input for Initialization Four-Quadrant Multiplication Low Power Consumption 6-Pin PDIP and SO Packages APPLICATIONS Process Control and Industrial Automation Remote Microprocessor-Controlled Systems Digitally Controlled Filters and Power Supplies Programmable Gain Amplifiers Automatic Test Equipment DESCRIPTION The LTC 754/LTC84 are serial-input -bit multiplying digital-to-analog converters (DACs). They are superior pin compatible replacements for the AD754 and DAC-84. Improvements include better accuracy, better stability over temperature and supply variations, lower sensitivity to output amplifier offset, tighter timing specifications and lower output capacitance. An easy-to-use serial interface includes an asynchronous CLEAR input for systems requiring initialization to a known state. The LTC84 has a serial data output to allow daisychaining multiple DACs on a -wire interface bus. These DACs are extremely versatile. They can be used for -quadrant and 4-quadrant multiplying, programmable gain and single supply applications, such as noninverting voltage output and biased or offset ground mode. Parts are available in 6-pin PDIP and SO packages and are specified over the extended industrial temperature range, 40 C to 85 C., LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION V IN Multiplying DAC Has Easy -Wire Serial Interface 5V Integral Nonlinearity Over Temperature.0 CLOCK DATA LOAD 4 7 5 4 5 6 V DD R FB STB OT SRI LTC754 LTC84 LD OT DGND AGND pf + LT 097 V OT 754/84 TA0 INTEGRAL NONLINEARITY (LSB) 0.5 0 0.5 T A = 85 C T A = 5 C T A = 40 C.0 0 5 04 56 048 560 07 584 4095 DIGITAL INPT CODE 754/84 TA0
ABSOLTE MAXIMM RATINGS W W W V DD to AGND... 0.5V to 7V V DD to DGND... 0.5V to 7V AGND to DGND... V DD + 0.5V DGND to AGND... V DD + 0.5V Digital Inputs to DGND... 0.5V to (V DD + 0.5V) V OT, V OT to AGND... 0.5V to (V DD + 0.5V) to AGND, DGND... ±5V V RFB to AGND, DGND... ±5V Maximum Junction Temperature... 50 C Operating Temperature Range... 40 C to 85 C Storage Temperature Range... 65 C to 50 C Lead Temperature (Soldering, 0 sec)... 00 C PACKAGE/ORDER INFORMATION OT OT AGND STB 4 LD 5 NC (LTC754) 6 SRO (LTC84) SRI 7 STB 8 TOP VIEW 6 R FB 5 4 V DD CLR DGND STB4 0 STB 9 LD N PACKAGE 6-LEAD PDIP SW PACKAGE 6-LEAD PLASTIC SO WIDE T JMAX = 50 C, θ JA = 00 C/ W (N) T JMAX = 50 C, θ JA = 0 C/ W (SW) W ORDER PART NMBER LTC754GKN LTC754KN LTC754GKSW LTC754KSW LTC84EN LTC84FN LTC84ESW LTC84FSW Consult factory for Military grade parts. ACCRACY CHARACTERISTICS LTC754 V DD = 5V, = 0V, V OT = V OT = AGND = DGND =0V, T A = T MIN to T MAX, unless otherwise specified. LTC754GK LTC754K SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Resolution Bits INL Integral Nonlinearity (Note ) ±0.5 ±0.5 LSB (Relative Accuracy) DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±0.5 ±0.5 LSB GE Gain Error (Note ) T A = 5 C ± ± LSB T MIN to T MAX ± ± LSB Gain Temperature Coefficient (Note ) 5 5 ppm/ C ( Gain/ Temp) I LKG Output Leakage Current (Note 4) T A = 5 C ± ± na T MIN to T MAX ±0 ±0 na Zero-Scale Error T A = 5 C ±0.006 ±0.006 LSB T MIN to T MAX ±0.06 ±0.06 LSB PSRR Power Supply Rejection Ratio V DD = 5V ±5% ±0.000 ±0.00 ±0.000 ±0.00 %/%
ACCRACY CHARACTERISTICS LTC84 V DD = 5V, = 0V, V OT = V OT = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. V DD = 5V, = 0V, V OT = V OT = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. LTC84E LTC84F SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX NITS Resolution Bits INL Integral Nonlinearity (Note ) ±0.5 ± LSB (Relative Accuracy) DNL Differential Nonlinearity Guaranteed Monotonic, T MIN to T MAX ±0.5 ± LSB GE Gain Error (Note ) T A = 5 C ± ± LSB T MIN to T MAX ± ± LSB Gain Temperature Coefficient (Note ) 5 5 ppm/ C ( Gain/ Temp) I LKG Output Leakage Current (Note 4) T A = 5 C ±5 ±5 na T MIN to T MAX ±5 ±5 na Zero-Scale Error T A = 5 C ±0.0 ±0.0 LSB T MIN to T MAX ±0.5 ±0.5 LSB PSRR Power Supply Rejection Ratio V DD = 5V ±5% ±0.000 ±0.00 ±0.000 ±0.00 %/% ELECTRICAL CHARACTERISTICS ALL GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Reference Input R REF Input Resistance (Note 5) 8 5 kω AC Performance (Note ) Output Current Settling Time (Notes 6, 7) 0.5 µs Multiplying Feedthrough Error = ±0V, 0kHz Sinewave 0.8 mv P-P Digital-to-Analog Glitch Energy (Notes 6, 8) 0 nv-sec THD Total Harmonic Distortion (Note 9) 08 9 db Output Noise Voltage Density (Note 0) nv/ Hz Analog Outputs (Note ) C OT Output Capacitance DAC Register Loaded to All s C OT 60 90 pf C OT 0 60 pf DAC Register Loaded to All 0s C OT 0 60 pf C OT 50 90 pf Digital Inputs V IH Digital Input High Voltage.4 V V IL Digital Input Low Voltage 0.8 V I IN Digital Input Current V IN = 0V to V DD 0.00 ± µa C IN Digital Input Capacitance (Note ), V IN = 0V 8 pf Digital Outputs: SRO (LTC84 Only) V OH Digital Output High I OH = 00µA 4 V V OL Digital Output Low I OL =.6mA 0.4 V
ELECTRICAL CHARACTERISTICS V DD = 5V, = 0V, V OT = V OT = AGND = DGND = 0V, T A = T MIN to T MAX, unless otherwise specified. ALL GRADES SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS Timing Characteristics (Note ) t DS Serial Input to Strobe Setup Time STB sed as the Strobe 50 5 ns t DS (t STB = 80ns) STB sed as the Strobe 0 5 ns t DS STB sed as the Strobe 0 0 ns t DS4 STB4 sed as the Strobe 0 0 ns t DH Serial Input to Strobe Hold Time STB sed as the Strobe 0 0 ns t DH (t STB = 80ns) STB sed as the Strobe 50 5 ns t DH STB sed as the Strobe 80 55 ns t DH4 STB4 sed as the Strobe 80 55 ns t SRI Serial Input Data Pulse Width 80 ns t STB, t STB, Strobe Pulse Width (Note ) 80 ns t STB, t STB4 t STB, t STB, Strobe Pulse Width (Note ) 80 ns t STB, t STB4 t LD, t LD Load Pulse Width 40 ns t ASB LSB Strobed into Input Register 0 ns to Load DAC Register Time t CLR Clear Pulse Width 80 ns SRO Timing Characteristics (LTC84 Only) t PD STB, STB, STB4 Strobe to SRO C L = 50pF 0 0 ns Propagation Delay t PD STB to SRO Propagation Delay C L = 50pF 50 80 ns Power Supply V DD Supply Voltage 4.75 5 5.5 V I DD Supply Current Digital Inputs = 0V or V DD 0. ma Digital Inputs = V IH or V IL ma The denotes specifications which apply over the full operating temperature range. Note : ±0.5LSB = ±0.0% of full scale. Note : sing internal feedback resistor. Note : Guaranteed by design, not subject to test. Note 4: I OT with DAC register loaded with all 0s or I OT with DAC register loaded with all s. Note 5: Typical temperature coefficient is 00ppm/ C. Note 6: OT load = 00Ω in parallel with pf. Note 7: To 0.0% for a full-scale change, measured from falling edge of LD or LD. Note 8: = 0V. DAC register contents changed from all 0s to all s or from all s to all 0s. Note 9: = 6V RMS at khz. DAC register loaded with all s. Note 0: Calculation from e n = 4KTRB where: K = Boltzmann constant (J/K ); R = resistance (Ω); T = resistor temperature ( K); B = bandwidth (Hz). Note : Minimum high time for STB, STB, STB4. Minimum low time for STB. Note. Minimum low time for STB, STB, STB4. Minimum high time for STB. 4
BLOCK DIAGRAM W 5 0k 0k 0k 6 R FB 0k V DD 4 OT OT DECODER AGND CLR LD 5 LD 9 CLR LOAD BIT (MSB) BIT BIT BIT 4 BIT DAC REGISTER (LSB) STB 4 STB 8 STB 0 CLK OT INPT -BIT SHIFT REGISTER IN 7 SRI STB4 6 SRO 754/84 BD LTC84 ONLY DGND W W TI I G DIAGRA STROBE INPT STB, STB, STB4 (INVERT FOR STB) t DS t DS t DS t DS4 t DH t DH t DH t DH4 t STB t STB t STB t STB4 t STB t STB t STB t STB4 t SRI SRI PREVIOS WORD BIT MSB BIT BIT BIT LSB t ASB LD, LD t PD t PD t LD t LD SRO (LTC84 ONLY) BIT (MSB) PREVIOS WORD BIT BIT BIT LSB BIT (MSB) CRRENT WORD 754/84 TD0 5
TRTH TABLES Table. Input Register CONTROL INPTS Input Register Operation STB STB STB STB4 (LTC84: SRO Operation) 0 0 Serial Data Bit on SRI Loaded into Input 0 0 Register, MSB First 0 0 0 (LTC84: Data Bit or SRI Appears on 0 0 SRO Pin After Clocked Bits) X X X No Input Register Operation X X X (LTC84: No SRO Operation) X X 0 X X X X Table. DAC Register CONTROL INPTS CLR LD LD DAC Register Operation 0 X X Reset DAC Register to All 0s (Asynchronous Operation; No Effect on Input Register) X No DAC Register Operation X 0 0 Load DAC Register with the Contents of Input Register TYPICAL APPLICATIONS nipolar Operation (-Quadrant Multiplication) 0V TO 0V 5V µp 0.µF TO NEXT DAC FOR DAISY-CHAINING (LTC84) 0 4 7 5 6 9 8 4 STB CLR V DD STB SRI LD SRO (LTC84) LD STB STB4 DGND 5 6 LTC754 LTC84 R FB AGND OT OT pf + LT097 V OT 0V TO 754/84 TA0 nipolar Binary Code Table DIGITAL INPT BINARY NMBER IN ANALOG OTPT DAC REGISTER V OT MSB LSB (4095/4096) 000 0000 0000 (048/4096) = / 0000 0000 000 (/4096) 0000 0000 0000 0V 6
TYPICAL APPLICATIONS Bipolar Operation (4-Quadrant Multiplication) 0V TO 0V 5V 0.µF 4 V DD 5 6 R FB pf R 0k R 0k (LOGIC INPTS OMITTED FOR CLARITY) LTC754 LTC84 OT OT + / LT R 0k + / LT V OT DGND AGND 754/84 TA04 Bipolar Offset Binary Code Table DIGITAL INPT BINARY NMBER IN ANALOG OTPT DAC REGISTER V OT MSB LSB (047/048) 000 0000 000 (/048) 000 0000 0000 0V 0 (/048) 0000 0000 0000 (048/048) = Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7
PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted. N Package 6-Lead Plastic DIP 0.00 0.5 (7.60 8.55) 0.0 ± 0.005 (.0 ± 0.7) 0.045 0.065 (.4.65) 6 5 4 0.770* (9.558) MAX 0 9 0.009 0.05 (0.9 0.8) 0.05 (0.8) MIN 0.55 ± 0.05* 0.065 (6.477 ± 0.8) (.65) TYP 0.5 +0.05 0.05 +0.65 8.55 0.8 ( ) 0.5 (.75) MIN 0.045 ± 0.05 (.4 ± 0.8) 0.00 ± 0.00 (.540 ± 0.54) *THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED 0.00 INCH (0.54mm). 0.08 ± 0.00 (0.457 ± 0.076) 4 5 6 7 8 N6 0694 S Package 6-Lead Plastic SOL 0.005 (0.7) RAD MIN 0.9 0.99 (7.9 7.595) (NOTE ) 0.00 0.09 45 (0.54 0.77) 0.09 0.04 (.6.64) 0.07 0.045 (0.940.4) 0.98 0.4 (0.09 0.490) (NOTE ) 6 5 4 0 9 0.009 0.0 (0.9 0.0) NOTE 0.06 0.050 (0.406.70) 0 8 TYP 0.050 (.70) TYP 0.04 0.09 (0.56 0.48) TYP NOTE:. PIN IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANFACTRING OPTIONS. THE PART MAY BE SPPLIED WITH OR WITHOT ANY OF THE OPTIONS.. THESE DIMENSIONS DO NOT INCLDE MOLD FLASH OR PROTRSIONS. MOLD FLASH OR PROTRSIONS SHALL NOT EXCEED 0.006 INCH (0.5mm). NOTE 0.004 0.0 (0.0 0.05) 4 5 6 7 8 0.94 0.49 (0.007 0.64) SOL6 09 RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC57 Complete Serial I/O V OT -Bit DAC 5V to 5V Single Supply in 8-Pin SO and PDIP LTC45/LTC45/LTC45 Complete Serial I/O V OT -Bit DACs V/5V Single Supply in 8-Pin SO and PDIP LTC754A Parallel I/O Mulitplying -Bit DAC -Bit Wide Input LTC804 Serial Mulitplying -Bit DAC 8-Pin SO and PDIP 8 Linear Technology Corporation 60 McCarthy Blvd., Milpitas, CA 9505-7487 (408) 4-900 FAX: (408) 44-0507 TELEX: 499-977 LT/GP 0695 0K PRINTED IN SA LINEAR TECHNOLOGY CORPORATION 995