LATCHES & FLIP-FLOP Chapter 7
INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely making them useful for storage devices. The main difference between between latches and flip flops is in the method used for changing their states.
LATCHES The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change S-R (Set-Reset) Latch Gated S-R Latch Gated D Latch
FLIP FLOPS The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input Edge-Triggered Flip-Flop (S-R, J-K, D) Asynchronous Inputs
S-R LATCH
S-R LATCH
NEGATIVE-OR EQUIVALENT OF THE NAND GATE S -R LATCH 1 1 1 SET state 0 When /R is LOW and /S is HIGH 1 0 Q is LOW and this Condition We call it RESET state 1
Example: Determine the waveform that will be observed on the Q output. Assume that Q is initially LOW
THE GATED S-R LATCH A gated latch requires an Enable input, EN (G is also used to designated an enable input). The S and R inputs control the state to which the latch will go when a HIGH level is applied to the EN input. The latch will not change until EN is HIGH. Initially RESET
TRUTH TABLE FOR GATED S-R LATCH S R EN Q Q 0 0 0 Q Q Hold 1 0 0 Q Q Hold 0 1 0 Q Q Hold 1 1 0 Q Q Hold 0 0 1 Q Q Hold 1 0 1 1 0 Set 0 1 1 0 1 Reset 1 1 1 0 0 not allowed
THE GATED D LATCH Only has one input in addition to EN. This input is called the D (data) input. -When the D input is HIGH and the EN input is HIGH, the latch will SET. -When the D input is LOW and EN is HIGH, the latch will RESET. -Another way, the output Q follows the input D when EN is HIGH Initially RESET
EDGE-TRIGGERED FLIP-FLOPS Edge-triggered S-R flip-flop Edge-triggered D flip-flop Edge-triggered J-K flip-flop
EDGE-TRIGGERED FLIP-FLOP LOGIC SYMBOLS (TOP: POSITIVE EDGE-TRIGGERED; BOTTOM: NEGATIVE EDGE- TRIGGERED).
Clock Signals & Synchronous Sequential Circuits 1 Clock signal 0 Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock Cycle Time A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.
THE EDGE-TRIGGERED S-R FLIP- FLOP The S and R inputs of the S-R flip-flop are called synchronous input because data on these inputs are transferred to the flip-flop s output only on the triggering edge of the clock pulse. Operation
OPERATION OF A POSITIVE EDGE- TRIGGERED S-R FLIP-FLOP Example
Example: Determine the Q and Q output waveforms of the flip-flop (Assume is initially RESET)
Exercise: Determine the Q and Q output waveforms of the flip-flop (Assume is initially RESET) and it is a negative edge-triggered device
THE EDGE-TRIGGERED D FLIP-FLOP The D flip-flop is useful when a single data bit (1 or 0) is to be stored. Example
Example: Determine the Q output waveform if the flip-flop starts out RESET Try This: Determine the Q output for the D flip-flop if the D input is inverted
Answer for related question
THE EDGE-TRIGGERED J-K FLIP- FLOP The J-K flip-flop is versatile and is widely used type of flip-flop. The difference is that he J-K flip-flop has no invalid state as does the S-R flip-flop. Example
Example: Determine the Q output, assuming that the flip-flop is initially RESET
Exercise: Determine the Q output, starting in the RESET state.
ASYNCHRONOUS PRESET AND CLEAR INPUTS The state of the flip-flop independent of the clock. The asynchronous inputs override the synchronous inputs. Active-LOW preset and clear inputs
Truth table of J-K flip-flop with Asynchronous inputs PRE CLR Q 0 0 INVALID 0 1 1 (SET) 1 0 0 (RESET) 1 1 SYNCRONOUS(clocked operation) These preset and clear inputs must both be kept HIGH for synchronous operation. When the PRE and the CLR inputs are used inputs J and K have no effect on the operation of the flip-flop. To use the flip-flop with synchronous inputs J-K, the PRE and the CLR inputs are set to logic 1. Setting PRE and the CLR to logic 0 is not allowed.
Example: Determine the Q output for the inputs shown in the timing diagram. Q is initially LOW. SET Toggle RESET
Exercise: Interchange the /PRE and /CLR waveforms, what will the Q output look like?
FLIP-FLOP APPLICATIONS Parallel Data Storage Frequency Division Counting
PARALLEL DATA STORAGE A common requirement in digital systems is to store several bits of data from parallel lines simultaneously in a group of flip-flops.
FREQUENCY DIVISION 2 n : n is number of flip-flops. Example: 2 flip-flop will divided frequency by 4 (2 2 )
Example: Develop the f out waveform for the circuit below when the 8 khz square wave input is applied to the clock input of flip-flop A
COUNTING The Q output of flip flop A clocks flip flop B. If Q A is taken as the least significant bit, a 2 bit sequenced is produced as the flip flop clocked. The binary sequence repeats every 4 clock pulses.
EXAMPLE Determine the output waveform in relation to the clock for Q A,Q B and Q C in the circuit below and show the binary sequence represented by these waveform.