Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 5 LSTTL Loads Low Power Consumption, 80-µA Max I CC Typical t pd = 22 ns ±6-mA Output Drive at 5 V Low Input Current of µa Max Bus-Structured Pinout description/ordering information These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. TA SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS8F DECEMBER 982 REVISED AUGUST 03 ORDERING INFORMATION PACKAGE SN54HC574...J OR W PACKAGE SN74HC574... DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) ORDERABLE PART NUMBER SN54HC574... FK PACKAGE (TOP VIEW) 3 4 2 9 8 5 6 7 8 7 5 9023 TOP-SIDE MARKING PDIP N Tube of SN74HC574N SN74HC574N SOIC DW Tube of 25 SN74HC574DW Reel of 00 SN74HC574DWR HC574 40 C to 85 C SSOP DB Reel of 00 SN74HC574DBR HC574 SOP NS Reel of 00 SN74HC574NSR HC574 Tube of 70 SN74HC574PW TSSOP PW Reel of 00 SN74HC574PWR HC574 Reel of 250 SN74HC574PWT CDIP J Tube of SNJ54HC574J SNJ54HC574J 55 C to 25 C CFP W Tube of 85 SNJ54HC574W SNJ54HC574W LCCC FK Tube of 55 SNJ54HC574FK SNJ54HC574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. 3D 4D 5D 6D 7D OE D 2D 3D 4D 5D 6D 7D 8D GND 2 3 4 5 6 7 8 9 0 2D D 8D GND CLK 9 8 7 5 3 2 OE V CC Q 8Q 7Q V CC Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 2Q 3Q 4Q 5Q 6Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 03, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS8F DECEMBER 982 REVISED AUGUST 03 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L H H L L L L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK D 2 D C 9 Q To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0.5 V to 7 V Input clamp current, I IK (V I < 0 or V I > V CC ) (see Note ).................................... ± ma Output clamp current, I OK (V O < 0 or V O > V CC ) (see Note )................................ ± ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±35 ma Continuous current through V CC or GND................................................... ±70 ma Package thermal impedance, θ JA (see Note 2): DB package................................. 70 C/W DW package................................. 58 C/W N package................................... 69 C/W NS package................................. 60 C/W PW package................................. 83 C/W Storage temperature range, T stg................................................... 65 C to 50 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 5-7. 2
recommended operating conditions (see Note 3) SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS8F DECEMBER 982 REVISED AUGUST 03 SN54HC574 SN74HC574 MIN NOM MAX MIN NOM MAX Supply voltage 2 5 6 2 5 6 V = 2 V.5.5 VIH High-level input voltage = 4.5 V 3.5 3.5 V = 6 V 4.2 4.2 = 2 V 0.5 0.5 VIL Low-level input voltage = 4.5 V.35.35 V = 6 V.8.8 VI Input voltage 0 0 V VO Output voltage 0 0 V = 2 V 000 000 t/ v Input transition rise/fall time = 4.5 V 500 500 ns = 6 V 400 400 TA Operating free-air temperature 55 25 40 85 C NOTE 3: All unused inputs of the device must be held at or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VOH VI I = VIH or VIL VOL VI I = VIH or VIL TA = 25 C SN54HC574 SN74HC574 MIN TYP MAX MIN MAX MIN MAX 2 V.9.998.9.9 IOH = µa 4.5 V 4.4 4.499 4.4 4.4 6 V 5.9 5.999 5.9 5.9 V IOH = 6 ma 4.5 V 3.98 4.3 3.7 3.84 IOH = 7.8 ma 6 V 5.48 5.8 5.2 5.34 2 V 0.002 0. 0. 0. IOL = µa 4.5 V 0.00 0. 0. 0. 6 V 0.00 0. 0. 0. V IOL = 6 ma 4.5 V 0.7 0.26 0.4 0.33 IOL = 7.8 ma 6 V 0.5 0.26 0.4 0.33 II VI = or 0 6 V ±0. ±00 ±000 ±000 na IOZ VO = or 0 6 V ±0.0 ±0.5 ±0 ±5 µa ICC VI = or 0, IO = 0 6 V 8 0 80 µa Ci 2 V to 6 V 3 0 0 0 pf UNIT UNIT 3
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS8F DECEMBER 982 REVISED AUGUST 03 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25 C SN54HC574 SN74HC574 MIN MAX MIN MAX MIN MAX 2 V 6 4 5 fclock Clock frequency 4.5 V 30 24 MHz 6 V 38 24 28 2 V 80 00 tww Pulse duration, CLK high or low 4.5 V 24 ns 6 V 7 2 V 00 50 25 tsu Setup time, data before CLK 4.5 V 30 25 ns 6 V 7 26 2 2 V 5 5 5 thh Hold time, data after CLK 4.5 V 5 5 5 ns 6 V 5 5 5 UNIT switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25 C SN54HC574 SN74HC574 MIN TYP MAX MIN MAX MIN MAX 2 V 6 4 5 fmax 4.5 V 30 36 24 MHz 6 V 36 40 24 28 2 V 90 80 270 225 tpd CLK Any Q 4.5 V 28 36 54 45 ns 6 V 24 3 46 38 2 V 77 50 225 90 ten OE Any Q 4.5 V 26 30 45 38 ns 6 V 23 26 38 32 2 V 52 50 225 90 tdis OE Any Q 4.5 V 24 30 45 38 ns 6 V 22 26 38 32 2 V 28 60 90 75 ttt Any Q 4.5 V 8 2 8 5 ns 6 V 6 0 5 3 UNIT 4
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS8F DECEMBER 982 REVISED AUGUST 03 switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25 C SN54HC574 SN74HC574 MIN TYP MAX MIN MAX MIN MAX 2 V 6 5 fmax 4.5 V 30 24 MHz 6 V 36 28 2 V 05 265 400 330 tpd CLK Any Q 4.5 V 36 53 80 66 ns 6 V 3 46 68 57 2 V 95 235 355 295 ten OE Any Q 4.5 V 32 47 7 59 ns 6 V 28 4 60 5 2 V 60 35 265 ttt Any Q 4.5 V 7 42 63 53 ns 6 V 36 53 45 UNIT operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance per flip-flop No load 00 pf 5
SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS8F DECEMBER 982 REVISED AUGUST 03 PARAMETER MEASUREMENT INFORMATION PARAMETER RL CL S S2 From Output Under Test CL (see Note A) Test Point RL LOAD CIRCUIT S S2 ten tpzh tpzl tdis tphz tplz tpd or tt kω kω 50 pf or 50 pf 50 pf 50 pf or 50 pf Open Closed Open Closed Open Closed Open Closed Open Open High-Level Pulse Low-Level Pulse tw VOLTAGE WAVEFORMS PULSE DURATIONS 0 V 0 V Reference Input Data Input 0% tsu VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES th 90% 90% tr 0 V 0% 0 V tf Input In-Phase Output Out-of- Phase Output tplh 0% tphl 90% 90% 90% tr tphl 0% 0% tf tplh 0 V VOH 0% VOL tf VOH 90% VOL tr Output Control (Low-Level Enabling) tpzl Output Waveform (See Note B) Output Waveform 2 (See Note B) tpzh tplz 0% tphz 90% 0 V VOL VOH 0 V VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is. E. The outputs are measured one at a time with one input transition per measurement. F. tplz and tphz are the same as tdis. G. tpzl and tpzh are the same as ten. H. tplh and tphl are the same as tpd. Figure. Load Circuit and Voltage Waveforms 6
MCFP006B JANUARY 995 REVISED JULY 03 W (R-GDFP-F) CERAMIC DUAL FLATPACK 0.045 (,) 0.026 (0,66) 0.300 (7,62) 0.245 (6,22) Base and Seating Plane 0.00 (2,54) 0.045 (,) 0.3 (8,3) MAX 0.009 (0,23) 0.004 (0,0) 0.022 (0,56) 0.05 (0,38) 0.050 (,27) 0.540 (3,72) MAX 0.005 (0,3) MIN 4 Places 0 0.370 (9,40) 0.250 (6,35) 0.370 (9,40) 0.250 (6,35) 404080-4/D 07/03 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification only. E. Falls within Mil-Std 835 GDFP2-F
MECHANICAL DATA MLCC006B OCTOBER 996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 8 7 5 3 2 NO. OF TERMINALS ** MIN A MAX MIN B MAX 9 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) A SQ B SQ 2 22 23 24 25 26 27 28 2 3 4 0 9 8 7 6 5 28 44 52 68 84 0.442 (,23) 0.640 (,26) 0.739 (8,78) 0.938 (23,83). (28,99) 0.458 (,63) 0.660 (,76) 0.76 (9,32) 0.962 (24,43).5 (29,59) 0.406 (0,3) 0.495 (2,58) 0.495 (2,58) 0.850 (2,6).047 (26,6) 0.458 (,63) 0.560 (,22) 0.560 (,22) 0.858 (2,8).063 (27,0) 0.0 (0,5) 0.00 (0,25) 0.080 (2,03) 0.064 (,63) 0.0 (0,5) 0.00 (0,25) 0.055 (,40) 0.045 (,) 0.045 (,) 0.035 (0,89) 0.028 (0,7) 0.022 (0,54) 0.050 (,27) 0.045 (,) 0.035 (0,89) 40400/ D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
MPDI002C JANUARY 995 REVISED DECEMBER 002 N (R-PDIP-T**) PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE DIM PINS ** 8 A A MAX 0.775 (9,69) 0.775 (9,69) 0.9 (23,37).060 (26,92) 9 A MIN 0.745 (8,92) 0.745 (8,92) 0.850 (2,59) 0.940 (23,88) 0.260 (6,60) 0.240 (6,0) C MS-00 VARIATION AA BB AC AD 0.070 (,78) 0.045 (,) D 8 0.045 (,) 0.030 (0,76) D 0.0 (0,5) MIN 0.325 (8,26) 0.300 (7,62) 0.05 (0,38) 0.0 (5,08) MAX Gauge Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M 0.430 (0,92) MAX /8 PIN ONLY pin vendor option D 4040049/E 2/02 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00, except 8 and pin minimum body lrngth (Dim A). D. The pin end lead shoulder width is a vendor option, either half or full width.
MECHANICAL DATA MSOI003E JANUARY 995 REVISED SEPTEMBER 0 DW (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.050 (,27) 0.0 (0,5) 0.0 (0,35) 9 0.00 (0,25) 0.299 (7,59) 0.29 (7,39) 0.49 (0,65) 0.400 (0,5) 0.00 (0,25) NOM Gage Plane 0.00 (0,25) A 8 0 8 0.050 (,27) 0.0 (0,40) 0.04 (2,65) MAX 0.02 (0,30) 0.004 (0,0) Seating Plane 0.004 (0,0) DIM PINS ** 8 24 28 A MAX 0.40 0.462 (0,4) (,73) 0.50 (2,95) 0.60 (5,49) 0.70 (8,03) A MIN 0.400 (0,) 0.453 (,5) 0.500 (2,70) 0.600 (5,24) 0.700 (7,78) 4040000/E 08/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,5). D. Falls within JEDEC MS-03
MECHANICAL DATA MSSO002E JANUARY 995 REVISED DECEMBER 0 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,5 M 28 5 5,60 5,00 8, 7,40 0,25 0,09 Gage Plane 0,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,0 DIM PINS ** 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 0,50 0,50 2,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 2,30 4040065 /E 2/0 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-50
MECHANICAL DATA MTSS00C JANUARY 995 REVISED FEBRUARY 999 PW (R-PDSO-G**) PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,0 M 0,9 8 4,50 4,30 6,60 6, 0,5 NOM Gage Plane A 7 0 8 0,25 0,75 0,50, MAX 0,5 0,05 Seating Plane 0,0 DIM PINS ** 8 24 28 A MAX 3,0 5,0 5,0 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 0/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,5. D. Falls within JEDEC MO-53
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