RS flip-flop using NOR gate
Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two types of triggering. 1. Edge triggering : (i) Positive edge triggering, (ii) Negative edge triggering 2. Level triggering : (i) Positive level triggering, (ii) Negative level triggering
1. Edge triggering : The circuits which change their outputs only corresponding to the positive or negative edge of the clock input are called as edge triggered circuit.
Symbol of positive edge triggered flip-flop
Symbol of Negative edge triggered flip-flop
Level triggering : The circuits which change their outputs only corresponding to the positive or negative level of the clock input are called as level triggered circuit.
Symbol of positive level triggered flip-flop
Symbol of negative level triggered flip-flop
clock Clocked R-S flip-flop:-
Clock
S-R flip-flop with preset and clear In the flip-flop when the power is switched on, the state of the circuit is uncertain. In many applications it is desired to initially set or reset the flip-flop, i.e. the initial state of the flipflop is to be assigned. This is accomplished by using preset (Pr) and clear (Cr) inputs.
S-R flip-flop with preset and clear
Logic symbol for S-R flip-flop with preset and clear:-
J-K flip-flop:- The forbidden state of S-R flip-flop when S = R = 1 can be eliminated by converting it into JK flip-flop. The data inputs are J and K which are ANDed with Q and Q respectively to obtain S and R inputs i.e. S = J Q R = K Q.
J-K flip-flop:-
Logic symbol:-
for J = K = 0, Q retains its previous value. for J = 1 and K = 0 sets the flip-flop. for J = 0 and K = 1 RESETS the flip-flop. for J = K = 1 Flip flop toggles between 0 and 1
Race around condition If J = K = 1 and Q = 0 and pulse is applied at the clock input. After a time interval t equal to propagation delay the output will change to Q = 1. Now we have J = K = 1 and Q = 1 and after another time interval of t the output will change back to Q = 0. Hence, for the duration tp of the clock pulse the output will oscillate back and forth between 0 and 1. At the end of clock pulse the value of Q is uncertain. This situation referred to as a race around condition.
J-K flip-flop using NAND gate:-
Master-slave J-K flip-flop:-
D-type flip-flop:-
T-type flip-flop:- Symbol of T flip-flop T = 1,
EXCITATION TABLE OF FLIP-FLOP The truth table of flip-flop is also referred to as the characteristic table. In the design of sequential circuit, if the present state and next state of the circuit are specified and we have to find the input conditions that must prevail to cause the desired transition of the state. The tabulation of these conditions is known as excitation Table.
APPLICATION OF FLIP- FLOP 1.Bounce elimination switch 2. Latch 3. Registers 4. Counters 5. Memory
COUNTERS A circuit used for counting the number of pulses is known as a counter. The counters are referred to as modulo N (mod N) counter there are two types of counters. 1. Asynchronous counter (ripple counter) 2. Synchronous counter In case of asynchronous counter, all the flip-flops are not clocked simultaneously, whereas in synchronous counter all flip-flops are clocked simultaneously. Ring counter and twisted ring counters are examples of synchronous counter.
Ring counter:-
Waveforms of ring counter
Twisted Ring Counter In ring counter, if Q1 is connected to serial input instead of Q1 then the circuit is called as twisted ring counter. The flipflops are cleared first and then clock is applied.