RS flip-flop using NOR gate
Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two types of triggering. 1. Edge triggering : (i) Positive edge triggering, (ii) Negative edge triggering 2. Level triggering : (i) Positive level triggering, (ii) Negative level triggering
1. Edge triggering : The circuits which change their outputs only corresponding to the positive or negative edge of the clock input are called as edge triggered circuit.
Symbol of positive edge triggered flip-flop
Symbol of Negative edge triggered flip-flop
Level triggering : The circuits which change their outputs only corresponding to the positive or negative level of the clock input are called as level triggered circuit.
Symbol of positive level triggered flip-flop
Symbol of negative level triggered flip-flop
Clocked R-S flip-flop:- R clock S
Clock
S-R flip-flop with preset and clear In the flip-flop when the power is switched on, the state of the circuit is uncertain. In many applications it is desired to initially set or reset the flip-flop, i.e. the initial state of the flipflop is to be assigned. This is accomplished by using preset (Pr) and clear (Cr) inputs.
S-R flip-flop with preset and clear
Logic symbol for S-R flip-flop with preset and clear:-
J-K flip-flop:- The forbidden state of S-R flip-flop when S = R = 1 can be eliminated by converting it into JK flip-flop. The data inputs are J and K which are ANDed with Q and Q respectively to obtain S and R inputs i.e. S = J Q R = K Q.
J-K flip-flop:-
Logic symbol:-
J-K flip-flop using NAND gate:-
for J = K = 0, Q retains its previous value. for J = 1 and K = 0 sets the flip-flop. for J = 0 and K = 1 RESETS the flip-flop. for J = K = 1 Flip flop toggles between 0 and 1
Race around condition If J = K = 1 and Q = 0 and pulse is applied at the clock input. After a time interval t equal to propagation delay the output will change to Q = 1. Now we have J = K = 1 and Q = 1 and after another time interval of t the output will change back to Q = 0. Hence, for the duration tp of the clock pulse the output will oscillate back and forth between 0 and 1. At the end of clock pulse the value of Q is uncertain. This situation referred to as a race around condition.
Master-slave J-K flip-flop:-
D-type flip-flop:-
T-type flip-flop:- Symbol of T flip-flop T = 1,
IC 7474 - Dual D-type positive edge triggered flip-flop
IC 7475 Edge triggered D-flip-flop
IC 74373 latch
EXCITATION TABLE OF FLIP-FLOP The truth table of flip-flop is also referred to as the characteristic table. In the design of sequential circuit, if the present state and next state of the circuit are specified and we have to find the input conditions that must prevail to cause the desired transition of the state. The tabulation of these conditions is known as excitation Table.
APPLICATION OF FLIP- FLOP 1.Bounce elimination switch 2. Latch 3. Registers 4. Counters 5. Memory
COUNTERS A circuit used for counting the number of pulses is known as a counter. The counters are referred to as modulo N (mod N) counter there are two types of counters. 1. Asynchronous counter (ripple counter) 2. Synchronous counter In case of asynchronous counter, all the flip-flops are not clocked simultaneously, whereas in synchronous counter all flip-flops are clocked simultaneously. Ring counter and twisted ring counters are examples of synchronous counter.
Normal binary counter counts from 0 to 2 N - 1, where N is the number flip-flops in the counter. In some cases, we want it to count to numbers other than 2 N - 1. This can be done by allowing the counter to skip states that are normally part of the counting sequence. There are a few methods of doing this. One of the most common methods is to use the CLEAR input on the flip-flops.
The 2-bit ripple counter circuit has four different states, each one corresponding to a count value. Similarly, a counter with n flip-flops can have 2 to the power n states. The number of states in a counter is known as its mod (modulo) number. Thus a 2-bit counter is a mod-4 counter. A mod-n counter may also described as a divide-byn counter. This is because the most significant flip-flop produces one pulse for every n pulses at the clock input of the least significant flip-flop. Thus, the above counter is an example of a divide-by-4 counter.
Ring counter:-
Waveforms of ring counter
Twisted Ring Counter In ring counter, if Q1 is connected to serial input instead of Q1 then the circuit is called as twisted ring counter. The flipflops are cleared first and then clock is applied.
Design a 3-bit synchronous counter using JK flipflop To design this counter, 3 flip-flops are required and 8 states are present. The excitation table of flip-flop can be written as
The k-maps and simplified expressions for all the flip-flops are as follows - Thus, the simplified equations are J C = Q B Q A K C = Q B Q A J B = Q A K B = Q A J A = 1 K A = 1
3-bit synchronous counter using JK FF
Design 3 bit synchronous counter using T flip-flops A 3 bit counter goes through 8 states thus it requires three flip-flops. The excitation table of T flip-flop is given as -
ASYNCHRONOUS COUNTER-up counter
Count sequence
Timing diagram of 3 bit asynchronous counter-up counter
Asynchronous Down Counters
Timing diagram of 3 bit asynchronous counter-down counter
A 3 bit asynchronous up-down counter
STUDY OF IC 7490:-
Timing diagram:-
Count sequence:-
Design a MOD 6 asynchronous counter using IC 7490.
MOD 20 counter using IC 7490
Design MOD 8 counter using IC 7490
APPLICATIONS OF COUNTERS 1. In digital clock. 2. In time measurement. 3. In the frequency counters. 4. In digital voltmeters. 5. In counter type A/D converter. 6. In digital triangular wave generator. 7. In frequency divider circuits.
COMPARISON OF SYNCHRONOUS AND ASYNCHRONOUS COUNTER
COMPARISON OF COUNTERS AND REGISTERS:-
DISADVANTAGE OF RIPPLE COUNTERS Every flip-flop has its own propagation delay. In ripple counter the output of previous flip-flop is used as clock for next flip-flop. Thus, the propagation delay goes on accumulating. Thus, as the number of flip-flops goes on increasing, the propagation delay increases. The frequency of clock pulse for reliable operations of counter is given by