Ethernet Switch Ethernet Interfaces Reference Design Contents 1.0 Introduction............................ 1 2.0 Interface Overview....................... 1 2.1 Fast Ethernet......................... 2 2.2 Gigabit Ethernet....................... 4 2.3 MII Management...................... 6 3.0 Interface Reference Design................ 9 3.1 Fast Ethernet......................... 9 3.2 Gigabit Ethernet...................... 12 4.0 Layout Guidelines...................... 15 4.1 M_CLK............................. 15 4.2 G_REFCLK......................... 15 4.3 10/100M Ethernet Physical Layer........ 16 1.0 Introduction This application note describes the Ethernet interfaces found on Zarlink s Ethernet Switches. Readers of this document should be familiar with the applicable Ethernet Switch datasheet before proceeding. 2.0 Interface Overview June 2006 Zarlink Ethernet Switches support many IEEE and/or industry standard interfaces. These interfaces are generally used to connect the MAC block of the Ethernet Switch to the PCS block of the PHY. Figure 1 highlights the IEEE 802.3 layers. This document will concentrate on the MAC-to-PHY connections. For MAC-to-MAC connections, please refer to the MAC-to- MAC Connections, ZLAN-30. In order to simplify the design-in of Zarlink Ethernet Switches into a customer s application, this document will go over the types of interfaces available on Zarlink Ethernet Switches and provide a reference design illustrating the interface. Figure 1 - IEEE 802.3 Layers 1 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Copyright 2004-2006, All Rights Reserved.
2.1 Fast Ethernet For the Fast Ethernet (FE) ports, the following interfaces are available: GPSI - General Purpose Serial Interface (also known as 7WS (7-Wire Serial)) MII - Media Independent Interface (IEEE 802.3) RMII - Reduced MII SMII - Serial MII The sections below provide a brief overview of the above interfaces. 2.1.1 GPSI This industry standard interface supports 1/10M speeds with half duplex operation. Most of Zarlink switches also supports a full duplex operation. GPSI uses two independent clocks, RXCLK and TXCLK, to clock a serial transmit bus (TXD) and serial receive bus (RXD). These two buses are independent from each other as far as the switch is concerned. Two clock speeds are used: a 1MHz clock for 1M interfaces and a 10MHz clock for 10M interfaces. Additional signals are highlighted in Table 1. From the MAC point of view, only transmit data (TXD) and transmit enable (TXEN) are outputs, the rest of the signals are inputs. The table below highlights the GPSI signals. GPSI Signal Name MAC Signal Direction Description Notes TXD O Transmit Data Bit driven on rising edge of TXCLK TXEN O Transmit Data Enable indicates valid TXD TXCLK I Transmit Clock 1 MHz (1 M) or 10 MHz (10 M) RXD I Receive Data Bit driven on rising edge of RXCLK RXDV I Receive Data Valid indicates valid RXD (full duplex only) RXCLK I Receive Clock 1 MHz (1 M) or 10 MHz (10M) CRS I Carrier Sense active during tx/rx activity COL I Collision Detected asserted when collision detected in tx/rx path Table 1 - GPSI Signal Description 2.1.2 MII This is the standard IEEE 802.3 Ethernet Interface, supporting 10/100M speeds and both full duplex and half duplex operation. It uses two independent clocks, RXCLK and TXCLK, to clock a 4-bit transmit bus (TXD[3:0]) and 4-bit receive bus (RXD[3:0]). These two buses are independent from each other as far as the switch is concerned. Two clock speeds are used: a 2.5 MHz clock for 10M interfaces and a 25 MHz clock for 100 M interfaces. Additional signals are highlighted in Table 2. From the MAC point of view, only transmit data (TXD[3:0]), transmit enable (TXEN), and transmit error (TXER) are outputs, the rest of the signals are inputs. Support of TXER is optional for switches, and most of Zarlink switch interfaces either don t have this signal pin, or allows the signal pin to be connected but would never be used. The RXER signal needs to be provided by the PHY, but is an optional connect to the switch. Again, Zarlink switches either don t have this signal pin, or allows the signal pin to be connected but would never be used. 2
The table below highlights the MII signals. MII Signal Name MAC Signal Direction Description Notes TXD[3:0] O Transmit Data Bits [3:0] driven on rising edge of TXCLK TXEN O Transmit Data Enable indicates valid TXD[3:0] TXER O Transmit Error indicates error during transmission (optional signal for MAC) TXCLK I Transmit Clock 2.5 MHz (10 M) or 25 MHz (100 M) RXD[3:0] I Receive Data Bits [3:0] driven on rising edge of RXCLK RXDV I Receive Data Valid indicates valid RXD[3:0] RXER I Receive Error indicates error during reception (optional signal for MAC) RXCLK I Receive Clock 2.5 MHz (10 M) or 25 MHz (100 M) CRS I Carrier Sense active during tx/rx activity COL I Collision Detected asserted when collision detected in tx/rx path Table 2 - MII Signal Description 2.1.3 RMII This is an industry standard Interface, supporting 10/100M speeds and both full duplex and half duplex operation. It uses a common clock, M_CLK, to clock a 2-bit transmit bus (TXD[1:0]) and 2-bit receive bus (RXD[1:0]). All data signals are synchronous to the clock. Only one clock speed is used, 50 MHz clock for 10/100M interfaces. For 10 M mode, the data on the bus is repeated 10 times, thus, why only a 50 MHz clock is required. Additional signals are highlighted in Table 3. From the MAC point of view, only transmit data (TXD[1:0]) and transmit enable (TXEN) are outputs, the rest of the signals are inputs. The table below highlights the RMII signals. RMII Signal Name MAC Signal Direction Description Notes TXD[1:0] O Transmit Data Bits [1:0] driven on rising edge of M_CLK TXEN O Transmit Data Enable indicates valid TXD[1:0] RXD[1:0] I Receive Data Bits [1:0] driven on rising edge of M_CLK CRS_DV I Carrier Sense and Receive Data Valid indicates valid RXD[1:0], and active during tx/rx activity M_CLK I Reference Clock 50 MHz (10/100M) common clock (provided to both the MAC and the PHY) Table 3 - RMII Signal Description 3
2.1.4 SMII This is an industry standard Interface, supporting 10/100M speeds and both full duplex and half duplex operation. It uses a common clock, M_CLK, to clock a serial transmit bus (TXD) and serial receive bus (RXD). All signals are synchronous to the clock. Only one clock speed is used, 125 MHz clock for 10/100M interfaces, along with a common synchronization pulse (SYNC) used to deliminate the Tx/Rx segment boundaries. For 10 M mode, the data on the bus is repeated 10 times, thus, why only a 125 MHz clock is required. Additional signals are highlighted in Table 4. From the MAC point of view, only transmit data (TXD) and synchronization signal (SYNC) are outputs, the rest of the signals are inputs. The table below highlights the SMII signals. SMII Signal Name MAC Signal Direction Description Notes 2.2 Gigabit Ethernet For the Gigabit Ethernet (GE) ports, the following interfaces are available: GMII - Gigabit MII (IEEE 802.3) TBI - Ten-Bit Interface (IEEE 802.3) Most GE ports also support a MII interface. The sections below provide a brief overview of the above interfaces. 2.2.1 GMII TXD O Transmit Data and Control driven on rising edge of M_CLK (contains both data and control signals) RXD I Receive Data and Control driven on rising edge of M_CLK (contains both data and control signals) M_CLK I Reference Clock 125 MHz common clock (provided to both the switch and the PHY) SYNC O Synchronization deliminates TXD/RXD segment boundaries (pulse every 10 clocks). This signal is common for each port group. Table 4 - SMII Signal Description This is the standard IEEE 802.3 Ethernet Interface, supporting 10/100/1000M speeds and both full duplex and half duplex operation. It uses three independent clocks, RXCLK, TXCLK and MTXCLK, to clock a 4/8-bit transmit bus (TXD[7:0]) and 4/8-bit receive bus (RXD[7:0]). These two buses are independent from each other as far as the switch is concerned. Three clock speeds are used: a 125 MHz clock for 1000 M interfaces, a 25 MHz clock for 100 M interfaces, and a 2.5 MHz clock for 10 M interfaces. Additional signals are highlighted in Table 5. From the MAC point of view, only transmit data (TXD[3:0]), transmit enable (TXEN), transmit clock (TXCLK), and transmit error (TXER) are outputs, the rest of the signals are inputs. Support of TXER is optional for switches, and most of Zarlink switch interfaces either don t have this signal pin, or allows the signal pin to be connected but would never be used. The RXER signal needs to be provided by the PHY, but is an optional connect to the switch. Again, Zarlink switches either don t have this signal pin, or allows the signal pin to be connected but would never be used. 4
The table below highlights the GMII signals. GMII Signal Name MAC Signal Direction Description Notes TXD[7:0] O Transmit Data Bits [7:0] driven on rising edge of TXCLK or MTXCLK TXEN O Transmit Data Enable indicates valid TXD[7:0] TXER O Transmit error indicates error during transmission (optional signal for MAC) TXCLK O Transmit Clock 125 MHz (1000 M) MTXCLK I MII Transmit Clock 2.5 MHz (10 M) or 25 MHz (100 M) RXD[7:0] I Receive Data Bits [7:0] driven on rising edge of RXCLK RXDV I Receive Data Valid indicates valid RXD[7:0] RXER I Receive error indicates error during reception (optional signal for MAC) RXCLK I Receive Clock 1 MHz (1 M) or 10 MHz (10 M) or 125 MHz (1000 M) CRS I Carrier Sense active during tx/rx activity COL I Collision Detected asserted when collision detected in tx/rx path Table 5 - GMII Signal Description 2.2.2 TBI This is the standard IEEE 802.3 Ethernet Interface, supporting 1000 M speeds and both full duplex and half duplex operation. It uses two independent clocks, RXCLK0/1 and TXCLK, to clock a 10-bit transmit bus (TXD[9:0]) and 10- bit receive bus (RXD[9:0]). These two buses are independent from each other as far as the switch is concerned. Two clock speeds are used: a 125 MHz clock for 1000 M Tx interfaces, and two 62.5 MHz clocks for 1000 M Rx interfaces. Additional signals are highlighted in Table 6. From the MAC point of view, only transmit data (TXD[3:0]) and transmit clock (TXCLK) are outputs, the rest of the signals are inputs. The table below highlights the TBI signals. TBI Signal Name MAC Signal Direction Description Notes TXD[9:0] O Transmit Data Bits [3:0] driven on rising edge of TXCLK TXCLK O Transmit Clock 125 MHz RXD[9:0] I Receive Data Bit [3:0] driven on rising edge of RXCLK0/1 RXCLK0 I Receive Clock 62.5 MHz RXCLK1 I Receive Clock 62.5 MHz (180 o out-of-phase from RXCLK0) Table 6 - TBI Signal Description 5
2.3 MII Management The IEEE 802.3 MII Management Interface uses a simple 3-wire, serial interface for purpose of controlling the PHY and gathering status from the PHY. The Management Interface can control up to 32 PHY devices. There are total 32 16-bit registers which resided inside the PHY. Only 2 registers, Control register (register 0) and Status register (register 1), are commonly used in the communication between management entity and the PHY. 2.3.1 MII Management Interface All Zarlink switches support the IEEE 802.3 MII Management interface. This interface is made up of a bi-directional serial data signal, MDIO, and a clock,. Optionally, an interrupt pin can be used, however, Zarlink switches do not support the interrupt signal. The table below highlights the MDIO signals. MDIO Signal Name MAC Signal Direction Description Notes MDIO I/O MII Management Data driven on rising edge of O MII Management Clock min. 400ns period Table 7 - MDIO Signal Description 2.3.2 PHY Register Set The following registers are resided inside the PHY device. Register address Register name Basic/Extend 0 Control B 1 Status B 2-3 PHY Identifier E 4 Auto-Negotiation Advertisement E 5 Auto-Negotiation Link Partner Ability E 6 Auto-Negotiation Expansion E 7 Auto-Negotiation Next Page Transmit E 8-15 Reserved E 16-31 Vendor Specific E The following sections describe PHY registers 0 & 1. For more description of the PHY register set, refer to IEEE 802.3 chapter "22.2.4 Management functions". 6
2.3.2.1 PHY Control Register (Register 0) Bit Name Description R/W 15 Reset 1=PHY reset R/W 0=normal operation 14 Loopback 1=enable loopback mode R/W 0=disable loopback mode 13 Speed selction 1=100Mbps R/W 0=10Mbps 12 Auto-Negotiation enable 1=enable auto-negotiation process R/W 0=disable auto-negotiation process 11 Power Down 1=power down R/W 0=normal operation 10 Isolate 1=electrically Isolate PHY from MII R/W 0=normal operation 9 Restart Auto-Negotiation 1=restart auto-negotiation process R/W 0=normal operation 8 Duplex Mode 1=full duplex R/W 0=half duplex 7 Collision Test 1=enable COLL signal test R/W 0=disable COLL signal test 0-6 Reserved Write as 0, ignore Read R/W 7
2.3.2.2 PHY Status Register (Register 1) Bit Name Description R/W 15 100Base-T4 1=PHY able to perform 100Base-T4 R 0=PHY not able to perform 100Base-T4 14 100Base-X Full Duplex 1=PHY able to perform 100Base-X Full Duplex R 0= PHY not able to perform 100Base-X Full Duplex 13 100Base-X Half Duplex 1=PHY able to perform 100Base-X Half Duplex R 0=PHY not able to perform 100Base-X Half Duplex 12 10Mbps Full Duplex 1=PHY able to perform 10Mbps in Full Duplex R 0=PHY not able to perform 10Mbps in Full Duplex 11 10Mbps Half Duplex 1=PHY able to perform 10Mbps in Half Duplex R 0=PHY not be able to perform 10Mbps in Half Duplex 7-10 Reserved Ignore when read R 6 MF Preamble Suppression 1=PHY accept mangmt frame with preamble suppressed R 0=PHY not accept mangmt frame with preamble suppressed 5 Auto-Negotiation 1=Auto-negotiation process completed R Complete 0=Auto-negotiation process not completed 4 Remote Fault 1=remote fault condition detected R 0=no remote fault condition detected 3 Auto-Negotiation 1=PHY is able to perform auto-negotiation R Ability 0=PHY is not able to perform auto-negotiation 2 Link Status 1=link is up R 0=link is down 1 Jaber Detect 1=jabber condition detected R 0=no jabber condition detected 0 Extended Capability 1=extended register capabilities R 0=basic register set capabilities only 8
3.0 Interface Reference Design The previous section highlighted the signals required for each interface. This section will provide reference examples based on Zarlink s reference designs. The complete system reference design for each device is available on request. 3.1 Fast Ethernet The following figures highlights details of each FE interface. 3.1.1 GPSI Figure 2 shows a GPSI connection using the ZL50408 and AMD79C901 as an example. The following GPSI PHYs have been used with Zarlink switches: AMD AM79C901 - HomePHY /10M PHY Transceiver 3.3V AMD79C901 ZL50408 SDO/MDIO 68 F2 MDIO SCLK/ 70 F1 RESET# 63 C1 RESETOUT# TXD0/TXDAT 17 J1 M0_TXD0 TX_EN/TXEN 16 H2 M0_TXEN TX_CLK/TXCLK 15 J3 M0_TXCLK RX_CLK/RXCLK 8 G3 M0_RXCLK RXD/RXDAT 4 G1 M0_RXD0 COL/CLS 26 E2 M0_COL CRS/RXCRS 28 H1 M0_CRSDV Figure 2 - GPSI Signal Connections 9
3.1.2 MII Figure 3 shows a MII connection using the ZL50408 and DP83843 as an example. The following MII PHYs have been used with Zarlink switches: National DP83843-10/100M PHY Transceiver Davicom DM9101-10/100M PHY Transceiver Broadcom BCM5208 - Quad 10/100M PHY Transceiver 3.3V DP83843 MDIO 34 F2 MDIO ZL50408 35 F1 RST 1 C1 RESETOUT# TXEN 25 H2 M0_TXEN TXD0 31 J1 M0_TXD0 TXD1 30 J2 M0_TXD1 TXD2 29 H3 M0_TXD2 TXD3 28 G4 M0_TXD3 TXCLK J3 M0_TXCLK RXCLK 18 G3 M0_RXCLK RXDV 20 H1 M0_CRSDV COL 21 E2 M0_COL RXD0 15 G1 M0_RXD0 RXD1 14 G2 M0_RXD1 RXD2 13 F3 M0_RXD2 RXD3 12 F4 M0_RXD3 CRS 22 10K Figure 3 - MII Signal Connections 10
3.1.3 RMII Figure 4 shows a RMII connection using the ZL50408 and AM79C875KC as an example. The following RMII PHYs have been used with Zarlink switches: AMD AM79C875 - Quad 10/100M PHY Transceiver Broadcom AC104 (AH104) - Quad 10/100M PHY Transceiver Marvell 88E3081 - Octal 10/100M PHY Transceiver 3.3V AM79C875KC ZL50408 MDIO 64 F2 MDIO 65 F1 RST# TX_EN[0] 95 C1 86 H2 RESETOUT# M0_TXEN TXD[0]_[0] 85 J1 M0_TXD0 TXD[0]_[1] 84 J2 M0_TXD1 RXD[0]_[0] 79 G1 M0_RXD0 RXD[0]_[1] 78 G2 M0_RXD1 CRS_DV[0] 82 H1 M0_CRSDV REFCLK 66 E2 M_CLK 50MHz Figure 4 - RMII Signal Connections 11
3.1.4 SMII Figure 5 shows a SMII connection using the ZL032 as an example. The following SMII PHYs have been used with Zarlink switches: Marvell 88E3081 - Octal 10/100M PHY Transceiver 3.3V 88E3081 ZL032 MDIO 169 B7 MDIO 172 A7 RST# SYNC0 175 D6 RESETOUT# 165 AE5 M_SYNC0 TXD[0]_[0] 166 AG1 M0_TXD0 RXD[0]_[0] 160 AE2 M0_RXD REFCLK 184 AE7 M_REFCLK 0 125MHz Figure 5 - SMII Signal Connections 3.2 Gigabit Ethernet The following figures highlights details of each GE interface. 3.2.1 GMII Figure 6 shows a GMII connection using the ZL50408 and 88E1000 as an example. The following GMII PHYs have been used with Zarlink switches: Marvell 88E1000(S) - 10/100/1000M PHY Transceiver Marvell 88E1020(S) - Dual 10/100/1000M PHY Transceiver 12
3.3V 88E1000 MDIO 89 F2 MDIO ZL50408 90 F1 RESET# GTX_CLK TXEN TXD0 32 C1 RESETOUT# 125 126 128 A14 M9_TXCLK A16 M9_TXEN H15 M9_TXD0 TXD1 17 H16 M9_TXD1 TXD2 19 G15 M9_TXD2 TXD3 20 G16 M9_TXD3 TXD4 23 F15 M9_TXD4 TXD5 24 F16 M9_TXD5 TXD6 26 E15 M9_TXD6 TXD7 27 E16 M9_TXD7 TXCLK 123 A15 M9_MTXCLK RXCLK 115 B16 M9_RXCLK RXDV 114 D15 M9_RXDV COL 121 C16 M9_COL RXD0 113 G13 M9_RXD0 RXD1 112 G14 M9_RXD1 RXD2 107 F13 M9_RXD2 RXD3 105 F14 M9_RXD3 RXD4 104 E14 M9_RXD4 RXD5 100 D13 M9_RXD5 RXD6 99 D14 M9_RXD6 RXD7 98 C14 M9_RXD7 CRS 122 C15 M9_CRS Figure 6 - GMII Signal Connections 13
3.2.2 TBI Figure 7 shows a TBI connection using the MVTX2804 and S2060 as an example. The following TBI PHYs have been used with Zarlink switches: AMCC S2060 - Single port Gigabit SERDES AMCC S2078 - Dual port Gigabit SERDES Marvell 88E1000S - 10/100/1000M PHY Transceiver with integrated SERDES Marvell 88E1020S - Dual 10/100/1000M PHY Transceiver with integrated SERDES The following transceivers have been used with Zarlink switches: Infineon V23826-K305-C353 S2060 TBC 22 AB4 G0_TXCLK MVTX2804 TXD9 13 AF2 G0_TXER/G0_TXD9 TXD8 12 AD2 G0_TXEN/G0_TXD8 TXD0 2 AB3 G0_TXD0 TXD1 3 W5 G0_TXD1 TXD2 TXD3 4 6 AB2 G0_TXD2 AC3 G0_TXD3 TXD4 7 Y5 G0_TXD4 TXD5 8 AC2 G0_TXD5 TXD6 9 AD4 G0_TXD6 TXD7 11 AA5 G0_TXD7 RXD9 34 AB5 G0_RXER/G0_RXD9 RBC0 31 AC1 G0_RXCLK/G0_RXCLK0 RXD8 35 AD5 G0_RXDV/G0_RXD8 RBC1 30 AD3 G0_COL/G0_RXCLK1 RXD0 45 AD1 G0_RXD0 RXD1 44 AE4 G0_RXD1 RXD2 43 AC4 G0_RXD2 RXD3 41 AE3 G0_RXD3 RXD4 40 AE2 G0_RXD4 RXD5 39 AE1 G0_RXD5 RXD6 38 AC5 G0_RXD6 RXD7 36 AF1 G0_RXD7 To SD on transceiver Y4 G0_CRS/LINK Figure 7 - TBI Signal Connections 14
4.0 Layout Guidelines The section only highlights some of the key layout guidelines for the Ethernet interfaces. Refer to the specific product Layout Guide for more details. 4.1 M_CLK We do not recommend the MK1714 as in the previous design due to the excess clock jitters. Use the ICS601 PLL clock chip is all right. Place the series damping resistors for the M_CLK signals as close to the driver output pins as possible. Route M_CLK in inter layer to prevent EMI interference M_CLK requires synchronization between each PHY chip and the ZL50400 chip (due to port mirroring). Place the clock source near the center of the board. Use a balanced drive clock buffer (or driver). For example, 49FCT3807A. Place the series resistors for each driver as close to its driven output pin of the clock distribution chip as possible. Each of the clock signals must be of equal length (+/- 0.1"). Use minimum 6-mil trace for clock distribution. Keep all other signal trace at least 12 mil clearance from the clock traces. Restrict signals from running parallel on the same or adjacent layer with Clocks for more than 1 inch. 4.2 G_REFCLK What applies to the M_CLK applies here as well. G_REFCLK is the 125 MHz reference to the Gigabit slot modules. To reduce EMI, the signal should be run on inner layers as much as possible. There is NO need for equal length on these signals between two different ports. Equal length between the data bus and the clock is required within each port to get the best error rate. Use 49FCT3807D type clock drivers. Clock driver chip should have a fairly fast rise time. Keep the rise time under 2 ns to allow a reasonable centering of the clock edge relative to the data. Use control impedance method to do the clock signal layout to reduce signal reflections. With the fast edge rate (rise and fall time), this is necessary. Place the series resistors for each output next to its driver output pin of the clock distribution chip. Use minimum 6-mil trace for clock distribution. Keep all other signal trace at least 12 mil clearance from the clock traces. Restrict signals from running parallel on the same or adjacent layer with Clocks for more than 1 inch. 15
4.3 10/100M Ethernet Physical Layer Keep the Ethernet connector area clear from Power and Ground planes. The cut off line should be at the edge of the RJ45 connectors (they have integrated transformers). No signals (other than the signals between the PHY chips and the RJ45 connectors) can be exposed to the area cleared from Power and Ground planes. For the PHY chips, follow the manufacturers recommendation closely. No external signals may pass under the PHY chips on layer 1. It is OK on the other three signal layers. Each differential pair of "TxP", "TxN" (RxP & RxN) signals connected from PHY to the RJ45 should be close together and parallel. The members of a differential pair should maintain 6-mil spacing, but the minimum spacing between different pairs and other signals should be at least 18 mils. The traces in the PHY area (RMII and differential pairs) should be ~50 Ohm impedance. On some PHY chips which use analog front end and have analog power input pins as well as digital power input pins, the analog power input is best isolated from the digital power input with ferrite beat filter components. The digital signal noise may be filter out before it reaches the analog circuitry. Generally follow the same set of instructions as for the 10/100MHz Ethernet physical layer, but since the interface is 125 MHz, and 10 bits wide, they must be treated with extra care. The clock signal should be control impedance design to match the connector impedance at the edge rate frequency. At a rise time of 1ns for this signal, for example, the frequency considered, is at 1 GHz. At this frequency, signal reflection is most likely to happen in a few inches. The differential pairs from the SERDES chips to the Fibre optic transceivers are 1.25 GHz PECL signals and must be treated with EXTREME CARE. Avoid all corners on these signals, and keep the number of vias to a minimum. NO OTHER SIGNALS ARE ALLOWED IN THE AREA OF THESE SIGNALS OR ON ADJACENT LAYERS NEAR THEM. 16
For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by or its subsidiaries (collectively Zarlink ) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink s conditions of sale which are available on request. Purchase of Zarlink s I 2 C components conveys a licence under the Philips I 2 C Patent rights to use these components in and I 2 C System, provided that the system conforms to the I 2 C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Copyright All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE