International Journal of Inventions in Computer Science and Engineering, Volume 2 Issue 4 April 2015 Reading an Image using CMOS Linear Image Sensor S.R.Shinthu 1, P.Maheswari 2, C.S.Manikandababu 3 1,2 PG scholar, Sri Ramakrishna Engineering College, Coimbatore. 3 Assistant professor, Sri Ramakrishna Engineering College, Coimbatore Abstract: This paper presents a CMOS linear image sensor to read an image into FPGA kit. The design chooses FPGA as the hardware platform and VHDL as the software design language, with which the drive time sequence design and signal output mode design are realized. The correctness of the design have been validated through the software emulating and hardware test. Implementation can be done by using Lattice XP2 Brevia Development kit. Keywords: CMOS, FPGA, ADC Reference to this paper should be made as follows: S.R.Shinthu 1, P.Maheswari 2, C.S.Manikandababu 3 (2015) Reading an Image using CMOS Linear Image Sensor, International Journal of Inventions in Computer Science and Engineering, Volume 2 Issue 4 2015 1 Introduction Image sensors are being used in many areas today, in cell phone cameras, digital video recorders, still cameras, and many more devices. The image sensor used in this loom is Hamamatsu S11108. The S11108 is a CMOS linear image sensor that achieves high sensitivity by adding an amplifier to each pixel. It has a long photosensitive area consisting of 2048 pixels, each with a pixel size of 14 14µm.Effective photo sensitive area length is 28.672mm. In this Simultaneous charge integration of all pixels is done. CCD image sensor has extremely low noise and so can acquire image signals with a high signal to noise. Hamamatsu CCD image sensor collects light with zero loss. CMOS image sensors have idyllic features such as low power consumption, small size and more highly integration signal processing circuit. This yields better cost efficiency. APS (Active Pixel Sensor) is an image sensor consisting of an integration circuit containing an array of pixels sensors, each pixel containing a photodetector and an act amplifier. APS used in cell phone, cameras, web camera and some DSLRs. Photodetector is an optoelectronic device that absorbs optical energy and convert it to electrical energy, which usually manifests a photocurrent[1]. Electronic shutter function concept is used, where shutter is a device that allows a light to pass for a determined period of time. Amplifier is used to increase the power of the signal. Small input terminal capacitance is of 5pF.Video data rate is of 10MHz max. II. Image Sensor Architecture After charging of all pixels the last pixel i.e., 2048th pixel will be send to Analog to Digital to analog Converter, Where the analog values from the pixel block is converted to digital signal and these digital outputs will be further implemented in FPGA kit for real time applications. A. Image sensor CMOS linear sensors incorporate a timing circuit and signal processing amplifiers integrated on the same chip, and operate from simple input pulses and single power supply. Thus the external circuit can be cut down. High speed read out type is also available with useful functions for simultaneous charge integration and variable integration time. Image sensor used in this paper is Hamamatsu S11108. Hamamatsu develops and produces advanced image sensors for measurement applications in spectral and energy ranges including infrared, visible, ultraviolet, vacuum ultraviolet, soft X-rays and hard X-rays. Small input terminal capacitance is of 5pF.Video data rate is of 10MHz max. Fig 1 shows the image sensor pixel block, which contains 2048 pixels, ADC and Lattice Xp2 Brevia Development kit (FPGA). Initially once the shutter is opened 2048 Pixels[2] containing capacitor will be charged. ISSN (Online): 2348 3539.
2 S.R.Shinthu et al. Hamamatsu designs and manufactures various types of image sensors that cover a wide supernatural response range from near infrared (NIR) at 2.6µm through visible, ultraviolet, vacuum ultraviolet (VUV) down to soft X-rays and hard X-rays at more than one hundred kev. This contains 2048 pixels once the light of an image falls onto the sensor capacitor will be charged. Simultaneous charging of capacitor is happened then this is followed by the process analog to digital converter. Four clocks are required for reading an image. Clocks namely clock, trigger, Start Of Scan (SOS) and End Of Scan(EOS).\ B. Analog to Digital Converter An analog-to-digital converter (ADC, A/D, or A to D) is a device that converts a unremitting physical quantity (usually voltage) to a digital number that represents the quantity's amplitude. The AD9826 is a complete analog signal processor for imaging applications. It features a 3- channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC, and Programmable Gain Amplifier (PGA), multiplexed to a high-performance 16-bit A/D converter. The AD9826 can operate at speeds greater than 15 MSPS with condensed performance. Once the pixels of image sensors are charged and the end of signal is reached then the analog to digital conversion starts by using clock. III. Timing Chart A. Hamamatsu Image Sensor Timing chart describes the working of Image sensor. Working principle is based on 4 clocks namely Clock, trigger. Start Of Signal (SOS), End Of Signal (EOS). Dark output increases if the start pulse period or the start pulse high period is lengthened. The integration time equals time equals the high period of ST plus 48 CLK cycles. The shift register starts operation at the rising edge of CLK immediately after ST goes low. The integration time can be changed by changing the ratio of the high and low periods of ST. If the first Trig pulse after ST goes low is counted as the FIRST PULSE, the video signal is acquired at the rising edge of the 89th Trig pulse. When reading from 1024 pixels, the video signal is output from 513 to 1536 channels. C. Lattice XP2 Brevia Development kit The LatticeXP2 Brevia Development Kit is an easy-touse, low-cost platform for evaluating and designing with LatticeXP2 FPGAs. The kit offers free design tools, reference designs, a small form-factor assessment board, and a parallel programming cable. The evaluation board features a LFXP2-5E- 6TN144C FPGA device, 2 Mbit SPI Flash, 1 Mbit SRAM memory, expansion headers, several LEDs, and user switches. B. Channel SHA mode This mode operates the same way as 3-Channel SHA mode[3], except that the multiplexer relics stationary. Only the channel specified in the MUX Configuration Register is processed. Timing for this mode is shown in Fig. 5. CDSCLK1 should be grounded in this mode of operation
Reading an Image using CMOS Linear Image Sensor 3 IV. Experimental Result Based on clock signal, Start Of Scan and End Of Scan (EOS) is controlled by trigger.
4 S.R.Shinthu et al. Fig.14 shows individual pixel value in zero light that is no analog signal in light off condition For Analog to Digital converter (ADC) two clocks are required namely CDSCLK2 and ADCCLK1. The operation of ADC is based on single channel SHA. Based on CDSCLK2 and ADCCLK1 the analog signal from Hamamatsu image sensor enters the Analog to Digital Converter. Once the End Of Signal (EOS) is reached then the signal starts to enter in ADC. Here the analog values are converted into digital signal and these digital values can be used for kit implementation. Fig 16 shows analog signal with ADC and CDS clocks in full light condition. Fig 14 shows individual pixel value in zero light that is no analog signal in light off condition Fig 17 shows analog signal with ADC and CDS clocks in a compressed form in full light condition
Reading an Image using CMOS Linear Image Sensor 5 Fig 18 shows analog signal with ADC and CDS clocks in less light Fig 21 shows analog signal with ADC and CDS clocks in a highly compressed form in full light condition V. Conclusion Hamamatsu captures an image and the pixels present are charged. The analog output from Hamamatsu is converted into Digital Signal using Analog to Digital Converter (ADC). These values are implemented in Lattice XP2 Brevia development kit. References Fig 19 shows analog signal with ADC and CDS clocks in no light [1] A.N. Selivanov and M.G. Fedotov Digital television camera for real-time image recording, Proceedings of the IASTED International Conference ACIT2002, ACTA Press, Anaheim-CalgaryZurich, 2002, p.14. [2] Datasheet CMOS linear image sensor S11108. [3] Datasheet AD9826.