Code No: A R09 Set No. 2

Similar documents
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad ELECTRICAL AND ELECTRONICS ENGINEERING

St. MARTIN S ENGINEERING COLLEGE

R13 SET - 1 '' ''' '' ' '''' Code No: RT21053

R13. II B. Tech I Semester Regular Examinations, Jan DIGITAL LOGIC DESIGN (Com. to CSE, IT) PART-A

1. Convert the decimal number to binary, octal, and hexadecimal.

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).

Find the equivalent decimal value for the given value Other number system to decimal ( Sample)

Department of Computer Science and Engineering Question Bank- Even Semester:

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

EXPERIMENT: 1. Graphic Symbol: OR: The output of OR gate is true when one of the inputs A and B or both the inputs are true.

PURBANCHAL UNIVERSITY

THE KENYA POLYTECHNIC

Department of CSIT. Class: B.SC Semester: II Year: 2013 Paper Title: Introduction to logics of Computer Max Marks: 30

Course Plan. Course Articulation Matrix: Mapping of Course Outcomes (COs) with Program Outcomes (POs) PSO-1 PSO-2

MODU LE DAY. Class-A, B, AB and C amplifiers - basic concepts, power, efficiency Basic concepts of Feedback and Oscillation. Day 1


TIME SCHEDULE. MODULE TOPICS PERIODS 1 Number system & Boolean algebra 17 Test I 1 2 Logic families &Combinational logic

LESSON PLAN. Sub Code: EE2255 Sub Name: DIGITAL LOGIC CIRCUITS Unit: I Branch: EEE Semester: IV

MODEL QUESTIONS WITH ANSWERS THIRD SEMESTER B.TECH DEGREE EXAMINATION DECEMBER CS 203: Switching Theory and Logic Design. Time: 3 Hrs Marks: 100


Bachelor Level/ First Year/ Second Semester/ Science Full Marks: 60 Computer Science and Information Technology (CSc. 151) Pass Marks: 24

A.R. ENGINEERING COLLEGE, VILLUPURAM ECE DEPARTMENT

The word digital implies information in computers is represented by variables that take a limited number of discrete values.

MODULE 3. Combinational & Sequential logic

Combinational Logic Design

Tribhuvan University Institute of Science and Technology Bachelor of Science in Computer Science and Information Technology

Question Bank. Unit 1. Digital Principles, Digital Logic

BHARATHIDASAN ENGINEERING COLLEGE, NATTRAMPALLI DEPARTMENT OF ECE

Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,

Subject : EE6301 DIGITAL LOGIC CIRCUITS

1. a) For the circuit shown in figure 1.1, draw a truth table showing the output Q for all combinations of inputs A, B and C. [4] Figure 1.

ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.

Using minterms, m-notation / decimal notation Sum = Cout = Using maxterms, M-notation Sum = Cout =

Final Examination (Open Katz, Calculators OK, 3 hours)

1. True/False Questions (10 x 1p each = 10p) (a) I forgot to write down my name and student ID number.

UNIT 1: DIGITAL LOGICAL CIRCUITS What is Digital Computer? OR Explain the block diagram of digital computers.

Computer Architecture and Organization

Digital Principles and Design

1.b. Realize a 5-input NOR function using 2-input NOR gates only.

a) (A+B) (C+D) b) AB+CD c) AC+BD d) (A+D) (B+C)

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET

EE292: Fundamentals of ECE

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics

Analogue Versus Digital [5 M]

Multi-Level Gate Circuits. Chapter 7 Multi-Level Gate Circuits NAND and NOR Gates. Some Terminologies (Cont.) Some Terminologies

Experiment (6) 2- to 4 Decoder. Figure 8.1 Block Diagram of 2-to-4 Decoder 0 X X

2 Marks Q&A. Digital Electronics. K. Michael Mahesh M.E.,MIET. Asst. Prof/ECE Dept.

EECS 270 Final Exam Spring 2012

Laboratory Objectives and outcomes for Digital Design Lab

Section 6.8 Synthesis of Sequential Logic Page 1 of 8

DHANALAKSHMI SRINIVASAN INSTITUTE OF RESEARCH AND TECHNOLOGY CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN. I Year/ II Sem PART-A TWO MARKS UNIT-I

211: Computer Architecture Summer 2016

CS 151 Final. Instructions: Student ID. (Last Name) (First Name) Signature

Prepared By Verified By Approved By Mr M.Kumar Mrs R.Punithavathi Dr. V.Parthasarathy Asst. Professor / IT HOD / IT Principal

CSE221- Logic Design, Spring 2003

Final Exam review: chapter 4 and 5. Supplement 3 and 4

TYPICAL QUESTIONS & ANSWERS

Microprocessor Design

4.S-[F] SU-02 June All Syllabus Science Faculty B.Sc. II Yr. Instrumentation Practice [Sem.III & IV] S.Lot

DIGITAL PRINCIPLES AND SYSTEM DESIGN

Semester III. Subject Name: Digital Electronics. Subject Code: 09CT0301. Diploma Branches in which this subject is offered: Computer Engineering

WINTER 15 EXAMINATION Model Answer

ME 515 Mechatronics. Introduction to Digital Electronics

DIGITAL ELECTRONICS MCQs

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

UNIVERSITI TEKNOLOGI MALAYSIA

Department of Electrical Engineering University of Hail Ha il - Saudi Arabia

Quiz #4 Thursday, April 25, 2002, 5:30-6:45 PM

UNIVERSITY OF MASSACHUSSETS LOWELL Department of Electrical & Computer Engineering Course Syllabus for Logic Design Fall 2013

Digital Circuits. Electrical & Computer Engineering Department (ECED) Course Notes ECED2200. ECED2200 Digital Circuits Notes 2012 Dalhousie University

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

problem maximum score 1 28pts 2 10pts 3 10pts 4 15pts 5 14pts 6 12pts 7 11pts total 100pts

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours

North Shore Community College

Chapter 5 Sequential Circuits


Sequential Logic. Analysis and Synthesis. Joseph Cavahagh Santa Clara University. r & Francis. TaylonSi Francis Group. , Boca.Raton London New York \

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)

AM AM AM AM PM PM PM

EECS 270 Midterm 2 Exam Closed book portion Fall 2014

WINTER 14 EXAMINATION

NORTHWESTERN UNIVERSITY TECHNOLOGICAL INSTITUTE

LORDS INSTITUTE OF ENGINEERING & TECHNOLOGY

Decade Counters Mod-5 counter: Decade Counter:

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

NUMBER SYSTEMS AND CODES...

Where Are We Now? e.g., ADD $S0 $S1 $S2?? Computed by digital circuit. CSCI 402: Computer Architectures. Some basics of Logic Design (Appendix B)

Electrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York

VU Mobile Powered by S NO Group

S.K.P. Engineering College, Tiruvannamalai UNIT I

RS flip-flop using NOR gate

Combinational / Sequential Logic

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER

Introduction to Digital Electronics

SEMESTER ONE EXAMINATIONS 2002

CHAPTER 4: Logic Circuits

Transcription:

Code No: A109210503 R09 Set No. 2 II B.Tech I Semester Examinations,November 2010 DIGITAL LOGIC DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks 1. Explain about Read only memory in detail? [15] 2. Explain about the following: (a) Merger diagrams (b) Flow and implication tables. [15] 3. Explain the differences among a Truth table, a state table, a characteristic table, and an Excitation table. Also explain the difference among a Boolean equation, a state Equation, a characteristic equation, and a Flip-flop input equation. [15] 4. Define BCD Counter and Draw its State table for BCD Counter? [15] 5. (a) Simplify to a sum of 3 terms: A C D +AC +BCD + A CD + A BC + AB C (b) Given AB + AB = C, Show that AC + A C = B (c) Factor to obtain a Product of Sums(simplify where possible) A C D +ABD + A CD +B D. [5+5+5] 6. (a) Design a 2 bit comparator using gates. (b) Use an 8-to-1 MUX to design the following combinational logic circuit There are four adjacent parking slots in the XYZ Inc executive parking area. Each slot is equipped with a special sensor whose output is asserted high when a car is occupying the slot. Design a decoding system that will signal the existence of two or more adjacent vacant slots. [10+5] 7. (a) A combinational circuit has 4 inputs(a,b,c,d) and three outputs(x,y,z)xyz represents a binary number whose value equals the number of 1 s at the input: i. Find the minterm expansion for the X,Y,Z ii. Find the maxterm expansion for the Y and Z (b) A combinational circuit has four inputs (A,B,C,D), which represent a binarycoded-decimal digit. The circuit has two groups of four outputs - S,T,U,V(MSB digit) and W,X,Y,Z.(LSB digit)each group represents a BCD digit.the output digits represent a decimal number which is five times the input number. Write down the minimum expression for all the outputs. [15] 8. (a) Perform the subtraction with the following unsigned binary numbers by taking the 2 s complement of the subtrahend: 1

Code No: A109210503 R09 Set No. 2 i. 100-110000 ii. 11010-1101. (b) Construct a table for 4-3 -2-1 weighted code and write 9154 using this code (c) Perform arithmetic operation indicated below.follow signed bit notation: i. 001110 + 110010 ii. 101011-100110. (d) Explain the importance of gray code. [4+4+4+3] 2

Code No: A109210503 R09 Set No. 4 II B.Tech I Semester Examinations,November 2010 DIGITAL LOGIC DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks 1. Explain about the following: (a) Hazards in sequential circuits (b) Four row flow table (c) Maximal compatibilities. [15] 2. Explain about the Following (a) Serial addition in 4-bit shift register (b) BCD Ripple Counter (c) Universal Shift Register. [15] 3. Explain about (a) ROM (b) FPGA. [7+8] 4. (a) Design a circuit with three inputs(a,b,c) and two outputs(x,y) where the outputs are the binary count of the number of ON (HIGH) inputs (b) Design a circuit with four inputs and one output where the output is 1 if the input is divisible by 3 or 7. [7+8] 5. Starting from state a, and the input sequences 01110010011,determine the output Sequence for (a) The state table below and (b) Also the reduced state table to the same state below and show that the same output sequence is obtained for both. [15] Present state Next state output X=0 X=1 X=0 X=1 a f g 0 0 b d c 0 0 c f e 0 0 d g a 1 0 e d c 0 0 f f b 1 1 g g h 0 1 h g a 1 0 3

Code No: A109210503 R09 Set No. 4 6. Convert the following numbers: (a) 10101100111.0101 to Base 10 (b) (153.513) 10 = ( ) 8 (c) Find (3250-72532) 10 using 10 s complement (d) Divide 01100100 by 00011001 (e) Given that (292)10 =(1204) b determine b [3+3+3+3+3] 7. (a) Verify that NAND and NOR operations are Commutative but not Associative. (b) A certain 4 input gate called LEMON gate realizes the switching function LEMON(A,B,C,D) = BC(A+D) Assuming that the input variables are available in both primed and unprimed form: i. show a realization of the function f(w,x,y,z)= (0,1,6,9,10,11,14,15) with only three LEMON gates and one OR gate. ii. Can all switching functions be realized with LEMON/OR logic. [5+5+5] 8. (a) Simplify to a sum of 3 terms: A B C +ABD+A C +A CD +AC D + AB C (b) As part of an aircraft s functional monitoring system, a circuit is required to indicate the status of the landing gears prior to landing. Green LED display turns on if all three gears are properly extended when the gear down switch has been activated in preparation for landing. Red LED display turns on if any of the gears fail to extend properly prior to landing. When a landing gear is extended, its sensor produces a LOW voltage. When a landing gear is retracted, its sensor produces a HIGH voltage. Implement a circuit to meet this requirement. (c) In a certain chemical processing plant, a liquid chemical is used in a manufacturing process. The chemical is stored in three different tanks. A level sensor in each tank produces a HIGH voltage when the level of chemical in the tank drops below a specified point. Design a circuit that monitors the chemical level in each tank and indicates when the level in any two of the tanks drops below the specified point. [5+5+5] 4

Code No: A109210503 R09 Set No. 1 II B.Tech I Semester Examinations,November 2010 DIGITAL LOGIC DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks 1. (a) Define the following i. Preset ii. Clear iii. Race condition iv. Race around condition (b) Draw the schematic circuit of T-Flip-flop. Give its truth table. Justify the entries in the truth table? [7+8] 2. (a) Implement Half adder using 4 NAND gates (b) Implement full subtractor using NAND gates only. [5+10] 3. Explain about Sequential Programming Devices in detail? [15] 4. (a) Find the possible terms which could be added to the expression using the consensus theorem.then reduce to a minimum SOP A C D + BCD + AB C +A BC (b) In a board of directors meeting 4 resolutions A,B,C,D are up to a vote. The vote must be governed by the following rules: i. Those who vote for resolution B must also vote for resolution C. ii. It is possible to vote for both resolutions A& C, only if a vote for either B or D is also cast. iii. Those who vote for either resolution C or D or vote against resolution A must vote for resolution B. Each member of the board has 4 switches A,B,C,D which he presses or releases, depending on whether he is in favor of or against the resolution under the consideration. The switches of each member are the inputs to a circuit associated with that member. Design such a circuit with as few gates as possible. [5+10] 5. (a) What is the gray code equivalent of the Hex Number 3A7 (b) Find the biquinary of number code for the decimal numbers from 0 to 9 (c) Find 9 s complement (25.639) 10 (d) Find (72532-03250) using 9 s complement. [4+3+4+4] 6. Compare the merits and demerits of ripple and Synchronous Counters? [15] 7. Explain about the Derivation of Latch circuit from Transition table? [15] 5

Code No: A109210503 R09 Set No. 1 8. (a) Design a BCD to Excess-3 code converter using minimum number of NAND gates (b) Design a BCD to Gray code converter using 8:1 multiplexers. [10+5] 6

Code No: A109210503 R09 Set No. 3 II B.Tech I Semester Examinations,November 2010 DIGITAL LOGIC DESIGN Computer Science And Engineering Time: 3 hours Max Marks: 75 Answer any FIVE Questions All Questions carry equal marks 1. (a) Design a circuit with four inputs and one output where the output is 1 if the input is divisible by 3 or 7. (b) A safe has 5 locks:v,w,x,y,all of which must be unlocked for the safe to open.the keys to the locks are distributed among five executives in the following manner: Mr.A has keys for locks v& x Mr.B has keys for locks v& y Mr.C has keys for locks w& y Mr.D has keys for locks x& z Mr.E has keys for locks v& z i. Determine the minimal no. of executives required to open the safe. ii. Find all the combinations of executives that can open the safe, write an expression f(a,b,c,d,e) which specifies when the safe can be opened as a function of which executives are present iii. Who is the essential executive without whom the safe cannot be opened. [7+8] 2. Explain about 4-bit binary Ripple Counters? [15] 3. Explain about the following: (a) latch excitation table (b) Merging of flow tables. [15] 4. Explain about PLA in Detail? [15] 5. Design a Excess-3 to BCD code converter using minimum number of NAND gates. [15] 6. Reduce the number of states in the following state table and tabulate the reduce state Table [15] 7

Code No: A109210503 R09 Set No. 3 Present state Next state output X=0 X=1 X=0 X=1 a f g 0 0 b d c 0 0 c f e 0 0 d g a 1 0 e d c 0 0 f f b 1 1 g g h 0 1 h g a 1 0 7. (a) Show the weights of three different 4 bit self complementing codes whose only negative weight is - 4 and write down number system from 0 to 9 (b) Decimal system became popular because we have 10 fingers. A rich person on earth has decided to distribute Rs.one lakh equally to the following persons from various planets. Find out the amount each one of them will get in their respective currencies: A from planet VENUS possessing 8 fingers B from planet MARS possessing 6 fingers C from planet JUPITER possessing 14 fingers D from planet MOON possessing 16 fingers [7+8] 8. A Communication system is designed to transmit just two code words A(x1,x2,x3,x4) = 0010 and B(x1,x2,x3,x4)=1101.However, due to noise in the system, the received word can have as many as two errors. Design a combinational circuit such that output f1will be equal to 1 if the received word is A; output f2 will be equal to 1 if the received word is B and output f3 will be equal to 1 if the word received none of these two. [15] 8