GV7704. Quad HD-VLC Receiver. Key Features. Applications. Description

Quad HD-VLC Receiver Key Features Quad channel serial digital video receiver for HD video surveillance and HDcctv applications Dual rate operation: 270Mb/s and 1.485Gb/s Supports HDcctv 1.0, HD-SDI (ST 292) and SD-SDI (ST 259)* Four independent receiver channels with high performance cable equalization, with support for 50/75Ω coaxial and twisted pair cable transmission Integrated High Definition Visually Lossless CODEC (HD-VLC ) for extended cable reach: 550m over Belden 543945 CCTV coaxial cable 150m over Cat-5e/6 UTP cable Serial digital loop-though output per channel Integrated audio de-embedder for the extraction of up to 4 channels of I 2 S serial digital audio at 32kHz, 44.1kHz and 48kHz sample rates, per video channel Supports both 720p and 1080p HD formats: 1080p 25/29.97/30fps 720p 25/29.97/30/50/59.94/60fps Four 8/10-bit BT.1120 compliant output video interfaces, with embedded TRS and external HVF timing outputs Automatic independent detection of HD-SDI and HD-VLC video input data streams per channel Downstream ancillary data detection and extraction Automatic HDcctv Stream ID detection 4-wire Gennum Serial Peripheral Interface (GSPI 2.0) for external host command and control JTAG test interface 1.2V core voltage power supplies 1.8V digital I/O power supply Small footprint 169-BGA (11mm x 11mm) Low power operation, typically 810mW Wide operating temperature range: -20 C to + 85 C Pb-free and RoHS compliant Applications Digital video recorders (DVR) Video servers Video multiplexers Video PC capture cards HDcctv peripherals Coaxial Cable Application HD Sensor HD-VLC Camera Image Signal Processor UTP Cable Application HD-VLC Camera GV7700 Transmitter Power Sink RS422 Description GV7700 Transmitter 550m Belden 543945 Coaxial Cable HD-SDI or HD-VLC Cameras 150m Cat-5e/6 Cable HD at 270Mb/s HD at 270Mb/s Power Source IN1 IN2 RS422 IN3 IN4 HD-VLC DVR Quad Receiver HD-VLC DVR Quad Receiver HD Video CODEC HDD Storage HDMI Output The is a quad channel serial digital video receiver for High Definition component video. With integrated high performance cable equalizer technology, the is capable of receiving HD video at 270Mb/s and 1.485Gb/s over 75Ω coaxial cable, or differentially over a 100Ω twisted pair cable. The integrates the High Definition Visually Lossless CODEC (HD-VLC ) technology, which has been developed specifically to reduce the transmission data rate of HD video over both coaxial and unshielded twisted pair (UTP) cable. This is achieved by encoding the HD video, normally transmitted at a serial data rate of 1.485Gb/s, to the same rate as Standard Definition (SD) video, at 270Mb/s serial data rate. At 270Mb/s, the effect of cable loss is greatly reduced, resulting in much longer cable transmission. For 75Ω coaxial cable, cable reach can be extended up to 3x the normal reach when transmitting encoded HD at 270Mb/s. In typical video over coaxial installations, cable distances of up to 550m are possible. 1 of 52

The can also be configured to receive HD video over UTP cable, such as Cat-5e and Cat-6 cable, when HD-VLC encoded at 270Mb/s. The device supports the reception of both 8-bit and 10-bit per pixel YCbCr 4:2:2 BT.1120 component digital video. A single 10-bit wide parallel digital video output bus per channel is provided, with associated pixel clock and timing signal outputs. The supports direct interfacing of HD video formats conforming to ITU-R BT.709 and BT.1120-6 for 1125-line formats, and SMPTE ST 296 for 750-line formats. The supports the extraction of ancillary data from the horizontal blanking of the input video data stream. Ancillary data packets can be accessed via the GSPI, allowing downstream communication from the video source to sink device. The recognizes data packets formatted in compliance with the HDcctv 2.0 communications protocol. The features an audio de-embedding core, which provides the extraction of up to 4 channels of I 2 S serial digital audio from the ancillary data space of the input video data stream. The audio de-embedding core supports 32kHz, 44.1kHz, and 48kHz sample rates. Packaged in a space saving 169 ball 11 x 11mm BGA, the is ideal for high density, multi-channel video recorder architectures. Typically requiring only 810mW of power, the device does not require any special heat sinking or air flow, reducing the over cost of HD DVR designs. *Frame structure with encoded HD only. Does not support SD/D1 video. Functional Block Diagram TDO TCK TMS TDI TRST RESET SDOUT SCLK CS SDIN RBIAS Common GSPI JTAG Digital Control Channel 3 CH3_SDO CH3_SDO CH3_SDI CH3_SDI EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format CH3_PCLK CH3_DOUT[9:0] CH3_AOUT_1_2 CH3_AOUT_3_4 CH3_ACLK CH3_WCLK Channel 2 CH2_SDO CH2_SDO CH2_SDI CH2_SDI EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format CH2_PCLK CH2_DOUT[9:0] CH2_AOUT_1_2 CH2_AOUT_3_4 CH2_ACLK CH2_WCLK Channel 1 CH1_SDO CH1_SDO CH1_SDI CH1_SDI EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format CH1_PCLK CH1_DOUT[9:0] CH1_AOUT_1_2 CH1_AOUT_3_4 CH1_ACLK CH1_WCLK Channel 0 CH0_SDO CH0_SDO CH0_SDI CH0_SDI EQ CDR S2P Format Detect Audio/ Ancilliary Extraction HDVLC Decoder Output Format CH0_PCLK CH0_DOUT[9:0] CH0_AOUT_1_2 CH0_AOUT_3_4 CH0_ACLK CH0_WCLK Functional Block Diagram 2 of 52

Revision History Version ECO PCN Date Description 3 027518 September 2015 2 027065 July 2015 1 024435 March 2015 Updated to Preliminary Data Sheet. Updated Section 2.1, Section 2.2, Section 2.3, Section 4., and Figure 6-2. Added Figure 6-3. Various updates throughout document. Updated cable reach values. Updated Table 2-2 and Table 2-3. Updated Section 2.2, Section 2.3, Section 5., and Figure 6-1. Added Section 3., Section 4.10 and Section 4.11. Various updates throughout document. 0 021239 October 2014 New Document Contents 1. Pin Out...5 1.1 Pin Assignment...5 1.2 Pin Descriptions...6 2. Electrical Characteristics... 13 2.1 Absolute Maximum Ratings... 13 2.2 DC Electrical Characteristics... 14 2.3 AC Electrical Characteristics... 15 3. Input/Output Circuits... 16 4. Detailed Description... 17 4.1 Functional Overview... 17 4.2 Serial Digital Inputs... 17 4.2.1 Input Termination Selection... 18 4.2.2 Automatic Signal Rate Detection... 18 4.3 Serial Digital Outputs... 18 4.3.1 Output Signal Interface Levels... 19 4.3.2 Serial Data Output Signal...19 4.4 Video Functionality... 19 4.4.1 Descrambling and Word Alignment... 19 4.4.2 HD-VLC Decoding... 20 4.4.3 High Definition Output Video Format... 21 4.5 Parallel Video Data Outputs CHn_DOUT_[9:0]... 24 4.6 Stream ID Packet Extraction... 25 4.7 Ancillary Data Extraction... 26 4.8 Audio Extraction... 28 4.8.1 Serial I2S Audio Data Format... 29 4.8.2 Audio Mute... 29 4.9 GSPI Host Interface... 30 3 of 52

4.9.1 CS Pin... 30 4.9.2 SDIN Pin... 30 4.9.3 SDOUT Pin... 30 4.9.4 SCLK Pin... 31 4.9.5 Command Word Description... 31 4.9.6 Data Word Description... 32 4.9.7 GSPI Transaction Timing...33 4.9.8 Single Read/Write Access... 34 4.9.9 Auto-increment Read/Write Access... 34 4.10 JTAG... 35 4.11 Power Supply and Reset Timing... 36 5. Register Map... 37 6. Application Information... 47 6.1 Typical Application Circuit... 47 7. Packaging Information... 49 7.1 Package Dimensions... 49 7.2 Recommended PCB Footprint... 50 7.3 Marking Diagram... 50 7.4 Solder Reflow Profile... 51 7.5 Packaging Data... 51 7.6 Ordering Information... 51 4 of 52

1. Pin Out 1.1 Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 A CH3_SDI CH3_SDI CH3_SDO TCK CH3_WCLK CH2_WCLK CH3_HOUT CH3_PCLK CH3_DOUT_5 CH3_DOUT_3 CH3_DOUT_1 CH3_DOUT_0 B VDD18_A CH3_SDO TMS CH3_ACLK CH2_ACLK CH3_VOUT CH3_DOUT_8 CH3_DOUT_6 CH3_DOUT_4 CH3_DOUT_2 CH2_VOUT C N/C N/C VDD18_A TDI TDO CH3_AOUT_1_2 CH2_AOUT_1_2 CH3_FOUT CH3_DOUT_9 CH3_DOUT_7 CH2_HOUT CH2_FOUT CH2_PCLK D CH2_SDI CH2_SDI TRST EXT_FW CH3_AOUT_3_4 CH2_AOUT_3_4 CH2_DOUT_9 CH2_DOUT_8 CH2_DOUT_7 E VDD18_A VDD12_A RSVD VDD18_D VDD18_D CH2_DOUT_6 CH2_DOUT_5 CH2_DOUT_4 F CH2_SDO CH2_SDO VDD18_A VDD12_A VDD12_D VDD12_D VDD12_D VDD18_D CH2_DOUT_3 CH2_DOUT_2 CH2_DOUT_1 G VDD18_A VDD12_A VDD12_D VDD12_D VDD12_D VDD18_D CH1_HOUT CH2_DOUT_0 H CH1_SDO CH1_SDO VDD18_A VDD12_A VDD12_D VDD12_D VDD12_D VDD18_D CH1_VOUT CH1_FOUT CH1_PCLK J VDD18_A VDD12_A VDD18_D VDD18_D CH1_DOUT_9 CH1_DOUT_8 CH1_DOUT_7 K CH1_SDI CH1_SDI RESET RSVD CH0_WCLK CH1_WCLK CH1_DOUT_6 CH1_DOUT_5 CH1_DOUT_4 L RBIAS VDD18_A SDIN SDOUT CH0_ACLK CH1_ACLK CH0_DOUT_2 CH0_DOUT_5 CH0_DOUT_8 CH1_DOUT_3 CH1_DOUT_2 CH1_DOUT_1 M VDD18_A CH0_SDO CS CH0_AOUT_1_2 CH1_AOUT_1_2 CH0_DOUT_1 CH0_DOUT_4 CH0_DOUT_7 CH0_DOUT_9 CH0_VOUT CH1_DOUT_0 N CH0_SDI CH0_SDI CH0_SDO SCLK CH0_AOUT_3_4 CH1_AOUT_3_4 CH0_DOUT_0 CH0_DOUT_3 CH0_DOUT_6 CH0_PCLK CH0_HOUT CH0_FOUT Figure 1-1: Pin Out 5 of 52

1.2 Pin Descriptions Table 1-1: Pin Descriptions Pin Number Name Type Description Analog High-Speed Inputs N1, N2 CH0_SDI, CH0_SDI K1, K2 CH1_SDI, CH1_SDI D1, D2 CH2_SDI, CH2_SDI A1, A2 CH3_SDI, CH3_SDI Analog High-Speed Outputs N4, M4 CH0_SDO, CH0_SDO H1, H2 CH1_SDO, CH1_SDO F1, F2 CH2_SDO, CH2_SDO A4, B4 CH3_SDO, CH3_SDO Analog Bias Analog High-Speed Input Analog High-Speed Input Analog High-Speed Input Analog High-Speed Input Analog High-Speed Output Analog High-Speed Output Analog High-Speed Output Analog High-Speed Output Differential high-speed data input 0. (75Ω nominal input impedance) Differential high-speed data input 1. (75Ω nominal input impedance) Differential high-speed data input 2. (75Ω nominal input impedance) Differential high-speed data input 3. (75Ω nominal input impedance) Differential high-speed test output 0. (75Ω nominal output impedance) Differential high-speed test output 1. (75Ω nominal output impedance) Differential high-speed test output 2. (75Ω nominal output impedance) Differential high-speed test output 3. (75Ω nominal output impedance) L1 RBIAS Input/Output External 10kΩ resistor for bias reference. Connect the resistor to ground. Digital Video Outputs Parallel digital video output. L8, L9, L10, M8, M9, M10, M11, N8, N9, N10 CH0_DOUT_[9:0] Output lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. 6 of 52

Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description N12 CH0_HOUT Output M12 CH0_VOUT Output N13 CH0_FOUT Output N11 CH0_PCLK Output Horizontal blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Vertical blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Pixel clock output (148.5MHz or 148.5/1.001 MHz). lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Parallel digital video output. J[11:13], K[11:13], L[11:13], M13 CH1_DOUT_[9:0] Output lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. G12 CH1_HOUT Output H11 CH1_VOUT Output H12 CH1_FOUT Output Horizontal blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Vertical blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. 7 of 52

Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description H13 CH1_PCLK Output Pixel clock output (148.5MHz or 148.5/1.001 MHz). lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Parallel digital video output. D[11:13], E[11:13], F[11:13], G13 CH2_DOUT_[9:0] Output lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. C11 CH2_HOUT Output B13 CH2_VOUT Output C12 CH2_FOUT Output C13 CH2_PCLK Output Horizontal blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Vertical blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Pixel clock output (148.5MHz or 148.5/1.001 MHz). lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Parallel digital video output. A[10:13], B[9:12], C9, C10 CH3_DOUT_[9:0] Output lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. A8 CH3_HOUT Output Horizontal blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. 8 of 52

Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description B8 CH3_VOUT Output C8 CH3_FOUT Output A9 CH3_PCLK Output Vertical blanking output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Frame indication output. lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Pixel clock output (148.5MHz or 148.5/1.001 MHz). lane (DISABLE_VIDEO_LANE). Drive strength may be adjusted using register PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL_REG. Digital Audio Outputs K6 CH0_WCLK Output L6 CH0_ACLK Output M6 CH0_AOUT_1_2 Output N6 CH0_AOUT_3_4 Output K7 CH1_WCLK Output L7 CH1_ACLK Output Channel 0 word clock (32kHz, 44.1kHz, or 48kHz). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 0 I 2 S Audio clock (64 x word clock). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 0 I 2 S Audio output 1 & 2. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 0 I 2 S Audio output 3 & 4. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 1 word clock (32kHz, 44.1kHz, or 48kHz). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 1 I 2 S Audio clock (64 x word clock). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). 9 of 52

Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description M7 CH1_AOUT_1_2 Output N7 CH1_AOUT_3_4 Output A7 CH2_WCLK Output B7 CH2_ACLK Output C7 CH2_AOUT_1_2 Output D7 CH2_AOUT_3_4 Output A6 CH3_WCLK Output B6 CH3_ACLK Output C6 CH3_AOUT_1_2 Output D6 CH3_AOUT_3_4 Output Channel 1 I 2 S Audio output 1 & 2. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 1 I 2 S Audio output 3 & 4. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 word clock (32kHz, 44.1kHz, or 48kHz). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 I 2 S Audio clock (64 x word clock). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 I 2 S Audio output 1 & 2. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 2 I 2 S Audio output 3 & 4. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 word clock (32kHz, 44.1kHz, or 48kHz). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 I 2 S Audio clock (64 x word clock). lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 I 2 S Audio output 1 & 2. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). Channel 3 I 2 S Audio output 3 & 4. lane (DISABLE_VIDEO_LANE) or user disables audio (DISABLE_AUDIO). 10 of 52

Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description JTAG Interface B5 TMS Input C4 TDI Input C5 TDO Output A5 TCK Input D4 TRST Input Dedicated JTAG pin Test Mode Select. This pin is used to control the operation of the JTAG test. Schmitt Trigger Input with Pull-Up. If JTAG is not used this pin may be left floating. Dedicated JTAG pin Test data input. This pin is used to shift JTAG test data into the device. Schmitt Trigger Input with Pull-Up. If JTAG is not used this pin may be left floating. Dedicated JTAG pin Test data output. This pin is used to shift results from the device. Dedicated JTAG pin Serial data clock signal. This pin is the JTAG clock. Schmitt Trigger Input. If JTAG is not used this pin must be pulled LOW. Dedicated JTAG pin Test Reset. When set LOW, the JTAG logic will be reset. Schmitt Trigger Input with Pull-Up. If JTAG is not used this pin must be pulled LOW. General I/O and Host Interface K4 RESET Input Digital active low reset input. Used to reset the internal. operating conditions to default settings. Schmitt Trigger Input. M5 CS Input Used to initiate and terminate GSPI commands. Active-low. L4 SDIN Input Serial input data, clocked in on the rising edge of SCLK. L5 SDOUT Output N5 SCLK Input D5 EXT_FW Input Serial data output. Only used in GSPI mode. Clocked out on the falling edge of SCLK. Drive strength may be adjusted using register GSPI_SDOUT_DRV_STRENGTH_SEL_REG. Serial clock. The rising edge is used to latch the SDIN bits and the falling edge to drive SDOUT bits. External firmware loading control: When HIGH, indicates to the that the host will download firmware to the. When LOW, indicates to the to boot with internal firmware. 11 of 52

Table 1-1: Pin Descriptions (Continued) Pin Number Name Type Description Supply Pins B3, C3, E3, F3, G3, H3, J3, L2, M3 E7, E8, F9, G9, H9, J7, J8 E4, F4, G4, H4, J4 F6, F7, F8, G6, G7, G8, H6, H7, H8 A3, B1, B2, D3, D8, D9, D10, E1, E2, E6, E9, E10, F5, F10, G1, G2, G5, G10, G11, H5, H10, J1, J2, J5, J6, J9, J10, K3, K8, K9, K10, L3, M1, M2, N3 VDD18_A Power Analog 1.8V Power Supply. Connect to 1.8V. VDD18_D Power Digital 1.8V Power Supply. Connect to 1.8V. VDD12_A Power Analog 1.2V Power Supply. Connect to 1.2V. VDD12_D Power Digital 1.2V Power Supply. Connect to 1.2V. Power Connect to. C1, C2 N/C Do not Connect. E5, K5 RSVD Connect to. 12 of 52

2. Electrical Characteristics 2.1 Absolute Maximum Ratings Table 2-1: Absolute Maximum Ratings Parameter Value 1.8V I/O and Analog Supply Voltage 0.5V to +2.5V DC 1.2V Analog and Core Supply Voltage 0.3V to +1.5V DC DC Input Voltage, VIN (Not to exceed 2.5V) DC Output Voltage, VOUT (Not to exceed 2.5V) Input ESD Voltage (HBM) Input ESD Voltage (CDM) 0.5V to (VDD18 + 0.5V) 0.5V to (VDD18 + 0.5V) 2kV 500V Storage Temperature Range (T S ) -50 C to 125 C Operating Temperature Range (T A ) -20 C to 85 C Solder Reflow Temperature (4s) 260 C Note: Absolute Maximum Ratings are those values beyond which damage may occur. Functional operation outside of the ranges shown in the AC and DC Electrical Characteristics is not guaranteed. 13 of 52

2.2 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics T A = -20 C to +85 C unless otherwise stated Parameter Symbol Conditions Min Typ Max Units Notes +1.2V Supply Current I 1V2 270Mb/s 172 ma 1.485Gb/s 250 ma +1.8V Supply Current I 1V8 270Mb/s 440 ma 1.485Gb/s 456 ma +1.8V Power Supply Range VDD18 At the device pin (nominal ±5%) 1.71 1.8 1.89 V +1.2V Power Supply Range VDD12 At the device pin (nominal ±5%) 1.14 1.2 1.26 V External RBIAS Resistor 9.9 10 10.1 kω Power Supply Noise Mask +1.2V Power Supply Noise Mask +1.8V 0-200kHz 100 mv pp 1 200kHz to 1MHz 100 mv pp 1 >1MHz 100 mv pp 1 0 to 200kHz 10 mv pp 1 200kHz to 1MHz 30 mv pp 1 >1MHz 100 mv pp 1 270Mb/s, All Cable Drivers Enabled 950 1030 mw Total Power Consumption P total 270Mb/s, All Cable Drivers Disabled 1.485Gb/s, All Cable Drivers Enabled 810 890 mw 1070 1160 mw 1.485Gb/s, All Cable Drivers Disabled 900 990 mw Digital Logic Input V IL Input LOW -0.3 0.63 V V IH Input HIGH 1.17 1.89 V V OL Output LOW 0.45 V 2 Digital Logic Output V OH Output HIGH 1.35 V 2 C LOAD 148.5MHz 12 pf Notes: 1. Using recommended supply decoupling. See Figure 6-1: Typical Application Circuit (Part 1). 2. All digital outputs. 14 of 52

2.3 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics VDD18_A, VDD18_D = 1.8V±5% and T A = -20 C to +85 C unless otherwise stated Parameter Symbol Conditions Min Typ Max Units Notes Input Conditions SDI Input Termination (On Chip) 50 Ω 75 Ω 1MHz to 5MHz 23 db Input Return Loss 5MHz to 1.485GHz 12 db Clock and Data Output Conditions 1.485GHz to 2.25GHz 10 db Output PCLK Clock Frequency f PCLK 148.5 or 148.5/ 1.001 MHz SDO Output Impedance 75Ω single-ended 66 75 84 Ω 100Ω differential 88 100 112 Ω 1MHz to 5MHz 25 db Output Return loss 5MHz to 1.485GHz 6 db 1.485GHz to 2.25GHz 6 db Amplitude 75Ω single-ended 0.36 0.8 0.9 V pp 100Ω differential 0.36 0.8 0.9 V ppd Rise/Fall Time 20% to 80% 130 150 ps Rise/Fall Time Matching 20% to 80% 15 ps Overshoot 10 % Output Total Jitter Data rate = 270Mb/s 0.08 UI pp Data rate = 1.485Gb/s 0.11 UI pp GSPI Digital Control GSPI Read/Write Clock Frequency 55 MHz Reset Time 10 ms Register Access Time 300 ns 15 of 52

3. Input/Output Circuits To Clamp RBIAS Figure 3-1: RBIAS ESD CLAMP 1.8V VDDA18_DRV 50/75Ω Output drive impedance CH[0:3]_SDO_P CH[0:3]_SDO_N Level & de-emphasis control Level & de-emphasis control Figure 3-2: Serial Output Driver ESD CLAMP 50/75Ω Receiver Termination CH[0:3]_SDI_P CH[0:3]_SDI_N Figure 3-3: Serial Input Receiver 16 of 52

4. Detailed Description 4.1 Functional Overview The is a low cost, quad channel HD-VLC receiver of compressed or uncompressed high-definition video. With integrated cable equalizer technology, the is capable of receiving HD video at 270Mb/s and 1.485Gb/s over 75Ω coaxial cable, or differentially over a 100Ω twisted pair cable. The High Definition Visually Lossless CODEC (HD-VLC ) technology is integrated in order to reduce the transmission data rate of HD video over both coaxial and unshielded twisted pair (UTP) cable. This is achieved by encoding the HD-SDI video, normally transmitted at a serial data rate of 1.485Gb/s, to the same rate as Standard Definition (SD-SDI) video, at 270Mb/s serial data rate. This provides extended cable reach for HD video up to 550m over Belden 543945 CCTV coax or 150m over Cat-5e/6 UTP cable. The features an audio de-embedding core, which provides the extraction of up to 4 channels of I 2 S serial digital audio from the ancillary data space of the input video data stream. The audio de-embedding core supports 32kHz, 44.1kHz and 48kHz sample rates. The device supports the reception of both 8-bit and 10-bit per pixel YCbCr 4:2:2 BT.1120 component digital video. A single 10-bit wide parallel digital video output bus per channel is provided, with associated pixel clock and H/V/F timing signal inputs. The supports the extraction of ancillary data from the horizontal blanking of the input video data stream. Ancillary data packets can be accessed via the GSPI, allowing downstream communication from the video source to sink device. The recognizes data packets formatted in compliance with the HDcctv 2.0 communications protocol. The device includes a 4-wire Gennum Serial Peripheral Interface (GSPI 2.0) for external host command and control. All read or write access to the is initiated and terminated by the application host processor. The host interface is provided to allow optional configuration of some of the functions and operating modes of the. 4.2 Serial Digital Inputs The can accept up to four separate channels of serial digital input signals compliant with ITU-R BT.709, and ITU-R BT.1120-6. The four differential input channels are CH0_SDI/CH0_SDI, CH1_SDI/CH1_SDI, CH2_SDI/CH2_SDI and CH3_SDI/CH3_SDI. The integrates adaptive 75Ω coaxial cable equalizer technology which is capable of >50dB for HD-VLC encoded input signals and >35dB for HD uncompressed signals. 17 of 52

Table 4-1: Typical Cable Length Performance Data Rate HD data @ 1.485Gb/s HD-VLC encoded data @ 270Mb/s Belden 543945 CCTV Coaxial 150m 550m Cat-5e/6 UTP N/A 150m The Serial Data Signal may be connected to the input pins of any of the four channels in either a differential or single ended configuration. Only AC coupling of the inputs is supported, as the SDI and SDI inputs are internally biased at approximately 1.8V. Note: The serial data output should be disabled to achieve maximum SDI cable reach. 4.2.1 Input Termination Selection Each of the four channels can be individually configured to work in either 50Ω or 75Ω input termination. Please refer to Register Map for details. 4.2.2 Automatic Signal Rate Detection The device is able to automatically detect the rate of the incoming video signal. There are two data rates which are supported: HD-VLC encoded 270Mb/s (including 270x1.001Mb/s) HD-SDI 1.485Gb/s (including 1.485 1.001Gb/s) The detected rate is indicated in bit SD_HDB in register GEN_VIDEO_CFG_0_REG which specify whether the incoming signal is HD-VLC encoded (270Mb/s) or HD (1.485Gb/s). 4.3 Serial Digital Outputs The s serial data output pins, SDO and SDO, provide complementary outputs, each capable of driving at least 800mV into a 75Ω single-ended load. Compliance with all requirements defined in Section 4.3.1 through Section 4.3.2 is guaranteed when measured across a 75Ω terminated load at the output of 1m of Belden 543945 cable, including the effects of the BNC and coaxial cable connection, except where otherwise stated. Figure 4-1 illustrates this requirement. Coupling Capacitor BNC 1m Belden 543945 75Ω coaxial cable BNC Measuring Device 75Ω resistive load Figure 4-1: BNC and Coaxial Cable Connection 18 of 52

4.3.1 Output Signal Interface Levels The Serial Data Output signals (SDO and SDO pins), of the device meet the amplitude requirements as defined in ITU-R BT.656 and BT.1120 for an unbalanced generator (single-ended). These requirements are met across all ambient temperature and power supply operating conditions described in 2. Electrical Characteristics. 4.3.2 Serial Data Output Signal The device supports two output termination modes (75Ω and 50Ω). The user can program the SDO_50_EN_REG to make that selection, on a per channel basis. Please refer to Register Map for details. 4.3.2.1 Serial Data Output Signal Procedure To enable the serial data output, the user must do a series of GSPI write transactions. The order is very important and must be followed exactly. The sequence is as shown below: 1. Write 03 to the POWER_UP_DRIVER_REG 2. Write 01 to the P2S_CLK_EN_REG 3. Write 01 to the TX_WORD_CLK_ENABLE_REG 4. Write 01 to the CDR_TX_CLK_EN_REG 5. Write 01 to the P2S_RSTB_REG 6. Write 09 to the DATALANE_FIFO_CTRL_REG 7. Write 08 to the DATALANE_FIFO_CTRL_REG Please refer to Section 5. Register Map for detailed register information. Refer to Section 4.9 for GSPI timing requirements. Note: The serial data output should be disabled to achieve maximum SDI cable reach. 4.4 Video Functionality 4.4.1 Descrambling and Word Alignment The performs NRZI to NRZ decoding and data descrambling according to ITU-R BT.1120, and word aligns the data to TRS sync words. The carries out descrambling and word alignment to enable the detection of TRS sync words. When two consecutive valid TRS words (SAV and EAV), with the same bit alignment have been detected, the device word-aligns the data to the TRS ID words. Note: Both 8-bit and 10-bit TRS headers are identified by the device. 19 of 52

4.4.2 HD-VLC Decoding The integrates the High Definition Visually Lossless CODEC (HD-VLC) decoder for extended reach video reception. When used in conjunction with the GV7700 HD-VLC transmitter, HD video transmission can be extended significantly over existing HD serial digital video systems. HD-VLC is based on a simple visually lossless implementation of the Dirac compression tool kit (http://diracvideo.org/) The visually lossless decoder is used to reduce the video bandwidth, using a very low latency mode, from a transmission rate of 1.485Gb/s (HD-SDI) to 270Mb/s (SD-SDI). At a data rate of 270Mb/s, the serial digital encoded HD video can be transmitted over longer runs of coaxial cable. Table 4-2 below shows a comparison of cable distances between HD video transmission at 1.485Gb/s and HD-VLC encoded at 270Mb/s for various common coaxial cable types. Table 4-2: Cable Reach for Various Cable Types (In Metres) Cable Type HD-VLC: 270Mb/s (m) HD-SDI: 1.485Gb/s (m) Belden 1694A / Canare L-4.5CHD 710 230 Belden 543945 550 150 KW-Link SYV 75-5 500 140 Canare L-3C2V 300 95 KW-Link SYV 75-3 300 85 Note: These values apply for new, properly terminated cables. Actual performance may vary. Note: The serial data output should be disabled to achieve maximum SDI cable reach. After transmission over the coaxial cable, the 270Mb/s serial data is recovered using the and the data is decoded back into the native HD format. The encoding and decoding process has a total latency of 12-14 HD lines, which makes the CODEC ideal for low latency real-time applications. Table 4-3 below shows the total encode/decode latency through the and the GV7700. Table 4-3: Encode and Decode Total Latency ( + GV7700) Video Format Delay (μs) Delay (HD Lines) 1080p25 422.2 11.9 1080p29.97 368.8 12.4 1080p30 368.4 12.4 720p25 635.1 11.9 720p29.97 546.6 12.2 720p30 546.6 12.2 720p50 368.6 13.8 720p59.94 324.2 14.5 720p60 324.2 14.5 20 of 52

The 270Mb/s data stream uses the same timing and frame structure as Standard Definition SDI (SD-SDI), and can be monitored using standard SD-SDI test equipment to check signal integrity. However, the data contained within the active picture area of the SD-SDI stream contains only encoded HD packets. The HD video content can only be viewed after the HD-VLC decoding process. When the is HD-VLC encoding HD video formats at true 30 or 60 frames per second, the 270Mb/s serial data input will actually be incoming at a rate of 270 x 1.001Mb/s. This multiplication factor is to account for the fractional increase in the original HD video frame rate. For all other HD frame rates, the incoming serial data will be exactly 270Mb/s. 4.4.3 High Definition Output Video Format ITU-R BT.1120 describes the serial and parallel format for 1080-line interlaced and progressive digital video. The field/frame blanking period (V), the line blanking period (H), and the field identification (F), are embedded as digital timing codes (TRS) within the video. After deserialization, a single 10-bit bus carrying the C'B, Y', C'R, Y', etc. data pattern is output on the 10-bit parallel data interface, operating at a pixel clock rate of 148.5MHz or 148.5/1.001 MHz. The following figures show horizontal and vertical timing for 1080-line interlaced systems. V=1 V=0 BLANKING LINE 1 20 21 FIELD 1 (F=0) ODD FIELD 1 ACTIVE VIDEO FIELD 2 (F=1) EVEN V=1 V=0 BLANKING BLANKING FIELD 2 ACTIVE VIDEO 560 561 563 564 583 584 V=1 BLANKING 1123 1124 1125 H=1 EAV H=0 SAV Figure 4-2: Field Timing Relationship for 1080-line Interlaced Systems 21 of 52

START OF DIGITAL LINE START OF DIGITAL ACTIVE LINE NEXT LINE EAV CODE BLANKING SAV CODE 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CCR0 YCR0 CCR1 YCR1 CA0 YA0 CA1 YA1 CA2 YA2 CA(n-1) YA(n-1) 3FF 3FF 000 000 000 000 XYZ XYZ CBD0 YD0 CRD0 YD1 CBD1 YD2 CBD959 YD1918 CRD959 YD1919 3FF 3FF MULTIPLEXED STREAM H1 1920 H2 Figure 4-3: Multiplexed Luma and Chroma Over One Video Line - 1080i Table 4-4: 1080-line Interlaced Horizontal Timing Interlaced 60 or 60/1.001 Hz 50Hz H1 560 1440 H2 4400 5280 4.4.3.1 High Definition 1080p Output Formats ITU-R BT.1120 also includes progressive scan formats with 1080 active lines, with Y'C' B C' R 4:2:2 sampling at pixel rates of 74.25MHz or 74.25/1.001 MHz. The following diagrams show horizontal and vertical timing for 1080-line progressive systems. The provides a 10-bit multiplexed output interface, doubling the pixel clock output rate to 148.5MHz or 148.5/1.001 MHz. V=1 V=0 BLANKING LINE 1 41 42 (F=0) ACTIVE VIDEO V=1 BLANKING 1121 1122 1125 H=1 EAV H=0 SAV Figure 4-4: Frame Timing Relationship For 1080-line Progressive Systems START OF DIGITAL LINE START OF DIGITAL ACTIVE LINE NEXT LINE EAV CODE BLANKING SAV CODE 3FF 3FF 000 000 000 000 XYZ XYZ LN0 LN0 LN1 LN1 CCR0 YCR0 CCR1 YCR1 CA0 YA0 CA1 YA1 CA2 YA2 CA(n-1) YA(n-1) 3FF 3FF 000 000 000 000 XYZ XYZ CBD0 YD0 CRD0 YD1 CBD1 YD2 CBD959 YD1918 CRD959 YD1919 3FF 3FF MULTIPLEXED STREAM H1 1920 H2 Figure 4-5: Multiplexed Luma and Chroma Over One Video Line - 1080p 22 of 52

Table 4-5: 1080-line Progressive Horizontal Timing Progressive 30 or 30/1.001 Hz 25Hz 24 or 24/1.001 Hz H1 560 1440 1660 H2 4400 5280 5500 4.4.3.2 High Definition 720p Output Formats The Society of Motion Picture and Television Engineers (SMPTE) defines the standard for progressive scan 720-line HD image formats. SMPTE ST 296-2001 specifies the representation for 720p digital Y'C' B C' R 4:2:2 signals at pixel rates of 74.25MHz or 74.25/1.001 MHz. The provides a 10-bit multiplexed output interface, doubling the pixel clock output rate to 148.5MHz or 148.5/1.001 MHz. V=1 V=0 BLANKING LINE 1 25 26 (F=0) ACTIVE VIDEO V=1 BLANKING 745 746 750 H=1 EAV H=0 SAV Figure 4-6: 720p Digital Vertical Timing The frame rate determines the horizontal timing, which is shown in Table 4-6. Table 4-6: 720p Horizontal Timing Frame Rate H = 1 Sample Number H = 0 Sample Number Total Samples Per Line 25 2560 0 7920 30 or 30/1.001 2560 0 6600 50 2560 0 3960 60 or 60/1.001 2560 0 3300 4.4.3.3 BT.656 Video Output Timing Mode By default, the 10-bit parallel video output will contain two embedded TRS words, as defined in ITU-R BT.1120. Some commercially available CODEC devices cannot detect the presence of the double TRS in the HD video stream, and require that the 8/10-bit HD video contain only one TRS word, as per the ITU-R BT.656 Standard Definition format. When the BT656_ENABLE bit is HIGH, the will re-format the parallel video output to conform with BT.656 embedded TRS. The device will replace all data words 23 of 52

from the second TRS, line number and line CRC with blanking values, as shown in Figure 4-7. Note that when BT.656 output mode is enabled, any embedded ancillary data in the horizontal balking will remain unchanged, and will not be contiguous from the EAV. This is shown in Figure 4-8 below. CHn_PCLK CHn_DOUT_[9:0] Cb, n-4 Y, n-4 Cr, n-4 Y, n-3 Cb, n-2 Y, n-2 Cr, n-2 Y, n-1 3FFh 000h 000h EAV 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h Inserted Blanking Words CHn_HOUT CHn_VOUT CHn_FOUT CHn_DOUT_[9:0] CHn_HOUT 200h 040h 200h 040h 200h 040h 3FFh 000h 000h SAV Cb, 0 Y, 0 Cr, 0 Y, 1 Cb, 2 Y, 2 Cr, 2 Y, 3 Cb, 4 Y, 4 Cr, 4 Y, 5 Cb, 6 Y, 6 Cr, 6 Y, 7 Cb, 8 Y, 8 Cr, 8 Y, 9 Cb, 10 Inserted Blanking Words Figure 4-7: BT.656 Video Output Timing CHn_DOUT_[9:0] 3FFh 000h 000h EAV 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 200h 040h 000h 040h 3FFh 040h 3FFh 040h Inserted Blanking Words Ancillary Data Figure 4-8: Ancillary Data in BT.656 Video Output Timing Mode 4.5 Parallel Video Data Outputs CHn_DOUT_[9:0] A 10-bit video output bus is provided for each received video channel. The parallel data outputs are aligned to the rising edge of PCLK. Each output provides a 10-bit multiplexed ITU-R BT.1120 compliant video bus with embedded TRS. The drive strength of the parallel video output pins (PCLK, HOUT, VOUT, FOUT, DOUT[9:0]) can be adjusted using the PARALLEL_VIDEO_OUT_DRV_STRENGTH_SEL bit. The device uses the low drive strength setting by default. For PCB trace longer than 6 inches the high drive strength setting should be used. CHn_PCLK CHn_DOUT[9:0], CHn_FOUT, CHn_HOUT, CHn_VOUT data_* is launched on the positive edge of PCLK PCLK period data_0 data_0 transition zone t H t OD t OD t SU t H data_0 transition zone data_1 transition zone data_1 Figure 4-9: Parallel Video Output Timing Diagram 24 of 52

Table 4-7: Digital Output Specifications Digital Parallel Video Output Interface Symbol Conditions Min Typ Max Units Notes Parallel Clock Frequency f PCLK 148.5 MHz Parallel Clock Duty Cycle DC PCLK 40 60 % Output Data Hold Time (HD) t OH 1.89V operation, 6pF C LOAD, 0 C Output Data Delay Time (HD) t OD 1.71V operation, 6pF C LOAD, 85 C 1.0 ns 3.7 ns Output Data Rise/Fall Time (HD) t r /t f 1.89V operation, 6 pf C LOAD, 0 C 1.71V operation, 15 pf C LOAD, 85 C 0.4 ns 1.4 ns 4.6 Stream ID Packet Extraction The will automatically detect and extract HDcctv Stream ID packets from all four video channels. Each channel s 6 byte packet can be read from the host interface through the bits EXTRACT_STREAM_ID_BYTE[1:6] located in registers EXTRACT_STREAM_ID_REG[1:6] respectively. There are independent registers for each of the four channels. When the is decoding HD-VLC streams, the device will automatically re-insert the correct Stream ID in the HD parallel video output. Only bytes 1 and 2 of the Stream ID packet will be updated, with all other bytes set to all zero. The re-inserted byte 1 and 2 data can be read from registers INS_ID_BYTE1_REG and INS_ID_BYTE_2_REG. Bytes 1 and 2 can be programmed from bits INS_ID_BYTE[1:2] located in registers INS_ID_BYTE_REG[1:2] respectively. Byte 1 of the Stream ID packet is interpreted according to Table 4-8 below. Table 4-8: Stream ID Packet Extraction Byte 1 Input Video Standard HD-VLC Encoding Byte 1 Value Original Video Standard 720p25 OFF 14h 720p25 625i25 ON 94h 720p25 720p29.97 OFF 12h 720p29.97 525i29.97 ON 92h 720p29.97 720p30 OFF 11h 720p30 525i30 ON 91h 720p30 1080i50 OFF E3h 1080i50 25 of 52

Table 4-8: Stream ID Packet Extraction Byte 1 (Continued) Input Video Standard HD-VLC Encoding Byte 1 Value Original Video Standard 720p50 OFF 13h 720p50 625i25 ON 93h 720p50 1080i59.94 OFF E2h 1080i59.94 720p59.94 OFF 16h 720p59.94 525i29.97 ON 96h 720p59.94 1080i60 OFF E1h 1080i60 720p60 OFF 15h 720p60 525i30 ON 95h 720p60 1080p25 OFF 23h 1080p25 625i25 ON A3h 1080p25 1080p29.97 OFF 22h 1080p29.97 525i29.97 ON A2h 1080p29.97 1080p30 OFF 21h 1080p30 525i30 ON A1h 1080p30 625i25 ON F3h 1080i50 525i29.97 ON F2h 1080i59.94 525i30 ON F1h 1080i60 Note: When the is receiving HD-VLC encoded HD video formats at "true" 30 or 60 frames per second, the 270Mb/s serial data rate will be at 270 x 1.001 Mb/s. This multiplication factor is to account for the fractional increase in the original HD video frame rate. For all other HD frame rates, the HD-VLC encoded serial data rate will be exactly 270Mb/s. 4.7 Ancillary Data Extraction The is capable of extracting ancillary data packets, with the type of packet specified by the user on a programmable 10 bit DID. The 2 MSBs of the DID are written to ANC_PACKET_DID_9_8 in register ANC_PACKET_DID_9_8_REG, and the next 8 bits are written to ANC_PACKET_DID_7_0 in register ANC_PACKET_DID_7_0_REG. Up to 16 User Data Words can be extracted per ancillary data packet. The chip will extract the DID-SDID/DBN-DC-UDWs-CS bytes, and they are available in 10-bit pairs (ANC_PACKET_UD W0_9_8, ANC_PACKET_UDW0_7_0) through to (ANC_PACKET_UD W15_9_8, ANC_PACKET_UDW15_7_0). 26 of 52

The looks for packets in the horizontal blanking region of a digital video signal. The vertical blanking region is used by the HD-VLC encoder of the GV7000 which inserts compression coefficients that cannot be overwritten. The payload of the ancillary data packet can be used to carry user-defined or proprietary data, which can be sent between an Aviia transmitter and receiver. The ancillary data packet is formatted according to the Figure 4-10 below. The packet must always begin with the Ancillary Data Flag (ADF), defined as the following 10-bit word sequence: 000 h, 3FF h, 3FF h. The next data word is the 8-bit Data ID (DID), used to define the contents of the packet. For example, a unique DID can be used to denote alarm data, with another DID to denote status data. After the DID, there are two possible options, as shown in Figure 4-10. Type 1 Ancillary Data Packet MSB Not b8 Parity bit CS UDW15 UDW14 UDW13 UDW12 UDW11 UDW10 UDW9 UDW8 UDW7 UDW6 UDW5 UDW4 UDW3 UDW2 UDW1 UDW0 DC DBN DID ADF LSB User Data Words MSB Type 2 Ancillary Data Packet Not b8 Parity bit LSB ADF DID SDID DC UDW0 UDW1 UDW2 UDW3 UDW4 UDW5 UDW6 UDW7 UDW8 UDW9 UDW10 UDW11 UDW12 UDW13 UDW14 UDW15 CS User Data Words Figure 4-10: Ancillary Data Packets A Type 1 packet defines an 8-bit Data Block Number (DBN) sequence, used to distinguish successive packets with the same DID. The DBN simply increments with each packet of the same DID, between 0 and 15. For a Type 2 packet, an 8-bit Secondary Data ID (SDID) word is defined, which can be used to denote variants of payloads with the same DID. For example, packets with a DID to denote error data may distinguish different error types using unique SDID's. After the DBN or SDID, the next data word is the 8-bit Data Count (DC). This word must be set to the number of user data words (UDW) that follow the DC, and must not exceed 16 (maximum payload size). The final word of the ancillary data packet is the 9-bit Checksum (CS). The CS value must be equal to the nine least significant bits of the sum of the nine least significant bits of the DID, the DBN or the SDID, the DC and all user data words (UDW) in the packet. For HD video formats, ancillary data packets are only extracted from the Luma channel. 27 of 52

4.8 Audio Extraction The will de-embed audio from both HD and HD-VLC encoded data. The can extract up to four channels of serial digital audio at an audio sampling rate of 32kHz, 44.1kHz, or 48kHz. By default, audio extraction for each channel is enabled, and it can be disabled on any channel by setting DISABLE_AUDIO to 01 in the AUDIO_CTRL_OVERRRIDE_REG register from the host interface. By default, the device will process audio at a sampling rate of 48kHz. When using a GV7700 to chip set, audio sampled at 44.1kHz and 32kHz will be automatically detected by the. The reads the Stream ID packet byte 3 to determine the audio sampling frequency. When receiving from a signal not transmitted by the GV7700, the audio sampling rate must be manually specified if different than 48kHz, first by setting AUDIO_SAMP_FREQ_MANUAL_MODE to 1, and then by specifying the sampling frequency through AUDIO_SAMP_FREQ. Refer to Table 4-9 below. Table 4-9: Register Settings for Manual Audio Sampling Frequency AUDIO_SAMP_FREQ Sampling Frequency 00 (default) 48khz 01 44.1kHz 10 32kHz 11 Reserved The device will continuously look for the programmable audio group DID and updates the audio packets present on every rising edge of the vertical blanking interval. If several audio groups are present in the video signal, the device will extract the lower Audio Group number (ex: Audio Group 2, Audio Group 8: Audio Group 2 will be extracted). As such, the programmable audio group DID is offered to the user as a method of selecting the audio group of his choice for extraction or for specifying an audio DID that would be different from the 8 HD audio group DIDs specified in the SMPTE standards. The audio packet format is SMPTE ST 299-1, regardless of the input signal rate (270Mb/s or 1.485Gb/s). The will compute ECC (Error Correcting Codes) and compare them to the ECC embedded in the audio packets, and it will correct errors wherever possible as well as report any errors found. Error correction can be disabled by setting DISABLE_ECC to 01 in the AUD_EXT_CONFIG_REG register, and the audio samples will be bypassed as found in the packets. The audio samples will be buffered and output on the four I 2 S channels via CHn_ACLK, CHn_WCLK, CHn_AIN_1_2, and CHn_AIN_3_4 pins. They will be formatted according to the standard I 2 S bus specifications, and the timing for this interface is shown in Figure 4-11 below. 28 of 52

Not to scale 48kHz audio: 325.5ns 44.1kHz audio: 354.3ns 32kHz audio: 488.3ns CHn_ACLK CHn_AOUT_0_1, CHn_AOUT_2_3 CHn_WCLK DATA DATA t oh t od Figure 4-11: ACLK to Audio Data and WCLK Signal Output Timing Table 4-10: Serial Audio Data Outputs - AC Electrical Characteristics Parameter Symbol Conditions Min Typ Max Units Output Data Hold Time t OH 50% levels; 1.8V operation 1.5 ns Output Data Delay Time t OD 7.0 ns 4.8.1 Serial I 2 S Audio Data Format The supports the I 2 S serial audio data format, as shown in Figure 4-12 below. CHn_WCLK Channel A (Left) Channel B (Right) CHn_ACLK CHn_AIN_0_1/CHn_AIN_2_3 23 22 6 5 4 3 2 1 0 23 22 6 MSB LSB MSB 5 4 3 2 1 0 LSB Figure 4-12: I 2 S Audio Output Format 4.8.2 Audio Mute The can mute either pair of output audio channels using 2 host interface control bits for each video lane. The bits can mute channels 0 & 1 or channels 2 & 3. Channels 0 & 1 can be muted by asserting the MUTE 0_1 bit in the AUD_EXT_CONFIG_REG for any of the four video lanes. Channels 2 & 3 can be muted by asserting the MUTE_2_3 bit in the AUD_EXT_CONFIG_REG for any of the four video lanes. See Table 4-11. By default, the 4 channels will not be muted. 29 of 52

Table 4-11: Audio Mute Controls Address Register Parameter Description Channel 0: 488D h Channel 1: 548D h Channel 2: 608D h Channel 3: 6C8D h AUD_EXT_CONFIG_ REG MUTE_0_1 MUTE_2_3 HIGH = Channels 0 & 1 are muted LOW = Channels 0 & 1 are not muted HIGH = Channels 2 & 3 are muted LOW = Channels 2 & 3 are not muted 4.9 GSPI Host Interface The is controlled via the Gennum Serial Peripheral Interface (GSPI). The GSPI host interface is comprised of a serial data input signal (SDIN pin), serial data output signal (SDOUT pin), an active-low chip select (CS pin) and a burst clock (SCLK pin). The is a slave device, so the SCLK, SDIN and CS signals must be sourced by the application host processor. All read and write access to the device is initiated and terminated by the application host processor. 4.9.1 CS Pin The Chip Select pin (CS) is an active-low signal provided by the host processor to the. The HIGH-to-LOW transition of this pin marks the start of serial communication to the. The LOW-to-HIGH transition of this pin marks the end of serial communication to the. 4.9.2 SDIN Pin The SDIN pin is the GSPI serial data input pin of the. The 16-bit Command and Data Words from the host processor are shifted into the device on the rising edge of SCLK when the CS pin is LOW. 4.9.3 SDOUT Pin The SDOUT pin is the GSPI serial data output of the. All data transfers out of the to the host processor occur from this pin. By default at power up or after system reset, the SDOUT pin provides a non-clocked path directly from the SDIN pin, only when the CS pin is LOW, except during the GSPI Data Word portion for read operations to the device. When the CS pin is HIGH, the SDOUT pin will be in a high-impedance state. 30 of 52

For read operations, the SDOUT pin is used to output data read from an internal Configuration and Status Register (CSR) when CS is LOW. Data is shifted out of the device on the falling edge of SCLK, so that it can be read by the host processor on the subsequent SCLK rising edge. The current drive strength of the SDOUT pin can be adjusted using the GSPI_SDOUT_DRV_STRENGTH_SEL bit. 4.9.4 SCLK Pin The SCLK pin is the GSPI serial data shift clock input to the device, and must be provided by the host processor. Serial data is clocked into the SDIN pin on the rising edge of SCLK. Serial data is clocked out of the device from the SDOUT pin on the falling edge of SCLK (read operation). SCLK is ignored when CS is HIGH. 4.9.5 Command Word Description All GSPI accesses are a minimum of 48 bits in length (a 16-bit Command Word, a 16-bit Extended Address field, and a 16-bit Data Word) and the start of each access is indicated by the HIGH-to-LOW transition of the chip select (CS) pin of the. The format of the Command Word and Data Words are shown in Figure 4-13. Data received immediately following this HIGH-to-LOW transition will be interpreted as a new Command Word. 4.9.5.1 R/W bit - B15 Command Word This bit indicates a read or write operation. When R/W is set to 1, a read operation is indicated and data is read from the register specified by the ADDRESS field of the Command Word. When R/W is set to 0, a write operation is indicated and data is written to the register specified by the ADDRESS field of the Command Word. 4.9.5.2 BROADCAST ALL - B14 Command Word This bit must always be set to 0. 4.9.5.3 EMEM - B13 Command Word This bit must always be set to 1. 4.9.5.4 AUTOINC - B12 Command Word When AUTOINC is set to 1, Auto-Increment read or write access is enabled. In Auto-Increment Mode, the device automatically increments the register address for each contiguous read or write access, starting from the address defined in the ADDRESS field of the Command Word. 31 of 52

The internal address is incremented for each 16-bit read or write access until a LOW-to-HIGH transition on the CS pin is detected. When AUTOINC is set to 0, single read or write access is required. Auto-Increment write must not be used to update values in HOST_CONFIG. 4.9.5.5 UNIT ADDRESS - B11:B5 Command Word The 7 bits of the UNIT ADDRESS field of the Command Word should always be set to 0. 4.9.5.6 ADDRESS - B4:B0 Command Word, B15:B0 Extended Address The Address Word consists of bits [4:0] of the Command Word, plus another 16 bits [15:0] from the Extended Address Word. The total Command and Data Word format, including the Extended Address, is shown in Figure 4-13 below. Command Word MSB UNIT ADDRESS ADDRESS[20:16] LSB R / W 0 1 AUTOINC 0 0 0 0 0 0 0 A20 A19 A18 A17 A16 ADDRESS[15:0] A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data Word REPETITION CODE PAYLOAD (READ/WRITE DATA) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4-13: Command and Data Word Format 4.9.6 Data Word Description The Data Word portion of the GSPI access consists of an 8-bit repetition code, followed by an 8-bit Read or Write access Payload. All registers in the are 8 bits long, however since GSPI write commands are required to be 16 bits long, the Data Word will have the same byte repeated. For example, to write FC h to a register within the CSR, the 16-bit Data Word of the GSPI Command should be FCFC h. 32 of 52