林尚亭 1 張誌軒 2 國 立 高 雄 師 範 大 學 高雄師大學報 2007,22,63-70 SRTS 方法在高速傳輸系統的應用

SRTS 方法在高速傳輸系統的應用 國 立 高 雄 師 範 大 學 高雄師大學報 2007,22,63-70 SRTS 方法在高速傳輸系統的應用 林尚亭 1 張誌軒 2 摘 要 SRTS 可 用於 ATM 網路 上提供 固定 位元傳 輸速 率服務 以 應用在 高解 析 度 的視訊 語 音等即 時性 服務 然 而 SRTS 這 項技術 也可 以應用 在其 它較高 傳輸 速率的 服務 上 例如高 品 質數位 電視 ( high definition television HDTV) 從 影像廣 播一直到 Gbp 速 率的範 圍 所需用 到的 傳輸速 率為 2.48832 Gbp(STM-16) 因為影 像信 號週 期對於網路週期是非同步的 所以週期補償的同歩 技術是必要的 但是 在 高 傳輸速 率中 的同步 技術 是一大 挑戰 在 本論文 中 我們將 焦點 著重在 以 CBR 訊 號 的週 期補償 方法 及將 SRTS 運 用在高 傳輸 速率服 務中 我們 除了 建立 SRTS 的 發送 接 收電路 外 還分 析 在高傳 輸速 率服務 下的 相關參 數的 設定 找出 SRTS 方 法 在高速 應用 中的 最 佳設定 值 關鍵詞 SRTS 固定位 元傳輸速 率 高品質 數 位電視 1 2 國立高雄師範大學電子系助理教授 國立高雄師範大學物理系研究生 63

64 高雄師大學報第二十二期 SRTS Application in High Speed Transmission System Sun-Ting Lin * Chih-Hsuan Chang ** ABSTRACT Synchronous residual timing stamp (SRTS) is a technique originally used for encoding and transporting synchronous timing information for constant bit rate (CBR) traffic over asynchronous transfer mode (ATM) network. Recently, this technique can also be applied to other services with higher transmission rate such as video broadcasting up to the order of Gbps range such as high definition television (HDTV). The corresponding clock rate of transmission link for those high bit rate video services should be 2.48832 Gbps (Synchronous Transport Module-level 16, STM-16) instead of 155.52 Mbps (STM-1). The clock recovery is necessary since the service clock for the video signal is asynchronous to the network clock. To apply the SRTS method in a new service with different transmission rates, the related parameters should be analyzed and redesigned. In this paper, we build up the SRTS transmitter and receiver as well as analyze the jitter performance at the high bit rate services to minimize jitter generation in the SRTS method. Key words : SRTS, CBR, HDTV * Assistant Professor, Department of Electronic Engineering, National Kaohsiung Normal University. ** Graduate Student, Department of Physics, National Kaohsiung Normal University.

SRTS 方法在高速傳輸系統的應用 65 I.Introduction SRTS is a technique selected for CBR services over ATM network to allow timing recovery of the CBR service clock at the destination. The concept of synchronous timing recovery technique is based on the availability of a common reference clock at both transmitted and received side. The fundamental concept of a synchronous network is illustrated in Fig. 1. The network provides the common reference clock called f n. In the transmitted side, the service clock, f s, is compared with a network derived clock, f nx, which is x times of the common reference clock. The related information is sent through the synchronous network. At the received side, the service clock is recovered from the information and the network derived clock. The performance of SRTS technique depends on the magnitude of the residual jitter which is controlled by the frequency of the network derived clock. The residual jitter of some lower bit rate service such as T1 (1.544 Mbps), E1 (2.048 Mbps) and DS3 (44.736 Mbps), etc. over an STM-1 (155.52 Mbps) physical layer network had been analyzed [1]-[4]. The SRTS technique can be also applied to other system applications such as video services. In this application, the clock recovery of the CBR signal is necessary for the video signal transmission since the clock rate of the video signal is asynchronous to the network clock. To delivery the high quality video signal, the corresponding clock rate of transmission link should be faster. However, it is not easy to perform the timing recovery at the high bit rate services such as HDTV [5] application. In Section II, the overview of the SRTS technique and its circuit design is introduced. The corresponding timing analysis and circuit simulation results are in Section III and IV, respectively. Finally, the conclusions are in Section V. II. Overview of the SRTS Technique and its Circuit Design The top level of the SRTS circuit can be divided into three modules, including SRTS transmitter, SRTS receiver, and phase locked loop (PLL). The functionality of each module is introduced in the following. At the transmitted side, the generation of residual timing stamp (RTS) in the transmitter is shown in Fig. 2. The network derived clock f nx, which is designed to be greater than the service clock f s but less then two times of f s, drives the P-bit counter C T. The output of the counter C T is sampled every T seconds (N source clock cycles) and stored in the RTS registers. Since those two signals, f nx and f s, are asynchronous and the RTS latches need special precautions to solve the race conditions. At the received side, the recovery of S n from the received RTS and M, where M is the exact number of reference clock cycles in N source clock cycles. The gating pulse S r is used

66 高雄師大學報第二十二期 to read the new RTS value from the FIFO, the current RTS is compared with a free running P-bit counter C R, which is driven by the network derived clock f nx. The comparator generates a pulse when the output of the counter C R matches the current RTS. However, the correct RTS pulse will locate at the interval between [M min ] and [M min ] + 2 P -1, where M min is minimum possible value due to service clock tolerance. The correct RTS pulse is used as the reference signal for the PLL. The PLL circuit can use the reference RTS signal and the network clock to adjust the phase difference between the two signals. Then, it generates the output signal to track the input reference signal. The smoothed output signal is the recovered source clock of the system. The challenge of SRTS circuit design is to determine the minimum required bit P of counter and the selection of optimal N for minimizing jitter generation. The related parameters of the SRTS technique for the high bit rate service can be determined by performing timing analysis for the whole system. After determining the parameters, the circuit simulation results of the SRTS technique for the high bit rate service are discussed in the next section. III. Timing Analysis for HDTV Applications The bit rates of HDTV is 1.485 or 1.001 Gbps, therefore, the physical layer of the optical transmission rate should be at least STM-16 (2.48832 Gbps) to have enough capacity to carry the high quality video services. Since the parallel data rate of HDTV video signals is its serial clock divided by 20, the service clock f s is 74.25 MHz, which is the target frequency that have to be recovered at the received side. From the previous section, it is known that we have to select a network derived clock, f nx, which is greater than one but less than two times of the service clock. In this application, the network derived clock, f nx, can be set to 77.76 MHz with x equals 32. Due to the frequency difference between the service clock and network reference clock, the residual jitter occurs and its amplitude depends on the value of the residual as shown in Fig. 3. From the analysis, it can be observed that the amplitude of residual jitter become high if the residual is closed to 0, 1 or some simple rational number such as 1/2, 1/3, etc.. To avoid the high residual jitter amplitude, the selection of network derived clock should be avoided to have a great common factor with the service clock. In this application, the ratio of the service clock and the network derived clock can be rewrite as (275/288). The most close rational number is about (1/24), and it is a reasonable choice of the system design. Since the SRTS technique is applied to a new service, the value of P and N should be reselected. To select the proper value of P and N, the residual jitter should be analyzed in advance. In this paper, the value N is set to 8 [6] to minimize the low frequency jitter and

SRTS 方法在高速傳輸系統的應用 67 since the value N is not as large as those in the traditional ATM network to be around three thousand, the bit number of the RTS generating counter can be set to 1. However, the small N value will cause the difficulty in the PLL design. For the tolerance of larger N selection, the RTS counter is set to be 2 bit. The jitter decomposition and the RTS value prediction for N=8 and P=2 are shown in Fig. 4. IV. Circuit Simulations The whole system for transmitting HDTV over STM-16 is simulated in this section. The SRTS circuit, which includes transmitter, receiver, and PLL circuits to achieve the source clock recovery, has been designed to verify its performance. The top-down design flow is used to implement this Application Specific Integrated Circuit (ASIC). In other words, the designer has to partition the whole system into several functional blocks and coding its high-level behavioral descriptions using the high-level description language (HDL). The functional behavioral HDL codes are then synthesized into the logic representations and mapped into the target technology. The output of each design phase can be verified by using the corresponding simulation tools. Fig. 5 shows the simulation output of the RTS value and it can be compared with the calculated value shown in Fig. 4. Five signals from the transmitted side are traced in Fig. 5. The first two signals are the service clock, f s and network derived clock f nx, respectively. The forth signal is the service clock divided by N, f sn. In this simulation, N=8, and thus the signal f sn rises high once per eight f s clock cycles. The fifth signal is the output value of the P-bit counter C T. The third signal is the output of the RTS value, which is derived by using the rising edge of the f sn signal to sample the C T counter. The time scale of the last two signals are reduced to observed more RTS output sequence and these sequence are the same as our calculated values in Fig. 4. V. Conclusions In this paper, the synchronous timing recovery technique, SRTS is introduced and its new application in the HDTV video signals transmission system. The SRTS technique is already the ITU-T standard for the AAL type 1 CBR clock recovery because it takes the advantages of previous approaches. However, this technology can be applied to other network service such as high speed video signal transmission system or circuit emulation in IP network [7]. The SRTS technique can be implemented into a digital circuit according to the requirement of the system. In the future, the jitter analysis of the SRTS technique in the HDTV or other circuit emulation network can be further studied.

68 高雄師大學報第二十二期 f s Compare Synchronous Network Timing Recovery f r f nx f nx Reference Clock Generation Network Timing : fn Reference Clock Generation Fig. 1 Synchronous network timing recovery technique concept. f s Divideby N s p P-bit Register RTS P-bit load data f n Divideby x f nx C T : P-bit Counter (a) RTS FIFO P-bit Comparator S r pulse Selector C R :P-bit Counter f nx S r S nr PLL (xn) Fig. 2. The architecture of the SRTS technology (a) Transmitter (b) Receiver. Jitter Amplitude [UIp-p] 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Residue Fig. 3 Jitter amplitude vs. residue value. (b)

SRTS 方法在高速傳輸系統的應用 69 Jitter Amplitude [UIp-p] 1 0.8 0.6 0.4 0.2 0 0 5 10 15 20 25 30 35 3 RTS Value 2 1 0 0 5 10 15 20 25 30 35 Time Stamp Fig. 4 Jitter waveform and RTS output for N=8 and P=2 (2-bit counter). References Fig. 5 Circuit simulation output. J. Walker and A. Cantoni, Jitter analysis for two methods of synchronization for external timing injection, IEEE Trans. Commun., 1996, 44, (2), pp. 269 276. J. Walker and A. Cantoni, Determining parameters to minimize jitter generation in the SRTS method, IEEE Trans. Commun., 1998, 46, (1), pp. 82 90. J. Walker and A. Cantoni, Modeling of synchronization process jitter spectrum, IEEE Trans. Commun., 1999, 47, (2), pp. 316 324. J. Walker and A. Cantoni, A new reconstruction approach in the SRTS method, IEEE Trans. Commun, 2003, 51, (11), pp. 1761 1764 H. Hoffmann et. al, Studies on the bit rate requirements for a HDTV format With 1920 times 1080 pixel resolution, progressive scanning at 50 Hz frame rate targeting large flat panel displays, IEEE Trans. Broad., 2006, 52, (4), pp.420 434. T. Shiozawa et. al, Non-compressed video signal optical transmission equipment and its

70 高雄師大學報第二十二期 applications for studio to transmitter link (STL), IEEE Trans. Broad., 2006, 52, (4), pp.435 442. Y. Shen and N. Ge, Dual-stage clock recovery for TDM in packet networks, in Proc. ISCIT 2005. 2, 12-14 Oct. 2005 pp.1051 1053