Chapter 29 Analog Digital Converter (ADC)

Chapter 29 Analog Digital Converter (ADC) 29.1 Introduction The analog-to-digital (ADC) converter block consists of two separate analog to digital converters, each with four analog inputs and their own sample and hold (S/H) circuit. A common digital control module configures and controls the converters. The module is instantiated as a dual 12-bit ADC with both converters sharing a common voltage reference and control block. This is illustrated in Figure 29-1. 29.1.1 Features ADC characteristics include: 12-bit resolution Maximum ADC clock frequency is 10 MHz with 100 ns period Sampling rate up to 4 million samples per second 1 Single conversion time of 8.5 ADC clock cycles (8.5 100 ns = 708.30 ns) Additional conversion time of 6 ADC clock cycles (6 100 ns = 499.98 ns) Eight conversions in 26.5 ADC clock cycles (26.5 100 ns = 2.21 s) using parallel mode Can be synchronized to the PWM via the PWM_SYNC0/1 input signal Sequentially scan and store up to 8 measurements While operating simultaneously and in parallel, scan and store up to four measurements on each ADC converter While operating asynchronously in parallel, scan and store up to four measurements on each ADC converter Optional interrupts at end of scan if an out-of-range limit is exceeded or at zero crossing Optional sample correction by subtracting a pre-programmed offset value Signed or unsigned result Single-ended or differential inputs PWM outputs with hysteresis for three of the analog inputs 1. While in loop mode, the time between each conversion is six ADC clock cycles (499.98 ns). Using simultaneous conversion, two samples can be obtained in 499.98 ns. Samples per second is calculated according to 499.98 ns per two samples or 4,000,160 samples per second. Freescale Semiconductor 29-1

29.2 Block Diagram Figure 29-1 illustrates the dual ADC configuration. V REFH V REFLO Voltage Reference Circuit ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 MUX Sample/ Hold Scaling and Cyclic Converter A Scaling and Cyclic Converter B 12 12 Digital Output Storage Registers 16 PWM_SYNCn Controller Bus Interface Interrupt Data 29.3 External Signal Table 29-1 shows the ADC signal interface. Figure 29-1. Dual ADC Block Diagram Table 29-1. ADC Signal Signal I/O Function ADC_IN[7:0] I Analog input to be converted. ADC_VDD Dedicated power supply pins to reduce noise coupling and to improve ADC_VSS accuracy. The power provided to these pins is suggested to come from a low noise filtered source. Connect uncoupling capacitors between ADC_VDD and ADC_VSS. ADC_VSS is shared among the analog and digital circuitry. Note: On this device, the ADC reference voltages are internally connected to this supply. 29.4 Memory Map/Register Definition Do not reconfigure the ADC during scan operations, as this can lead to unpredictable results. The following accesses are allowed during scan operations: Reading status Reading conversion results Clearing interrupts 29-2 Freescale Semiconductor

Clearing zero crossing and limit status flags Starting/stopping scans using START and STOP bits. Table 29-2. ADC Memory Map Address Register Width (bits) Access Reset Value Section/Page 0xFC09_4000 Control register 1 (ADC_CR1) 16 R/W 0x5005 29.4.1/29-3 0xFC09_4002 Control register 2 (ADC_CR2) 16 R/W 0x5080 29.4.2/29-6 0xFC09_4004 Zero crossing control register (ADC_ZCCR) 16 R/W 0x0000 29.4.3/29-7 0xFC09_4006 Channel list register 1 (ADC_LST1) 16 R/W 0x3210 29.4.4/29-7 0xFC09_4008 Channel list register 2 (ADC_LST2) 16 R/W 0x7654 29.4.4/29-7 0xFC09_400A Sample disable register (ADC_SDIS) 16 R/W 0x0000 29.4.5/29-9 0xFC09_400C Status register (ADC_SR) 16 R/W 0x0000 29.4.6/29-9 0xFC09_400E Limit status register (ADC_LSR) 16 R/W 0x0000 29.4.7/29-11 0xFC09_4010 Zero crossing status register (ADC_ZCSR) 16 R/W 0x0000 29.4.8/29-12 0xFC09_4012 + 2 n 0xFC09_4022 + 2 n 0xFC09_4032 + 2 n 0xFC09_4042 + 2 n Result registers (ADC_RSLTn) n = 0 7 Low limit 0 7 registers (ADC_LLMTn) n = 0 7 High limit 0-7 registers (ADC_HLMTn) n = 0 7 Offset 0 7 registers (ADC_OFSn) n = 0 7 16 R/W 0x0000 29.4.9/29-13 16 R/W 0x0000 29.4.10/29-13 16 R/W 0x7FF8 29.4.10/29-13 16 R/W 0x0000 29.4.11/29-14 0xFC09_4052 Power control register (ADC_PWR) 16 R/W 0x3D8F 29.4.12/29-15 0xFC09_4054 Calibration register (ADC_CAL) 16 R/W 0x0000 29.4.13/29-18 0xFC09_4056 Power control register 2 (ADC_PWR2) 16 R/W 0x0005 29.4.14/29-18 0xFC09_4058 Conversion divisor register (ADC_DIV) 16 R/W 0x0505 29.4.15/29-19 0xFC09_405A Auto-standby divisor register (ADC_ASDIV) 16 R/W 0x0137 29.4.16/29-20 29.4.1 ADC Control Register 1 (ADC_CR1) This register controls all types of scans except parallel scans in the B converter when ADC_CR2[SIMULT] is cleared. Non-simultaneous parallel scan modes allow independent parallel scanning in the A and B converter. Bits 14, 13, 12, and 11 in ADC_CR2 register control converter B scans in non-simultaneous parallel scan modes. Freescale Semiconductor 29-3

Address: 0xFC09_4000 Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 DMA STOP SYNC EOS ZC LLMT HLMT W EN 0 START CHNCFG SMODE 0 IE0 IE IE IE 0 Reset 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1 Figure 29-2. Control Register 1 (ADC_CR1) Table 29-3. ADC_CR1 s 15 DMAEN 14 STOP0 13 START0 12 SYNC0 11 EOSIE0 10 ZCIE DMA enable. Enables DMA use, instead of interrupts. Also when set, all bits and signals related to the interrupt interface are redundant. This bit is used for both the converters 0 DMA disabled 1 DMA enabled ADC stop enable. When set, the current scan is stopped and no further scans can begin. Any further SYNC0 input pulses or writes to the START0 bit are ignored until this bit is cleared. After the ADC is in stop mode, you can change the result registers, and these changes are treated as if the analog core supplied the data. Therefore, limit checking, zero crossing, and associated interrupts can occur when authorized. 0 Normal operation 1 Stop mode Note: This is not the same as the processor s low-power stop mode. Start conversion. A scan is started by setting the START0 bit. This is a write-only bit. Writing one to the START0 bit again while the scan remains in process is ignored. 0 No action 1 Start command is issued Note: The ADC must be in a stable power configuration prior to writing this bit. Refer to the functional description of power modes for further details. SYNC0 enable. If set, a conversion may be initiated by asserting a positive edge on the SYNC0 input. Any subsequent SYNC0 input pulses while the scan remains in process are ignored. 0 Scan is initiated by setting the START0 bit only 1 Use a SYNC0 input pulse or START0 bit to initiate a scan Note: The ADC must be in a stable power mode prior to SYNC0 input assertion. Refer to the functional description of power modes for further details. Note: In once-scan modes, only the first SYNC0 input pulse is honored. Subsequent SYNC0 input pulses are ignored until the SYNC0 input is re-armed by writing to ADC_CR1. This can be done at any time, including while the scan remains in process. End of scan interrupt 0 enable. Enables an EOSI0 interrupt to be generated upon completion of the scan. For loop scan modes, the interrupt triggers after the completion of each iteration of the loop. 0 Interrupt disabled 1 Interrupt enabled Zero crossing interrupt enable. Enables the zero crossing interrupt if the current result value has a sign change from the previous result as configured by the ADC_ZCCR register. 0 Interrupt disabled 1 Interrupt enabled 29-4 Freescale Semiconductor

Table 29-3. ADC_CR1 s (continued) 9 LLMTIE 8 HLMTIE 7 4 CHNCFG Low limit interrupt enable. Enables the low limit exceeded interrupt when the current result value is less than the low limit register value. The raw result value is compared to ADC_LLMT, before the offset register value is subtracted. 0 Interrupt disabled 1 Interrupt enabled High limit interrupt enable. Enables the high limit exceeded interrupt if the current result value is greater than the high limit register value. The raw result value is compared to ADC_HLMT, before the offset register value is subtracted. 0 Interrupt disabled 1 Interrupt enabled Channel configure. Configures the analog inputs for single-ended or differential conversions. CHNCFG Inputs xxx1 xxx0 ADC_IN0 ADC_IN1 xx1x ADC_IN2 xx0x ADC_IN3 x1xx ADC_IN4 x0xx ADC_IN5 1xxx ADC_IN6 0xxx ADC_IN7 Differential pair (ADC_IN0 is + and ADC_IN1 is ) Single-ended inputs Differential pair (ADC_IN2 is + and ADC_IN3 is ) Single-ended inputs Differential pair (ADC_IN4 is + and ADC_IN5 is ) Single-ended inputs Differential pair (ADC_IN6 is + and ADC_IN7 is ) Single-ended inputs Differential measurements: return the max value (2 12 1) when the positive input is V REFH and the negative input is V REFLO return zero when the + input is at V REFLO and the negative input is at V REFH scale linearly between based on the voltage difference between the two signals Single-ended measurements: return the max value when the input is at V REFH return zero when the input is at V REFLO scale linearly between based on the amount by which the input exceeds V REFLO 3 Reserved, must be cleared. 2 0 SMODE Scan mode control. This bit: Determines whether the slots perform one long sequential scan or two shorter parallel scans, each performed by one of the two converters Controls how these scans are initiated and terminated Controls if the scans are performed once or repeatedly See Section 29.5.1, Scan Modes, for detailed descriptions of these modes. 000 Once sequential 001 Once parallel 010 Loop sequential 011 Loop parallel 100 Triggered sequential 101 Triggered parallel 110 Reserved 111 Reserved Freescale Semiconductor 29-5

29.4.2 ADC Control Register 2 (ADC_CR2) ADC_CR2[14:11] and the SYNC1 module input only control converter B during parallel scan modes when SIMULT = 0 (non-simultaneous parallel scan modes). Address: 0xFC09_4002 Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 STOP SYNC EOS SIM W 1 STAR 1 IE1 ULT T1 Reset 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 Figure 29-3. Control Register 2 (ADC_CR2) Table 29-4. ADC_CR2 s 15 Reserved, must be cleared. 14 STOP1 13 START1 12 SYNC1 11 EOSIE1 During parallel scan modes when SIMULT = 0, setting STOP1 stops parallel scans in the B converter and prevents new ones from starting. Any further SYNC1 input pulses or writes to the START1 bit are ignored until the STOP1 bit is cleared. After the ADC is in stop mode, you can change the B converter ADC_RSLTn, and these changes are treated as if the analog core supplied the data. Therefore, limit checking, zero crossing, and associated interrupts can occur when authorized. 0 Normal operation 1 Stop command issued Note: This is not the same as the processor s low power stop mode. Start conversion 1. During parallel scan modes when SIMULT = 0, a B converter parallel scan is started by writing one to the START1 bit. This is a write-only bit. Writing one to the START1 bit again while the scan remains in process, is ignored. 0 No action 1 Start a B converter parallel scan Note: The ADC must be in a stable power configuration prior to writing the START bit. Refer to the functional description of power modes for further details. SYNC1 enable. During parallel scan modes when SIMULT = 0, setting SYNC1 permits a B converter parallel scan to be initiated by asserting the SYNC1 input for at least one ADC clock cycle. Any SYNC1 input pulses while the scan remains in process are ignored. 0 B converter parallel scan is initiated by setting the START1 bit only 1 Use a SYNC1 input pulse or START1 bit to initiate a B converter parallel scan Note: The ADC must be in a stable power mode prior to SYNC1 input assertion. Refer to the functional description of power modes for further details. Note: In once-scan modes, only the first SYNC1 input pulse is honored. Subsequent SYNC1 input pulses are ignored until the SYNC1 input is re-armed by writing to ADC_CR2. This can be done at any time, including while the scan remains in process. End of scan interrupt 1 enable. During parallel scan modes when SIMULT = 0, this bit enables an EOSI1 interrupt to be generated upon completion of a B converter parallel scan. For loop scan mode, the interrupt triggers upon the completion of each iteration of the loop. 0 Interrupt disabled 1 Interrupt enabled 10 8 Reserved, must be cleared. 29-6 Freescale Semiconductor

Table 29-4. ADC_CR2 s (continued) 7 SIMULT Simultaneous mode. This bit only affects parallel scan modes. 0 Parallel scans in the A and B converters operate independently. Each converter s scan continues until its sample list is exhausted (four samples) or a disabled sample in its list is encountered. For loop parallel scan mode, each converter starts its next iteration when the previous iteration in that converter is complete and continues until the STOP bit for that converter is asserted. 1 Parallel scans in the A and B converters operate simultaneously and always result in pairs of simultaneous conversions. START0, STOP0, START1, and STOP1 control bits and the SYNC0 input are used to start and stop scans in both converters simultaneously. A scan ends in both converters when either converter encounters a disabled sample slot. When the parallel scan completes, the EOSI0 triggers if EOSIEN0 is set. The CIP0 status bit indicates a parallel scan is in process. 6 0 Reserved, must be cleared. 29.4.3 ADC Zero Crossing Control Register (ADC_ZCCR) ADC_ZCCR monitors the selected channels and determines the direction of zero crossing triggering the optional interrupt. Zero-crossing logic monitors only the sign change between the current and previous sample. ZCE0 monitors the sample stored in ADC_RSLT0 and bit ZCE7 monitors ADC_RSLT7. When zero crossing is disabled for a selected ADC_RSLTn, sign changes are not monitored or updated in ADC_ZCSR. Zero crossing functionality is only available on the first eight conversions in sequential mode and only available on the first four conversions assoicated with each converter in parallel modes. Address: 0xFC09_4004 Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ZCE7 ZCE6 ZCE5 ZCE4 ZCE3 ZCE2 ZCE1 ZCE0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-4. Zero Crossing Control Register (ADC_ZCCR) Table 29-5. ADC_ZCCR s 15 0 ZCEn Zero crossing enable. For each channel n setting the ZCEn field allows detection of the indicated zero-crossing condition. 00 Disabled 01 Enabled for positive to negative sign change 10 Enabled for negative to positive sign change 11 Enabled for any sign change 29.4.4 Channel List n Registers (ADC_LST1 2) The ADC_LSTn registers contain an ordered list of the channels to be converted when the next scan is initiated. If all samples are enabled in ADC_SDIS, a sequential scan of inputs proceeds in order of: SAMPLE0 7. If one of the parallel sampling modes is selected instead, the converter A sampling order is SAMPLE0 3 and the converter B sampling order is SAMPLE4 7. Freescale Semiconductor 29-7

In sequential conversion mode full functionality (offset subtraction and high/low limit checks) is only available on the first eight conversion slots, SAMPLE0 7. In parallel conversion mode full functionality is only available on the first four conversion slots of each channel, SAMPLE0 3 for converter A and SAMPLE4 7 for converter B. Address: 0xFC09_4006 Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 SAMPLE3 SAMPLE2 SAMPLE1 SAMPLE0 W Reset 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Figure 29-5. Channel List Register 1 (ADC_LST1) Address: 0xFC09_4008 Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 SAMPLE7 SAMPLE6 SAMPLE5 SAMPLE4 W Reset 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0 0 Figure 29-6. Channel List Register 2 (ADC_LST2) Table 29-6. ADC_LSTn s SAMPLEn Selects the input channel to be sampled. SAMPLEn Single Ended Differential 000 ADC_IN0 ADC_IN0+, ADC_IN1 001 ADC_IN1 ADC_IN0+, ADC_IN1 010 ADC_IN2 ADC_IN2+, ADC_IN3 011 ADC_IN3 ADC_IN2+, ADC_IN3 100 ADC_IN4 ADC_IN4+, ADC_IN5 101 ADC_IN5 ADC_IN4+, ADC_IN5 110 ADC_IN6 ADC_IN6+, ADC_IN7 111 ADC_IN7 ADC_IN6+, ADC_IN7 In sequential modes, the sample slots are converted in order from SAMPLE0 to SAMPLE7. Any sample slot may reference any analog input (may contain a binary value between 000 111). In parallel modes, converter A processes sample slots SAMPLE0 3 while converter B processes sample slots SAMPLE4 7. Because converter A only has access to analog inputs ADC_IN0 3, sample slots SAMPLE0 3 should only contain binary values between 000 and 011. Likewise, because converter B only has access to analog inputs ADC_IN4 7, sample slots SAMPLE4 7 should only contain binary values between 100 and 111. No damage occurs if this constraint is violated but results are undefined. When inputs are configured as differential pairs, a reference to either analog input in a differential pair by a sample slot implies a differential measurement on the pair. The details of single-ended and differential measurement are described in the CHNCFG bit field. Disable sample slots using the ADC_SDIS register. 29-8 Freescale Semiconductor

29.4.5 Sample Disable Register (ADC_ SDIS) Analog Digital Converter (ADC) This register is an extension to ADC_LSTn. It allows you to enable only the desired samples programmed in the SAMPLE0 7 fields. At reset all samples are enabled. Address: 0xFC09_400A Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-7. Sample Disable Register (ADC_SDIS) Table 29-7. ADC_SDISn s 15 8 Reserved, must be cleared. 7 0 DSn Disable sample. 0 Enable SAMPLEn 1 Disable SAMPLEn and all subsequent samples. Which samples are actually disabled depends on the conversion mode (sequential/parallel) and the value of SIMULT. 29.4.6 Status Register (ADC_SR) This register provides the current status of the ADC module. RDYn bits are cleared by reading their corresponding result (ADC_RSLTn) registers. HLMTI and LLMTI bits are cleared by writing one to all asserted bits in the limit status register (ADC_LSR). Likewise, ZCI is cleared by writing one to all asserted bits in ADC_ZCSR. The EOSIn bits are cleared by writing one to them. Except for CIP0 and CIP1, the register bits are sticky. When set, they require some specific action to clear them. They are not cleared automatically on the next scan sequence. Address: 0xFC09_400C Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R CIP0 CIP1 0 EOSI1 EOSI0 ZCI LLMTI HLMT RDY W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-8. Status Register (ADC_SR) Freescale Semiconductor 29-9

Table 29-8. ADC_SR s 15 CIP0 14 CIP1 Conversion in progress 0. 0 Idle state 1 A scan cycle is in progress. The ADC ignores all sync pulses or start commands. Note: This refers to any scan except a B converter scan in non-simultaneous parallel scan modes. Conversion in progress 1. 0 Idle state 1 A scan cycle is in progress. The ADC ignores all sync pulses or start commands. Note: This refers only to a B converter scan in non-simultaneous parallel scan modes. 13 Reserved, must be cleared. 12 EOSI1 11 EOSI0 10 ZCI 9 LLMTI End of scan interrupt 1. Indicates if a scan of analog inputs was completed since the last read of the status register or since a reset. If DMA is enabled (ADC_CR1[DMAEN] = 1), this bit is cleared by the DMA engine. Otherwise, EOSI1 is cleared by writing one to it. This bit cannot be set by software. 0 A scan cycle was not completed; no end of scan interrupt/dma pending 1 A scan cycle was completed; end of scan interrupt/dma pending In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop. This interrupt is triggered only by the completion of a B converter scan in non-simultaneous parallel scan modes. End of scan interrupt 0. Indicates if a scan of analog inputs was completed since the last read of the status register, or since a reset. If DMA is enabled (ADC_CR1[DMAEN] = 1), this bit is cleared by the DMA engine. Otherwise, EOSI1 is cleared by writing one to it. This bit cannot be set by software. EOSI0 is the preferred bit to poll for scan completion if interrupts are not enabled. 0 A scan cycle was not completed; no end of scan interrupt/dma pending 1 A scan cycle was completed; end of scan interrupt/dma pending In loop scan modes, this interrupt is triggered at the completion of each iteration of the loop mode. This interrupt is triggered upon the completion of any scan except for the completion of a B converter scan in non-simultaneous parallel scan modes. Zero crossing interrupt. If the respective offset register is configured by having a value greater than 0x0000, zero crossing checking is enabled. If ADC_OFSn register is 0x7FF8, the result always is less than or equal to zero. On the other hand, if ADC_OFSn is 0x0000, the result is always greater than or equal to zero and no zero crossing can occur because the sign of the result does not change. This interrupt asserts at the completion of an individual conversion which may or may not be the end of a scan. The ZCI bit is cleared by writing one to all active ADC_ZCSR[ZCSn] bits. 0 No ZCI interrupt request 1 Zero crossing encountered; interrupt pending if ZCIE is set Low limit interrupt. If the respective low limit register is enabled by having a value other than 0x0000, low limit checking is enabled. This interrupt asserts at the completion of an individual conversion which may or may not be the end of a scan. The LLMTI bit is cleared by writing one to all active ADC_LSR[LLSn] bits. 0 No low limit interrupt request 1 Low limit exceeded; interrupt pending if LLMTIE is set 29-10 Freescale Semiconductor

Table 29-8. ADC_SR s (continued) 8 HLMTI 7 0 RDYn High limit interrupt. If the respective high limit register is enabled by having a value other than 0x7FF8, high limit checking is enabled. This interrupt asserts at the completion of an individual conversion which may or may not be the end of a scan. The HLMTI bit is cleared by writing one to all active ADC_LSR[HLSn] bits. 0 No high limit interrupt request 1 High limit exceeded; interrupt pending if HLMTIE is set Ready sample 7 0. Indicate samples 7 0 are ready to be read. These bits are cleared after a read from the respective result register. The RDYn bits are set as the individual channel conversions are completed. If polling the RDYn bits to determine if a particular sample is completed, do not to start a new scan until all enabled samples are done. 0 Sample not ready or was read 1 Sample ready to read EOSI0 EOSIE0 ADC_CC0_INT EOSI1 EOSIE1 ADC_CC1_INT ZCI ZCIE LLMTI ADC_ERR_INT LLMTIE HLMTI HLMTIE Figure 29-9. ADC Interrupt 29.4.7 Limit Status (ADC_LSR) Register ADC_LSR latches in the result of the comparison between the result of the sample and the respective limit register (ADC_HLMTn, ADC_LLMTn). For example, if the result for the channel programmed in SAMPLE0 is greater than the value programmed in ADC_HLMT0, then HLS0 is set. An interrupt is generated if ADC_CR1[HLMTIE] is set. An ADC_LSR bit is cleared by writing a value of one to that specific bit. These bits are sticky. When set, they require a specific modification to clear them and are not cleared automatically by subsequent conversions. Freescale Semiconductor 29-11

Address: 0xFC09_400E Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R HLS LLS W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-10. Limit Status Register (ADC_LSR) Table 29-9. ADC_LSRn s 15 8 HLS 7 0 LLS High limit status 7 0. Indicates if the result for the channel is greater than the value programmed in the corresponding ADC_HLMTn register. Low limit status 7 0. Indicates if the result for the channel is less than the value programmed in the corresponding ADC_HLMTn register. 29.4.8 Zero Crossing Status Register (ADC_ZCSR) ADC_ZCSR latches the result of the comparison between the current result of the sample and the previous result of the same sample register. For example, if the result for the channel programmed in SAMPLE0 changes sign from the previous conversion and the respective ADC_ZSR[ZCEn] field is 11 (any edge change) then the ZCS0 bit is set. An interrupt is generated if ADC_CR1[ZCIE] is set. A bit can only be cleared by writing one to that specific bit. These bits are sticky. When set, they require a write to clear them. They are not cleared automatically by subsequent conversions. Address: 0xFC09_4010 Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 ZCS W w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-11. Zero Crossing Status Register (ADC_ZCSR) Table 29-10. ADC_ZCSRn s 15 8 Reserved, must be cleared. 7 0 ZCS Zero crossing status. The zero crossing condition is determined by examining the ADC value after it is adjusted by the offset for the ADC_RSLTn register. Please see Figure 29-26. Each bit of the register is cleared by writing one to that bit. 0 A sign change did not occur in a comparison between the current channeln result and the previous channel result, or zero crossing control is disabled for channel n in ADC_ZCCR. 1 In a comparison between the current channel n result and the previous channel n result, a sign change condition occurred as defined in ADC_ZCCR. 29-12 Freescale Semiconductor

29.4.9 ADC Result Registers (ADC_RSLT0 7) Analog Digital Converter (ADC) These eight result registers contain the converted results from a scan. The SAMPLE0 result is loaded into ADC_RSLT0, SAMPLE1 result in ADC_RSLT1, etc. In a parallel scan mode, the first channel pair designated by SAMPLE0 and SAMPLE4 in register ADC_LST1 2 are stored in ADC_RSLT0 and ADC_RSLT4 respectively. NOTE When writing to this register, only the RESULT portion of the value written is used. This value is modified, illustrated in Figure 29-26 and the result of the subtraction is stored. The SEXT bit is only set as a result of this subtraction and is not directly determined by the value written. Address: 0xFC09_4012 (ADC_RSLT0) 0xFC09_4014 (ADC_RSLT1) 0xFC09_4016 (ADC_RSLT2) 0xFC09_4018 (ADC_RSLT3) 0xFC09_401A (ADC_RSLT4) 0xFC09_401C (ADC_RSLT5) 0xFC09_401E (ADC_RSLT6) 0xFC09_4020 (ADC_RSLT7) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SEXT RESULT 0 0 0 W TEST_DATA Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-12. Result Registers (ADC_RSLTn) Table 29-11. ADC_RSLTn s 15 SEXT 14 3 RESULT Sign extend bit of the result. If all positive results are required, set the respective ADC_OFSn register to zero. 0 Positive result 1 Negative result Digital result of the conversion. The ADC_RSLTn register can be interpreted as: Signed fractional number the RSLTn can be used directly. Signed integer you may right shift with sign extend, arithmetic shift right (ASR) three places and interpret the number, or accept the number as presented, knowing there are missing codes. The lower three bits of this register are always zero. Negative results (SEXT = 1) are always presented in two s compliment format. If the ADC_RSLTn registers must always be positive, clear ADC_OFSn. The interpretation of the numbers programmed into the ADC_LLMTn, ADC_HLMTn, and ADC_OFSn registers should match the interpretation of ADC_RSLTn. See Section 29.5.4, ADC Data Processing for a description of reading this field and how/when it can be used. 2 0 Reserved, must be cleared. 29.4.10 Low and High Limit Registers (ADC_LLMT0 7 & ADCHLMT0 7) Each ADC sample is compared against its corresponding limit registers. The comparison is based upon the raw conversion value with no offset correction applied. Please refer to Figure 29-26. Freescale Semiconductor 29-13

The ADC tests if the result is greater than the high limit or less than the low limit. Disable limit checking by programming the respective high limit register with 0x7FF8 and the low limit register with 0x0000. At reset, limit checking is disabled. Address: 0xFC09_4022 (ADC_LLMT0) 0xFC09_4024 (ADC_LLMT1) 0xFC09_4026 (ADC_LLMT2) 0xFC09_4028 (ADC_LLMT3) 0xFC09_402A (ADC_LLMT4) 0xFC09_402C (ADC_LLMT5) 0xFC09_402E (ADC_LLMT6) 0xFC09_4030 (ADC_LLMT7) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 LIMIT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-13. Low Limit Registers (ADC_LLMTn) Address: 0xFC09_4032 (ADC_HLMT0) 0xFC09_4034 (ADC_HLMT1) 0xFC09_4036 (ADC_HLMT2) 0xFC09_4038 (ADC_HLMT3) 0xFC09_403A (ADC_HLMT4) 0xFC09_403C (ADC_HLMT5) 0xFC09_403E (ADC_HLMT6) 0xFC09_4040 (ADC_HLMT7) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 LIMIT W Reset 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 Figure 29-14. High Limit Registers (ADC_HLMTn) Table 29-12. ADC_LLMTn & ADC_HLMTn s 15 Reserved, must be cleared. 14 3 LIMIT High or low limit to compare the ADC sample result. 2 0 Reserved, must be cleared. 29.4.11 Offset Registers (ADC_OFS0 7) The ADC_OFSn registers correct the ADC result before it is stored in the ADC_RSLTn registers. Address: 0xFC09_4042 (ADC_OFS0) 0xFC09_4044 (ADC_OFS1) 0xFC09_4046 (ADC_OFS2) 0xFC09_4048 (ADC_OFS3) 0xFC09_404A (ADC_OFS4) 0xFC09_404C (ADC_OFS5) 0xFC09_404E (ADC_OFS6) 0xFC09_4050 (ADC_OFS7) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 OFFSET W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-15. Offset Registers (ADC_OFSn) 29-14 Freescale Semiconductor

Table 29-13. ADC_OFSn s 15 Reserved, must be cleared. 14 3 OFFSET qa The offset value is subtracted from the ADC result. To obtain unsigned results, program the respective ADC_OFSn register with a value of 0x0000. This results in a range of 0x0000 to 0x7FF8. Reserved, must be cleared. 29.4.12 Power Control Register (ADC_PWR) This register controls the power management features of the ADC module. There are individual manual power down controls for the two ADC converters and the voltage reference generator. There are also five distinct power modes. The following terms are used to describe power modes and their related controls. Power down state Each converter and the voltage reference generator can individually be put into a power down state. When powered down, the unit consumes no power. Results of scans referencing a powered down converter are undefined. The voltage reference generator and at least one converter must be powered up to use the ADC module. Manual power down controls Each converter and the voltage reference generator have a manual power control bit capable of putting that component into the power down state. Converters have other mechanisms with the capacity to automatically put them into the power down state. Idle state The ADC module is idle when neither of the two converters has a scan in process. Active state The ADC module is active when at least one of the two converters has a scan in process. Current mode Both converters share a common current mode. Normal current mode is used to power the converters at clock rates above 600 khz. Start-up delay Auto-power down modes cause a start-up delay when the ADC module goes between the idle and active states to allow time to switch clocks or power configurations. See Section 29.5.7, Power Management for details of the five power modes and how to configure them. See Section 29.5.12, Interrupt Operation for a more detailed description of the clocking system and the control of current mode. Address: 0xFC09_4052 (ADC_PWR) Access: User read/write R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASB APD PSTS 3 PSTS 2 PSTS 1 PSTS 0 PUDELAY Reset 0 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 Figure 29-16. Power Control Register (ADC_PWR) PD 3 PD 2 PD 1 PD 0 Freescale Semiconductor 29-15

Table 29-14. ADC_PWR s 15 ASB 14 APD 13 PSTS3 12 PSTS2 11 PSTS1 10 PSTS0 Auto standby mode enable. This bit is ignored if APD is set. When the ADC is idle, ASB mode selects the standby clock as the ADC clock source, putting the converters into standby current mode. At the start of any scan, the conversion clock is selected as the ADC clock and then a delay of PUDELAY ADC clock cycles is imposed for current levels to stabilize. After this delay, the ADC initiates the scan. When the ADC returns to the idle state, the standby clock is again selected and the converters revert to the standby current state. 0 ASB mode disabled 1 ASB mode enabled Note: This mode is not recommended for conversion clock rates at or below 200 khz. Instead, clear ASB and APD, and use standby power mode (normal mode with a sufficiently slow conversion clock so standby current mode automatically engages). This provides the advantages of standby current mode while avoiding the clock switching and PUDELAY. Note: Ideally, you should set this bit before clearing PD0 and PD1 to get the benefit of this power-saving mode right after power-up. Auto power down. Powers down the converters when not in use for a scan. When a scan is started in APD mode, a delay of PUDELAY ADC clock cycles is imposed during which the needed converters, if idle, are powered up. The ADC then initiates a scan equivalent to that when APD is not active. When the scan completes, the converters are powered down again. 0 Auto power down mode is not active 1 Auto power down mode is active Note: If ASB or APD is set while a scan is in progress, that scan is unaffected and the ADC waits to enter its low power state until after all conversions are complete and both ADCs are idle. Note: ASB and APD are not useful in loop modes. The continuous nature of scanning means the low power state can never be entered. Voltage reference converter B power status. 0 Voltage reference circuit is currently powered up 1 Voltage reference circuit is currently powered down Voltage reference converter A power status. 0 Voltage reference circuit is currently powered up 1 Voltage reference circuit is currently powered down Converter B Power status. PSTS1 is set immediately following a write of one to PD1. It is de-asserted PUDELAY ADC clock cycles after a write of 0 to PD1 if ADP is cleared. This bit can be read as a status bit to determine when the ADC is ready for operation. During auto-powerdown mode, this bit indicates the current powered state of converter B. 0 Converter B is currently powered up 1 Converter B is currently powered down Converter A power status. PSTS0 is set immediately following a write of one to PD0. It is de-asserted PUDELAY ADC clock cycles after a write of 0 to PD0 if ADP is cleared. This bit can be read as a status bit to determine when the ADC is ready for operation. During auto-powerdown mode, this bit indicates the current powered state of converter A. 0 Converter A is currently powered up 1 Converter A is currently powered down 29-16 Freescale Semiconductor

Table 29-14. ADC_PWR s (continued) 9 4 PUDELAY 3 PD3 2 PD2 1 PD1 0 PD0 Power-up delay. Determines the number of ADC clocks provided to power up an ADC converter (after clearing PD0 or PD1) before allowing a scan to start. It also determines the number of ADC clocks of delay provided in APD and ASB modes between when the ADC goes from the idle to active state and when the scan is allowed to start. The default value is 24 ADC clocks for a 10 MHz conversion clock as a 2 s delay is required after PD2/PD3 is cleared. Accuracy of the initial conversions in a scan is degraded if PUDELAY is set to too small of a value. After power-up, you can reprogram PUDELAY to 13 for minimal delay in APD and lesser in ASB. The value required for PUDELAY depends on the power down state chosen: Power down state 1, PD0/1 = 1, PD2/3 = 1 The entire ADC is in power down mode. Upon clearing PDn, there is a delay of 2 s before the ADC can start making conversions. Value of 24 is required for a 10 MHz conversion clock. Power down state 2, PD0/1 = 1, PD2/3 = 0 In this partial power down state only the amplifiers in the recursive sub-ranging sections (RSD) are powered off, which significantly reduces the power consumption of the ADC. Upon clearing PD0/1, there is a delay of 13 clock cycles before the ADC can start making conversions. Power down state 3, PD0/1 = 0, PD2/3 = 1 In this partial power down state only the bias reference generator, switch reference generator and the over rant reference generator are turned off. Upon releasing PD2/3, there is a delay of 2 s before the ADC can start making conversions. Note: PUDELAY defaults to a value typically sufficient for any power mode. The latency of a scan can be reduced by decreasing PUDELAY to the lowest value that accuracy is not degraded. Refer to the processor s data sheet for further details. Voltage reference converter B power down enable. Forces the voltage reference circuit to power down. 0 Manually power up 1 Power down controlled by PD1. The voltage reference is activated when PD1 is cleared. Note: After clearing this bit, wait at least 2 s (use PUDELAY to enforce this delay) before initiating a scan to stabilize the current levels within the converter. Voltage reference converter A power down enable. Forces the voltage reference circuit to power down. 0 Manually power up 1 Power down controlled by PD0. The voltage reference is activated when PD0 is cleared. Note: After clearing this bit, wait at least 2 s (use PUDELAY to enforce this delay) before initiating a scan to stabilize the current levels within the converter. Manual converter B power down. 0 Manually power up. This converter is powered up continuously (APD = 0) or automatically when needed (APD = 1). Do not clear this bit unless PD3 is cleared. 1 Immediately power down converter B. The results of a scan using this converter are invalid. Note: In any power mode except auto-powerdown (APD=1), when clearing PD1, wait PUDELAY ADC clock cycles before initiating a scan to stabilize power levels within the converter. Poll PSTS1 to determine when the PUDELAY time has elapsed. Failure to do this results in loss of accuracy of the first two samples. Manual converter A power down. 0 Manually power up. This converter is powered up continuously (APD = 0) or automatically when needed (APD = 1). Do not clear this bit unless PD2 is cleared. 1 Immediately power down converter A. The results of a scan using this converter are invalid. Note: In any power mode except auto-powerdown (APD=1), when clearing PD0, wait PUDELAY ADC clock cycles before initiating a scan to stabilize power levels within the converter. Poll PSTS0 to determine when the PUDELAY time has elapsed. Failure to do this results in loss of accuracy of the first two samples. Freescale Semiconductor 29-17

29.4.13 Calibration Register (ADC_CAL) The ADC provides for off-chip references used for ADC conversions. Address: 0xFC09_4054 (ADC_CAL) Access: User read/write R VREF W H1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VREF L1 VREF H0 VREF L0 0 0 0 0 0 0 0 0 0 0 DAC 1 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 29-17. Calibration Register (ADC_CAL) Table 29-15. ADC_CAL s DAC 0 15 VREFH1 14 VREFL1 13 VREFH0 12 VREFL0 V REFH source 1. Selects the source of the V REFH reference for all conversions in converter 1. 0 Internal V DDA 1 ADC_IN4 V REFLO source 1. Selects the source of the V REFLO reference for all conversions in converter 1. 0 Internal V SSA 1 ADC_IN5 V REFH source 0. Selects the source of the V REFH reference for all conversions in converter 0. 0 Internal V DDA 1 ADC_IN0 V REFLO source 0. Selects the source of the V REFLO reference for all conversions in converter 0. 0 Internal V SSA 1 ADC_IN1 11 2 Reserved, must be cleared. 1 DAC1 0 DAC0 DAC1 alternate source 1. Selects the source of the ADCB3 input as DAC1 output. 0 Normal operation 1 ADC_IN7 input is replaced with DAC1 output DAC0 alternate source 0. Selects the source of the ADCA3 input as DAC0 output. 0 Normal operation 1 ADC_IN3 input is replaced with DAC0 output 29.4.14 Power Control Register 2 (ADC_PWR2) Address: 0xFC09_4056 (ADC_PWR2) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 STN SPEEDB SPEEDA W BY Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Figure 29-18. Power Control Register 2 (ADC_PWR2) 29-18 Freescale Semiconductor

Table 29-16. ADC_PWR2 s 15 5 Reserved, must be cleared. 4 STNBY 3 2 SPEEDB 1 0 SPEEDA Standby mode enable. 0 Not in standby mode 1 Enable standby mode. The ADC converters are placed into low power mode. Set ADC_DIV such that the conversion clock is in the 200 600 khz range. Only set this bit when the bus clock is running at a lower frequency as the dividers are not large enough to generate a 200-kHz conversion clock from a 125-MHz bus clock. Converter B speed control. Configures the clock speed the ADCB operates. Faster conversion speeds require greater current consumption. Default value is set to 01 for conversion up to 10 MHz. Note: If the conversion clock frequency remains in a range for a specific SPEEDB setting, you can change the frequency of the conversion clock without any wait period. However, if the conversion clock frequency change is significant enough that it falls into a different SPEEDB setting, then you must wait 2 s after changing the SPEEDB setting before using the ADC. Note: Before changing SPEEDB, set ADC_PWR[PD3] or ADC_PWR[PD1]. After changing SPEEDB, clear ADC_PWR[PD3,PD1]. This sequence is followed by PUDELAY(which should be set to 24) which forces a 2 s delay. Converter A speed control. Configures the clock speed that the ADCA operates. Faster conversion speeds require greater current consumption. Default value is set to 01 for conversion up to 10 MHz. Note: If the conversion clock frequency remains in a range for a specific SPEEDA setting, you can change the frequency of the conversion clock without any wait period. However, if the conversion clock frequency change is significant enough that it falls into a different SPEEDA setting, then you must wait 2 s after changing the SPEEDA setting before using the ADC. Note: Before changing SPEEDA, set ADC_PWR[PD2] or ADC_PWR[PD0]. After changing SPEEDA, clear ADC_PWR[PD2,PD0]. This sequence is followed by PUDELAY(which should be set to 24) which forces a 2 s delay. 29.4.15 Conversion Divisor Register (ADC_DIV) Address: 0xFC09_4058 (ADC_DIV) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 DIV1 DIV0 W Reset 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 Figure 29-19. Conversion Divisor Register (ADC_DIV) Table 29-17. ADC_DIV s 15 Reserved, must be cleared. 14 8 DIV1 Same as the DIV0 description, but DIV1 is used to generate the clock for converter B during parallel non-simultaneous scan modes. See the DIV0 description for details. Freescale Semiconductor 29-19

Table 29-17. ADC_DIV s (continued) 7 Reserved, must be cleared. 6 0 DIV0 Clock divisor select. The divider circuit generates the ADC clock by dividing the system clock by 2 (DIV0 + 1). Select a DIV0 value so the ADC clock does not exceed 10 MHz or go below 600 KHz. The following table shows ADC clock frequency based on the value of DIV0 for various configurations. Default value is set for an internal clock of 125 Mhz with maximum valid conversion clock below 10 MHz. DIVn Divisor ADC Conversion Clock (MHz) 125MHz 60MHz (Limp Mode) 0x00 2 62.5 30 0x01 4 31.25 15 0x02 6 20.83 10 0x03 8 15.62 7.5 0x04 10 12.5 6 0x05 12 10 5............ 0x67 208 0.6 Note: When ADC_PWR2[STNBY] is set, program values in both dividers so that a 200 600 khz conversion clock is generated. 29.4.16 Auto-Standby Divisor Register (ADC_ASDIV) Address: 0xFC09_405A (ADC_ASDIV) Access: User read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 ASDIV W Reset 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 Figure 29-20. Auto-Standby Divisor Register (ADC_ASDIV) 29-20 Freescale Semiconductor

Table 29-18. ADC_ASDIV s 15 7 Reserved, must be cleared. 6 0 ASDIV Clock divisor select. The divider circuit generates the ADC auto-standby clock by dividing the system clock by 2 (ASDIV + 1). Select a ASDIV value so the ADC auto-standby clock is in the 200 600 khz range. The following table shows the ADC auto-standby clock frequency based on the value of ASDIV for various configurations. Default value is set for an internal clock of 125Mhz. ASDIV ADC Clock In (MHz) Divisor Auto-Standby Clock (khz) 0x137 125 624 200 0x12B 120 600 200 0x0F9 100 500 200 0x0EF 96 480 200............ 0x03B 24 120 200 0x027 16 80 200 0x013 8 60 200 29.5 Functional The ADC block consists of two 4-channel input select function, two independent sample and hold (S/H) circuits feeding two separate 12-bit ADCs. The two separate converters store their results in an accessible buffer, awaiting further processing. The conversion process is initiated by a SYNC signal from one of the on-chip timer channels (see Chapter 10, Chip Configuration Module (CCM)) or by writing one to a ADC_CRn[START] bit. Starting a single conversion actually begins a sequence of conversions, or a scan. A conversion takes up to eight-single ended or differential samples, one at a time in sequential scan mode. In parallel scan mode, the eight samples are allocated, four to converter A and four to converter B. In parallel scan modes, converter A can only sample analog inputs ADC_IN0 3 while converter B can only sample analog inputs ADC_IN4 7. Each converter can take up to four samples. The scan sequence is determined by defining eight sample slots, processed in order SAMPLE0 7 during sequential scan mode. In parallel scan mode, the SAMPLE0 3 are processed in order by converter A, and SAMPLE4 7 are processed in order by converter B. Sample slots may be disabled using the ADC_SDIS register to terminate a scan early. The following pairs of analog inputs can be configured as a differential pair: ADC_IN0 1, ADC_IN2 3, and ADC_IN4 5, ADC_IN6 7. When configured as a differential pair, a reference to either member of the pair by a sample slot results in a differential measurement using that differential pair. Freescale Semiconductor 29-21

The ADC can perform a single scan and halt, perform a scan when triggered, or perform the scan sequence repeatedly until manually stopped. These modes are described in the following section. 29.5.1 Scan Modes The various scan modes defined by ADC_CR1[SMODE] are described in Table 29-19. Table 29-19. Scan Modes SMODE Scan 000 Once sequential Upon start or an enabled sync signal, samples are taken one at a time starting with SAMPLE0, until the first disabled sample is encountered. If no disabled sample is encountered, conversion concludes after SAMPLE7. If the scan is initiated by a SYNC signal only one scan is completed until the converter is rearmed by writing to ADC_CR1. 001 Once parallel Upon start or an enabled sync signal, converter A converts SAMPLE0 3 and converter B converts SAMPLE4 7 in parallel. When SIMULT is set, scanning stops when either converter encounters a disabled sample or both converters complete their 4 samples. When SIMULT is cleared, scanning stops in a converter when that converter encounters a disabled sample or that converter completes its four samples. If the scan is initiated by a SYNC signal, only one scan is completed until the converter is rearmed by writing to ADC_CR1. If SIMULT is cleared, then the B converter must be rearmed by writing to ADC_CR2. 010 Loop sequential Upon an initial start or enabled sync pulse, up to eight samples in order SAMPLE0 7 are taken one at a time until a disabled sample is encountered. The process repeats until the STOP0 bit is set. While a loop mode is running, do not give any additional start commands or sync pulses. If ASB or APD is the selected power mode control, PUDELAY is only applied on the first conversion. 011 Loop parallel Upon an initial start or enabled sync pulse, converter A converts SAMPLE0 3 and converter B converts SAMPLE4 7. Each time a converter completes its current scan, it immediately restarts its scan sequence. This continues until the STOP bit is set. While a loop mode is running, do not give any additional start commands or sync pulses. When SIMULT is set, scanning restarts when either converter encounters a disabled sample. When SIMULT is cleared, scanning restarts in a converter when that converter encounters a disabled sample. If auto-standby (ASB) or auto-power down (APD) is the selected power mode control, PUDELAY is only applied on the first conversion. 100 Triggered sequential Upon start or an enabled sync signal, samples are taken one at a time starting with SAMPLE0, until a disabled sample is encountered. If no disabled sample is encountered, conversion concludes after SAMPLE7. If external sync is enabled, new scans are started for each SYNC pulse that is non-overlapping with a current scan in progress. 101 Triggered parallel Upon start or an enabled sync signal, converter A converts SAMPLE0 3 and converter B converts SAMPLE4 7 in parallel. When SIMULT is set, scanning stops when either converter encounters a disabled sample. When SIMULT is cleared, scanning stops in a converter when that converter encounters a disabled sample. If external sync is enabled new scans are started for each non-overlapping SYNC pulse with a current scan in progress. 29-22 Freescale Semiconductor

The parallel scan modes can be simultaneous or non-simultaneous, as defined by ADC_CR2[SIMULT]: Simultaneous scan mode the parallel scans in the two converters are executed simultaneously, always resulting in simultaneous pairs of conversions: one by converter A and one by converter B. The two converters share the same start, stop, sync, end-of-scan interrupt enable control, and interrupt. Scanning in both converters is terminated when either converter encounters a disabled sample. Non-simultaneous scan mode the parallel scans in the two converters are done independently. The two converters have their own start, stop, sync, end-of-scan interrupt enable controls and interrupts. Scanning in either converter terminates only when that converter encounters a disabled sample. CAL REF ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 ADC_IN4 ADC_IN5 ADC_IN6 ADC_IN7 4 1 analog mux SAMPLEn 4 1 analog mux CAL REF 2 1 mux CAL0 2 1 mux CAL1 A/D#0 AD#1 2 8 mux RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 ADC_LSTn{SAMPLEn] SAMPLEn Figure 29-21. ADC Sequential Operation Mode Freescale Semiconductor 29-23