AN9 Application note STE0P full feature fast ethernet transceiver Introduction This document details how STE0P can be configured with external hardware to form a complete system. It gives design and layout guidelines together with suggestions and hints to interface it to external components. A sample application with bill of materials is also provided. May 00 Doc ID Rev / www.st.com
Contents AN9 Contents Introduction................................................ General description........................................... Features................................................... Design and layout guidelines................................... General guidelines............................................ Differential signal layout guidelines............................... Power and ground............................................ Recommendations........................................... Twisted pair interface......................................... Transmit interface circuitry...................................... Receive termination circuitry.................................... Standard termination......................................... Crystal and LEDs............................................ Crystal requirements.......................................... LED pins................................................... Typical application.......................................... 9. Schematics and bill of materials................................ 0 Revision history........................................... / Doc ID Rev
AN9 General description General description The STE0P is a high performance Fast Ethernet physical layer transceiver for 0BASE-T and 00BASE-TX applications. It is designed with advanced CMOS technology to provide a Media Independent Interface (MII, RMII, or SMII) for easy connection to 0/00 Media Access Controllers (MAC) and a physical media interface for 00BASE-TX and 0BASE-T standards. The twisted pair interface directly drives a 0/00 twisted pair and supports automatic detection and adaptation for MDI or MDIX connections, as well as autonegotiation to 0Mbps or 00Mbps, and half or full duplex operation, depending upon the abilities of the link partner. The STE0P is an excellent device perfectly suited for hub, switch, router and other embedded Ethernet applications. A typical system diagram is as shown below: Figure. Typical system diagram Serial EEPROM LEDs PCI Interface MAC device STE0P Transformer RJ- Boot ROM MHz crystal. Features Integrates the whole physical layer functions of the 00BASE-TX and 0BASE-T Automatic detection and adaptation for MDI or MDIX connections The hardware control pins set the initial state of the STE0P at power-up. V low power operation Can operate either in full duplex or in half duplex network applications. MII, RMII, and SMII interfaces supported Provides auto-negotiation, parallel detection or MAC control for mode setting Provides MLT- transceiver with DC restoration for base-line wander compensation Provides transmit wave-shaper, receive filters, and adaptive equalizer Provides loop-back modes for diagnostic testing Built in stream cipher scrambler/descrambler and B/B encoder/decoder Supports external transmit transformer with turns ratio of.: Supports external receive transformer with turns ratio of.: Doc ID Rev /
Design and layout guidelines AN9 Design and layout guidelines. General guidelines Verify that all components meet application requirements. Design in filters for the analog power circuits. Use bulk capacitors (0- µf) between the power and ground planes to minimize switching noise, particularly near high-speed busses (> MHz). Use an ample supply of 0. µf decoupling capacitors to reduce high-frequency noise on the power and ground planes. Use a single analog power and ground plane for multiple devices. Keep ferrite bead currents under % of the rated load. Avoid breaks in the ground plane, especially in areas where it is shielding highfrequency signals. Keep power and ground noise levels below 0 mv. Keep high-speed signals out of the area between STE0P and the magnetics. Ensure that the power supply is rated for the load and that output ripple is minimal (<0 mv). Route high-speed signals next to a continuous, unbroken ground plane. Provide impedance matching on long traces to prevent reflections. Do not route any digital signals between the STE0P and the RJ- connectors at the edge of the board. It is recommended to fill in unused areas of the signal planes with solid copper and attach them with vias to a Vcc or ground plane that is not located adjacent to the signal layer.. Differential signal layout guidelines Route differential pairs close together and away from everything else. Keep both traces of each differential pair as close to the same length as possible. Avoid vias and layer changes. Keep transmit and receive pairs away from each other. Run orthogonally, or separate with a ground plane layer.. Power and ground In order to obtain high speed communications design, the power and ground planes may be conceptually divided into three regions (the analog and digital power planes and the signal ground plane). The analog power region extends from the magnetics back to the STE0P, whereas the digital power region extends from the MII interfaces of the STE0P through the rest of the board. Only components and signals pertaining to the particular interface should be placed or routed through each respective region. The digital section supplies power to the digital Vcce/i pin and to the external components. The analog section supplies power to Vcca pins of the STE0P. / Doc ID Rev
AN9 Design and layout guidelines The signal ground region is one continuous, unbroken plane that extends from the magnetics through the rest of the board. The signal ground plane may be combined with chassis ground or isolated from it. If the ground planes are combined, an isolation area is not required. When laying out ground planes, special care must be taken to avoid creating loop antenna effect. Some guidelines are as follows- Run all ground plane as solid square or rectangular regions. Avoid creating loops with ground planes around other planes.. Recommendations The following recommendations apply to design and layout of the power and ground planes and will prevent the most common signal and noise issues. Divide the Vcc plane into two sections - analog and digital. The break between the planes should run under the device. When dividing the Vcc plane, it is not necessary to add extra layers to the board. Simply create moats or cutout regions in existing layers. Place a high-frequency bypass capacitor (0. µf) near each analog Vcc pin. Join the digital and analog sections at one or more points by ferrite beads. Ensure that the maximum current rating of the bead is at least 0% of the nominal current that is expected to flow through it. (0 ma per STE0P). Place a bulk capacitor ( µf) on each side of each ferrite bead to stop switching noise from travelling through the ferrite. For designs with multiple STE0P s, it is acceptable to supply all from one analog Vcc plane. This plane can be joined to the digital Vcc plane at multiple points, with a ferrite bead at each one. Doc ID Rev /
Twisted pair interface AN9 Twisted pair interface. Transmit interface circuitry Figure shows a typical transmit interface circuitry. Current is sourced by the AVddt output to the center tap of the primary side of the winding. Current flows from the center tap to TX+ and TX-. Other components are as follows: The STE0P internally implements impedance matching to the line, which has a nominal impedance of 00 Ohm. C shunts any common-mode energy present in the output to ground. The magnetics consists of the main winding and a common-mode choke. The common-mode choke stops common mode energy from reaching the line. It works together with capacitor C to direct common-mode energy away from the line. The STE0P requires no external impedance matching 0 Ohm load resistors. It implements these impedances internally, thus requiring lower external component cost. The following list of.: transformers have been tested and verified to operate properly with the STE0P: Tyco/Transpower HB Pulse Engineering H00 Halo Electronics TG0-SN Figure. Transmit interface circuitry TX+ AVdd Magnetics RJ- STE0P TX-. : C A Chassis ground. Receive termination circuitry The receive termination circuit as shown in Figure is a simple direct connection to the transformer. No external impedance matching resistor is required across the RX+/RX- pair, as it is internally implemented. The receive circuit just consists of magnetics, which include a main winding and a common-mode choke. The center tap of the receive transformer must be connected to AVdd and to ground with a small capacitor. The common-mode choke can be located on either the primary or secondary side of the winding. Either locations are acceptable. / Doc ID Rev
AN9 Twisted pair interface Figure. Receive termination circuitry RX+ AVdd Magnetics RJ- STE0P RX-. : C A Chassis ground. Standard termination A standard termination is recommended for the unused pairs on the twisted pair interface as shown in Figure. The termination basically is a load, matched to the line, which is by passed to chassis ground. This termination is added for robustness and noise reduction. Figure. Suggested termination circuit Ohm RX Ohm TX Ohm Ohm RJ- 0.00 µf kv Doc ID Rev /
Crystal and LEDs AN9 Crystal and LEDs. Crystal requirements The following table shows the crystal specifications. Table. Crystal specification Parameter Min Typ Max Units Frequency -.0 - MHz Frequency stability - - + 0 ppm Load capacitance pf Shunt capacitance pf. LED pins The LED display consists of five separate LEDs. Speed LED: 00 Mbps = ON 0 Mbps = OFF Receive LED: blinks at 0 Hz when receiving, but not colliding Transmit LED: blinks at 0 Hz when transmitting, but not colliding Link LED: steady on when 00 Mbps or 0 Mbps link is okay and blinks during TX or RX activity if PRB bit 9 = 0 (default). The link LED will remain steady on and will not blink during TX or RX activity if PRB bit 9 =. Collision LED: blinks at 0 Hz to indicate a collision / Doc ID Rev
AN9 Typical application Typical application While the STE0P may be used in a variety of applications such as multi-port repeaters or switches, the application shown below gives a very simple way of evaluating and using the STE0P with minimum circuitry (see Table ). The application of the STE0P presented in Figure can be used to design a Fast Ethernet transceiver with a standard MII interface and a 0/00 Mbps twisted pair connector. In this application, STE0P is the only IC needed. It connects directly to the industry standard 0-pin MII connector. It also connects to the RJ- jack via a standard Fast Ethernet transformer. Jumpers JP-JP are used to select the PHY address. (More details on the PHY address registers, etc. are available on the STE0P datasheet) An -position DIP switch is used for determination of most of the pin-selectable options of the STE0P such as duplex mode, data rate and auto negotiation. Jumper JP disables Auto-MDIX. LEDs are included to indicate status information such as speed, duplex mode, transmit and receive activity and link status. STE0P also supports the MII MDIO access to all of its internal registers. There are normal registers with bits each supported for STE0P. (More details on these registers are available in the STE0P datasheet). There are also shadow registers for advanced chip control and status information. Doc ID Rev 9/
Typical application AN9. Schematics and bill of materials The schematics and the bill of materials for the sample application can be found on the following pages. Figure. Sample application schematic MII MII MII MII MII MII MII MII0 MII9 MII MII MII MII MII MII MII MII MII0 MII9 MII MII MII MII MII MII MII MII MII0 MDIX Disable RMII/SMII CLOCK SCLK supplied by MAC for RMII/SMII mode BYPASS CAPS RESET POWER MII0 MII MII MII MII MII MII MII MII MII MII MII MII MII MII MII9 MII0 MII MII MII MII MII MII MII [0..] MII0 CFG CFG0 SCLK CF mdix_dis RESET PWRDWN V.A V.A PWRDWN 0K RESET R C SCLK V MII MII V V.A C C 0.uF 0.uF AVDD AVDD AVDD R 0 V U 9 0 9 0 STE0P 0 9 0 9 R9 0 L BEAD 9 0 0 9 rx_clk gnd rx_er/rxd tx_er/txd tx_clk tx_en txd0 txd txd txd col crs mdint dvdd cfg cfg0 sclock cf mdix_dis rip reset pwrdwn test gnd gnda txn vcca txp gnda rxp rxn vcca mf mf mf mf mf0 fde gnda nc vcca gnda x x vcca gnda iref vcca rx_dv rxd0 rxd dvdd rxd rxd mdc mdio gnd ovdd ledr0 ledtr ledl ledc leds test_sel R K SW 0 SW DIP-/SM R0.K RIP D D D R 0K 9 9 0 9 0 U +V +V MII +V MDIO MDC RXD[] RXD[] RXD[] RXD[0] RXDV RXCLK RXER TXER TXCLK TXEN TXD[0] TXD[] TXD[] TXD[] COL CRS +V 0 9 0 MDINT R MF MF MF MF MF0 FDE 0 0K R-Pack Y Mhz JP PHYADD / LEDTR JP TP 9 9 J +V MDIO MDC RXD[] RXD[] RXD[] RXD[0] RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD[0] TXD[] TXD[] TXD[] COL CRS MII TEST R9.99K C C9 pf pf R R R R.K.K.K.K D D R 0K JP PHYADD / LED0 JP PHYADD / LEDL JP PHYADD / LEDC JP PHYADD0 / LEDS U TD+ TX+ CT CT TD- TX- RD+ RX+ 0 CT CT 9 RD- RX- HB R 0K R R R R J RJ C C C 0.uF 0.uF 0.uF R 0 ohm JP C0 uf C 0.uF C uf D PWR C C R uf 0.uF 0 C C uf uf R 0 R 0 JP C 0.00uF C C C0 C9 0.uF 0.uF 0.uF 0.uF R SW 0.uF L BEAD U0 REG. OUT IN C 0.uF R 0 0K 0/ Doc ID Rev
AN9 Typical application Table. Bill of materials Item Quantity Reference Part RIP, TP, V, MDINT,, AVDD TEST POINT C, C, C µf C, C, C, C, C, C, C, C, C, C9, C0, C, C 0. µf C,C9 pf C0, C µf C 0.00 µf D, D, D, D, D LTL-9 D LED 9 JP PHYADD / LED0 Jumper 0 JP PHYADD / LEDTR Jumper JP PHYADD / LEDL Jumper JP PHYADD / LEDC Jumper JP PHYADD0 / LEDS Jumper JP, JP, JP Jumper J MII TEST header J RJ L, L BEAD R, R, R, R, R9, R 0 Ohm 9 R, R, R, R, R0.K Ohm 0 R, R, R, R Ohm R K Ohm R, R, R, R, R 0K Ohm R9.99K Ohm R 0K R-Pack SW SW DIP-/SM SW SW TACT-SPST U MII connector U STE0P PHY 9 U.: transformer 0 U0 VREG. Tyco HB, Pulse H00 or Halo TG0-SN U Test connector Y MHz crystal Doc ID Rev /
Revision history AN9 Revision history Table. Document revision history Date Revision Changes -May-00 Initial release. / Doc ID Rev
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