CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output timing diagram (waveform) for single and combination of latches and flip-flops Troubleshoot basic flip-flops circuits 2 FKEKK 1
Terminology Multivibrator A class of digital circuits in which the output is connected back to the input (i.e. it is fed back to the input, commonly referred to as feedback) to produce either two stable states, one stable state, or no stable states, depending on the configuration. Bistable Having two stable states. Latches and flip-flops are bistable multivibrators Latch An asynchronous bistable multivibrator, used for storing 1 bit Flip-Flop A synchronous bistable multivibrator, used for storing 1 bit 3 Teminology (continue..) Asynchronous There is no fixed timing relationship Synchronous There is a fixed timing relationship, usually through the use of a clock pulse Edge-triggered Flip-Flop A type of flip-flop in which the input data are entered and appear on the output on the same clock edge, either the positive or negative edge 4 FKEKK 2
Introduction: Comparison between combinational circuits and sequential circuits Characteristics of combinational circuits are; Output depends only to current input No feedback from output of the system Unable to remember past values Logic gates AND, OR, XOR, NOT 5 Introduction (continue..) 6 FKEKK 3
Introduction (continue..) Multivibrator any digital circuit employing feedback. Sequential/Multivibrator devices are categorized as; Bistable Two stable states, SET and RESET Latches and flip-flops Monostable Has one stable state Timer Astable No stable state Oscillator (to generate periodic pulse waveforms for timing purposes. ) Fig: inverter with feedback 7 Latches Latches are bistable multivibrator A two stable states digital circuit that produces HIGH or LOW depending on the input For gated (enabled) latches, the output are controlled by the enable (EN) input It is level triggered, means that any input changes during the EN is active, the output will be affected The operation will be observed by examining the timing diagram 8 FKEKK 4
Latches (continue..) Four types; S-R latch S-R latch Gated S-R latch Gated D latch 9 S-R (Set-Reset) Latch Logic circuit Symbol Truth table 10 FKEKK 5
S-R Latch Timing Diagram 11 S-R (Set-Reset) Latch Logic circuit Symbol Truth table 12 FKEKK 6
S-R Latch Timing Diagram 13 Gated S-R Latch Logic circuit Symbol Truth table 14 FKEKK 7
Gated S-R Latch Timing Diagram 15 Gated D latch Logic circuit Symbol Truth table 16 FKEKK 8
Gated D Latch Timing Diagram 17 How does S-R latch works? By using DeMorgan s Theorem NAND gate Negative-OR gate The equivalent logic circuit 18 FKEKK 9
How does S-R latch works? (continue..) Assume that S = 0 and R = 1, therefore Q = 1 and Q = 0 Change both S and R to 1, therefore both Q and Q are still the same as previous value 19 How does S-R latch works? (continue..) Now, change S = 1 and R = 0, therefore Q = 0 and Q = 1 Change both S and R to 1, therefore both Q and Q are still the same as previous value 20 FKEKK 10
How does S-R latch works? (continue..) Now, set both input to 0, hence, both Q and Q are 1 which is invalid This state should be avoided since the changing state from invalid is unpredictable. Prove it!!! 21 Gated D Latch Exercises 22 FKEKK 11
Latch applications SR and D latches are among the simplest and least expensive types of memory elements used in logic circuits. Fig: Typical use of latches in a computer s input/output circuits 23 Edge-Triggered Flip-Flops Flip-flops are synchronous bistable multivibrator. Synchronous means the output changes state only occur at a triggering point called clock Edge-triggered can be either positive (rising) edge or negative (falling) edge of the clock Edge triggered flip-flops change state either at positive or negative clock Clock input for flip-flops 24 FKEKK 12
Edge-Triggered Flip-Flops (continue..) Four types; Positive-edge triggered Negative-edge triggered S-R flip flops D flip-flops J-K flip-flops T flip-flops 25 Edge-Triggered S-R Flip-Flop Positive-edge S-R FF 26 FKEKK 13
Edge-Triggered S-R Flip-Flop Exercises 27 Edge-Triggered D Flip-Flop Positive-edge D FF 28 FKEKK 14
Edge-Triggered D Flip-Flop Exercises 29 Edge-Triggered J-K Flip-Flop Positive-edge J-K FF 30 FKEKK 15
Edge-Triggered J-K Flip-Flop Exercises 31 Edge-Triggered T Flip-Flop Positive-edge T FF 32 FKEKK 16
Edge-Triggered T Flip-Flop Exercises 33 Latch and Flip-Flop Exercise Draw the output waveform for the JK flip flop and D latch whose input are as given 34 FKEKK 17
Master Slave Flip-Flops Introduced to overcome timing problem that might be occurred to flip-flop Two similar flip-flops are connected with different clock The output is stable even though input changes Qo Q1 35 Asynchronous Preset and Clear Most integrated circuit FF have asynchronous inputs These input change the FF output without clock triggering Normally label as preset (PRE) and clear (CLR) For example, take the T FF /PRE /CLR OUTPUT 0 0 Invalid 0 1 Q = 1 (Set) 1 0 Q = 0 (Reset) 1 1 Flip-flop normal operation 36 FKEKK 18
Flip-Flop Operating Characteristics Propagation Delay Times Required time interval for output signal to occur after an input signal has been applied CLK Q 50% CLK Q tphl tplh Set-up Time Minimum time interval for the signal to retain the value before clock pulse is triggered D CLK ts 37 Flip-Flop Operating Characteristics Hold time Minimum time interval for the signal to retain the value after clock pulse is triggered CLK D th Maximum Clock Frequency Highest rate at which a flip-flop can respond to the input signal fmax 38 FKEKK 19
Flip-Flop Operating Characteristics (continue..) Pulse Width Minimum clock pulse width is smallest time between HIGH and LOW Power Dissipation Total power consumption of the flip-flops For example, a 7474 chip has two D flip-flops which each of the flip-flop operates at +5Vdc and draws 5mA P = Vcc x Icc = 5 x 5 = 25mW P T = 2 x 25 mw = 50mW I = 50mW/5V = 10mA Therefore, the chip must be supplied by +5Vdc supply with at least 10mA of current. 39 Flip-Flop Applications Parallel data storage You will learn more in Chapter 3 40 FKEKK 20
Flip-Flop Applications (continue..) Frequency division 41 Flip-Flop Applications (continue..) Counting You will learn more in Chapter 2 42 FKEKK 21
Exercises (a) What is the difference between latch and flip-flop operation? (b) List 3 applications of flip-flops. Explain briefly each of the application of the flipflops. (c) Give the definition and describe the propagation delay time in flip-flop operating characteristics. 43 Exercises (Continue) (d) For negative edge triggered J-K flip-flop with preset (/PRE) and (/ CLR) inputs, determine the Q output for the input shown in the timing diagram in Figure Q1(d). Assume Q starts with 1 and the input J and K always 1. 44 FKEKK 22