Wire Delay and Switch Logic Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author
Topics Wire delay Buffer insertion Crosstalk Switch logic Modern VLSI Design: Chap3 2of 33
Wire delay Wires have parasitic resistance, capacitance Parasitics start to dominate in deep-submicron wires vgrowing wire delay compared to gate delay Distributed RC introduces time of flight along wire into gate-to-gate delay Modern VLSI Design: Chap3 3of 33
RC transmission line Assumes: v Dominant capacitive coupling is to ground v Inductance can be ignored Elemental values are r i, c i v All the transmission line section r s and c s are identical Modern VLSI Design: Chap3 4of 33
RC Elmore delay Can be computed as sum of sections: n δ E = Σ r(n - i)c = 0.5 rcn(n-1) i=1 Resistor r i must charge all downstream capacitors Delay grows as square of wire length Minimizing rc product minimizes growth of delay with increasing wire length vtherefore, use metal Modern VLSI Design: Chap3 5of 33
Wire sizing Wire length is determined by layout architecture vwe can choose wire width to minimize delay Wire width can vary with distance from driver to adjust the resistance which drives downstream capacitance(due to Elmore rule) Modern VLSI Design: Chap3 6of 33
Optimal wiresizing Widening the wire v Reduces the resistance v Increases its capacitance Wire with minimum delay has an exponential taper v Optimal tapering improves delay by about 8% Can approximate optimal tapering with a few rectangular segments source sink Modern VLSI Design: Chap3 7of 33
Tapering of wiring trees Different branches of tree can be set to different lengths to optimize delay source sink 1 sink 2 Modern VLSI Design: Chap3 8of 33
Spanning tree A spanning tree has segments that go directly between sources and sinks source sink 1 sink 2 Modern VLSI Design: Chap3 9of 33
Steiner tree A Steiner point is an intermediate point for the creation of new branches source Steiner point sink 1 sink 2 Modern VLSI Design: Chap3 10 of 33
RC trees Generalization of RC transmission line: Modern VLSI Design: Chap3 11 of 33
Topics Wire delay Buffer insertion Crosstalk Switch logic Modern VLSI Design: Chap3 12 of 33
Buffer insertion in RC transmission lines Assume RC transmission line vr int and C int are the total resistance and capacitance of the transmission line For driver vr 0 : driver s resistance vc 0 : driver s input capacitance Goal: Divide line into k sections of length l with buffers of size h Modern VLSI Design: Chap3 13 of 33
Buffer insertion analysis (Cont d) Assume h = 1: vk = sqrt{(0.4 R int C int )/(0.7R 0 C 0 )} gives the number of repeaters for minimum delay Assume arbitrary h: vk = sqrt{(0.4 R int C int )/(0.7R 0 C 0 )} vh = sqrt{(r 0 C int )/(R int C 0 )} vt 50% = 2.5 sqrt{r 0 C 0 R int C int } Modern VLSI Design: Chap3 14 of 33
Buffer insertion example Minimum-size inverter drives metal 1 wire of 2000 λ * 3 λ vr 0 = 3.9 kω, C 0 = 0.68 ff, R int = 53.3 kω, C int = 105.1 ff Then vk = 1.099 vh = 106.33 vt 50% = 9.64 E-12 Modern VLSI Design: Chap3 15 of 33
Topics Wire delay Buffer insertion Crosstalk Switch logic Modern VLSI Design: Chap3 16 of 33
RC crosstalk Crosstalk slows down signals vincreases settling noise Two nets in analysis: vaggressor net causes interference vvictim net is interfered with Modern VLSI Design: Chap3 17 of 33
Aggressors and victims aggressor net victim net Modern VLSI Design: Chap3 18 of 33
Wire cross-section Victim net is surrounded by two aggressors S W aggressor T victim aggressor H substrate Modern VLSI Design: Chap3 19 of 33
Crosstalk delay vs. wire aspect ratio relative RC delay increased spacing Increasing aspect ratio (W/T) Assume: T/H = 1 There is an optimum wire width (at bottom of U curve) for any given wire spacing Optimum width increases as spacing between wires increases Modern VLSI Design: Chap3 20 of 33
Topics Wire delay Buffer insertion Crosstalk Switch logic Modern VLSI Design: Chap3 21 of 33
Switch logic Can implement Boolean formulas as networks of switches Can build switches from MOS transistors; transmission gates Transmission gates have smaller layouts Modern VLSI Design: Chap3 22 of 33
Types of switches Modern VLSI Design: Chap3 23 of 33
Behavior of n-type switch n-type switch has source-drain voltage drop when conducting: vconducts logic 0 perfectly vintroduces threshold drop into logic 1 V DD V DD -V t V DD Modern VLSI Design: Chap3 24 of 33
n-type switch driving static logic Switch underdrives static gate, but gate restores logic levels Delay is increased V DD V DD -V t V SS /V DD Modern VLSI Design: Chap3 25 of 33
n-type switch driving switch logic Voltage drop causes next stage to turn on weakly V DD V DD -V t V DD -2V t V DD Modern VLSI Design: Chap3 26 of 33
Behavior of complementary switch Complementary switch produces full-supply voltages for both logic 0 and logic 1: vn-type transistor conducts logic 0 vp-type transistor conducts logic 1 Modern VLSI Design: Chap3 27 of 33
Layout characteristics Has two source/drain areas compared to one for inverter Doesn t have gate capacitance Modern VLSI Design: Chap3 28 of 33
Boolean functions and switches pseudo-and pseudo-or Modern VLSI Design: Chap3 29 of 33
Driving switch outputs If switch network output is not connected to power supply through switch path, output will float Switch network inputs may be connected to power supply or logic signals Modern VLSI Design: Chap3 30 of 33
Switching logic signals b a a b ab + a b Modern VLSI Design: Chap3 31 of 33
Switch multiplexer Modern VLSI Design: Chap3 32 of 33
Charge sharing Interior nodes in a switch network may not be driven Charge can accumulate on small parasitic capacitances Shared charge can produce erroneous output values At undriven nodes, charge is divided according to capacitance ratio v Make sure that for every input combination there is a path from the power supply to the output Modern VLSI Design: Chap3 33 of 33