Mixed signal systems and integrated circuits

Mixed signal systems and integrated circuits Akira Matsuzawa Tokyo Institute of Technology 9/28/2007 A. Matsuzawa 1

Contents Mixed signal systems High speed A/D converters High speed D/A converters Sigma delta A/D and D/A converters Wireless systems and RF CMOS circuits PLL and related systems 9/28/2007 A. Matsuzawa 2

Aim of this lecture Understanding basic current mixed signal systems Wireless transceiver Understanding basic mixed signal circuit building blocks: basic operation method and basic design method A/D and D/A converter Sigma-delta modulation Phase Lock Loop and Delay Lock Loop Low Noise Amplifier Frequency Mixer Voltage Controlled Oscillator and Frequency Synthesizer 9/28/2007 A. Matsuzawa 3

1. Mixed signal systems 9/28/2007 A. Matsuzawa 4

Current electronics and mixed signal technology 9/28/2007 A. Matsuzawa 5

Exciting digital consumer electronics world New consumer electronics era has been emerged. Key technologies are digital multimedia and System on a Chip. Broadcasting Communication Network Exciting Multimedia with System LSI Solutions Storage Media Anywhere Audio and Video Better Look Better Sound Higher Quality Media Processor Anytime Semiconductor Technology System and Software Technologies 9/28/2007 A. Matsuzawa 6

LCD Driver LCD driver is a simple example of mixed signal LSI LCD Drivers 9/28/2007 A. Matsuzawa 7

LCD Driver LCD driver is an array of DA converters Cotroler 6bit *R,G,B*2=36bit Start Carry #1 #2 #8 Shift Resigter 64 D00-07 D20-27 D40-47 D10-17 D30-37 D50-57 Flip- Flop Flip- Flop 6bits*3=18 6bits*3=18 selector 6 6 6 6 6 6 1 64 6bits*3=18 384 * 6 bits Latch 384 * 6 bits Latch 6 6 384 * 6 bits level shifter 384 * Voltage Scalling DA Converter 384 output XGA: 1024*RGB (=3072) 3072/384=8LSIs subpixel pixel 9/28/2007 A. Matsuzawa 8

Image of current electronics Digital consumer electronics and networking drive current electronics. DAB IEEE 1394, USB, Blue tooth, Wireless LAN CS/BS Digital TV ITS ADSL, FTTH Network HII Station Digital TV Ethenet Home network W-CDMA Home Server DVC DVD 9/28/2007 A. Matsuzawa 9

Mixed signal technology :Digital networking Mixed signal technology enables high speed digital networking. Data conversion Data and clock recovery Equalization Noise cancellation Encryption Error correction Analog Line I/F DAC DAC DAC DAC Pulse Shaping 6b, 125MHz ADC, DAC Digital TX1 TX2 TX3 TX4 Side-stream Scramber & Trellis,Viterbi Symbol Encoder 250Mbaud (PAM-5) ADC ADC Clock Recovery FFE Slicer DFE Side-stream Descramber & Trellis, Viterbi decoder Analog circuit Digital circuit Echo Canceller 3-NEXTCanceller 9/28/2007 A. Matsuzawa 10

x-dsl ADSL and VDSL use the mixed signal technology 9/28/2007 A. Matsuzawa 11

Mixed signal tech. ; Digital read channel Digital storage also needs high speed mixed signal technologies. Variable Variable Gain Gain Amp. Amp. Analog Analog Filter Filter A to to D Converter Converter Digital Digital FIR FIR Filter Filter Viterbi Viterbi Error Error Correction Correction Data Out Data In (Erroneous) Pickup signal Voltage Voltage Controlled Controlled Oscillator Oscillator Clock Clock Recovery Recovery Data Out (No error) Analog circuit Digital circuit 9/28/2007 A. Matsuzawa 12

Mixed signal SoC for DVD RAM system This enables high readability for weak signal from DVD RAM pickup. World fastest and highly integrated mixed signal CMOS SoC 0.18um- edram 24M Tr 16Mb DRAM 500MHz Mixed Signal Goto, et al., ISSCC 2001 9/28/2007 A. Matsuzawa 13

Mixed signal SoC Mixed signal SoC can realize full system integration for DVD application. Embedded analog is the key. 0.13um, Cu 6Layer, 24MTr CPU System Controller VCO ADC CPU2 Front-End Analog FE +Digital R/C PRML Read Channel Servo DSP AV Decode Processor Pixel Operation Processor IO Processor Gm-C Filter Back -End Analog Front End Okamoto, et al., ISSCC 2003 9/28/2007 A. Matsuzawa 14

Recent developed mixed signal CMOS LSIs 5G RF LAN 12b 50MHz ADC 2ch 12b 50MHz DAC 2ch Digital network 1394b (1GHz) AFE (Analog Front End) AFE for Digital Camera 12b 20MHz ADC+AGC AFE for ADLS 12b 20MHz ADC+DAC 2GHz RF CMOS 9/28/2007 A. Matsuzawa 15

Application area in mixed signal CMOS tech. Almost all the products need mixed signal CMOS LSI tech. Wireless Network Communication Recording Output Input Wired Cellular phone: PDC, W-CDMA RR-Net: Bluetooth, IEEE802.11 Broad cast: STB, DTV, DAB Optical:FTTH, OC-xx Metal: ADSL, VDSL, Power line modem Serial: IEEE1394, USB, Ethernet Parallel: DVI, LVDS DVD, VDC, HDD LCD, PDP, EL, Audio drive Camera, Others Power supply Switching supply, Every LSIs (On-chip) 9/28/2007 A. Matsuzawa 16

Digital technology in real world Digital signal suffers heavy damage in real world. But, digital can address this issue by own advantages, but needs the help of analog tech. Pure digital Advantages of Digital Tech. High robustness Programmability Time shift (memory) Error correction High Scalability Media (Cable, Disc, Air, etc) Mixed Mixed signal signal technology (Analog+Digital) Noise Distortion Interference Limited bandwidth Real world Damaged digital Reconstruction Not only digital, but also analog; ADC, DAC, Filter, and PLL are needed Recovered digital 9/28/2007 A. Matsuzawa 17

Role of current analog technology The role of current analog technology is an interface between digital technology and outer physical world. Analog supports digital. Clock Generation Analog Physical aspects Digital Meta-physics Outer world Wireless com. (Brain Wired com. Digital signal Processing and control Power supply Interface (Sense and actuate organ; Mouse, Eye, Ear, Nose, etc.) Energy conversion Recording Image Audio Motor Sensor (Digestive organ, Circulatory organ) 9/28/2007 A. Matsuzawa 18

Basic technology for digital network and storage Analog and data converter technologies are needed for digital network and digital storage Network Storage media Analog Processing Data Data Converter Communication Communication processing processing Data Data compression RF A/D Converter Optical I/F D/A Converter Cable drive Signal Generation Mod/ Demod Channel select Error correction Protocol Encryption MPEG2, 4 DSP Codec Analog technology Digital technology 9/28/2007 A. Matsuzawa 19

Development of ADCs for digital consumer products Performance Index Number Development of ADCs has contributed to the progress of digital consumer electronics. 100 50 20 10 5 2 1 Applied System 8b,120MHz 10b,20MHz Bip / BiCMOS CMOS Camera Digital OSC Video Switcher 10b, 30MHz 8b,20MHz 6b, 1GHz 10b, 20MHz, 30mW Digital OSC 10b, 300MHz Video Camera Wide-TV MUSE Receiver '85 '90 '95 6b,800MHz Perfec TV 9/28/2007 A. Matsuzawa 20 Digital Camera 6b, 80MHz 8b, 100MHz DVC DVD

Progress in A/D converter; video-rate 10b ADC ADC is a key for mixed signal technology. We have reduced the cost and power of ADC drastically; 1/ 2,000 in Power and 1/200,000 in cost! CMOS technology attained it. dulling past 20 years 1980 1982 Conventional product World 1 st 1993 Now Monolithic World lowest power SoC Core Board Level (Disc.+Bip) 20W $ 8,000 Bipolar (3um) 2W $ 800 CMOS (1.2um) 30mW $ 2.00 CMOS (0.15um) 10mW $0.04 Analog Devices Inc. Our development Our development Our development 9/28/2007 A. Matsuzawa 21

Power and area reduction of video-rate 10b ADCs Power and area of ADC have been reducing continuously. Currently, ADC can be embedded on a chip Power (mw) Power reduction 10000 5000 Flash Two-step 2000 Subranging 1000 Folding/Interpolating 500 Pipeline 200 Look-ahead Pipeline 100 Others 50 20 10 5 2 1 1980 1985 1990 1995 2000 2005 2010 Year Area size (mm2) Area reduction 100.0 Flash 50.0 Two-step 20.0 Subranging Folding/Interpolating 10.0 Pipeline 5.0 Look-ahead Pipeline Others 2.0 1.0 0.5 0.2 0.1 1980 1985 1990 1995 2000 2005 2010 Year 9/28/2007 A. Matsuzawa 22

Power and area reduction of video-rate 10b ADCs Power/MHz (mw/mhz) 100.0 50.0 20.0 10.0 Flash 5.0 Two-step 2.0 Subranging 1.0 Folding/Interpolating Pipeline 0.5 Look-ahead Pipeline 0.2 Others 0.1 0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 Process node (µm) Area size (mm2) 100.0 50.0 20.0 10.0 5.0 Flash 2.0 Two-step Subranging 1.0 Folding/Interpolating 0.5 Pipeline 0.2 Look-ahead Pipeline Others 0.1 0.1 0.2 0.3 0.5 0.7 1 2 5 10 Process node (µm) M. Hotta et al. IEICE 2006. June 9/28/2007 A. Matsuzawa 23

Early stage mixed signal CMOS LSI for CE Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI. This also enabled low cost and low power digital portable AV products. 1993 Model: Portable VCR with digital image stabilizing 6b Video ADC Digital Video filter System block diagram 8b low speed ADC;DAC 8b CPU 9/28/2007 A. Matsuzawa 24

Mixed signal system: Digital Camera Current camera system uses digital technology. 9/28/2007 A. Matsuzawa 25

Ultra-high speed ADCs Ultra-high speed ADCs have been developed. 8b, 120MHz, (1984 World fastest 8b ADC 8b, 600MHz ADC (1991 World fastest 8b ADC 6b, 1GHz ADC (1991 World fastest in production (Dual Parallel method 9/28/2007 A. Matsuzawa 26

Digital Oscilloscope Ultra-high speed ADCs have realized Digital Oscilloscopes. 10b 100MHz OSC (1986 8b 1GHz (1994 9/28/2007 A. Matsuzawa 27

Progress in high-speed ADC High speed ADC has reduced its power and area down to be embedded. World fastest 6b ADC ISSCC 2000 6b, 1GHz ADC 2W, 1.5um Bipolar ISSCC 1991 10 World fastest CMOS ADC Reported Pd of CMOS ADCs ISSCC 2002 6b, 800MHz ADC 400mW, 2mm 2 0.25umCMOS 9/28/2007 A. Matsuzawa 28 Pd/2 N [mw] World lowest Pd HS ADC 7b, 400MHz ADC 50mW, 0.3mm 2 0.18umCMOS 1 0.1 10mW/Gsps 1mW/Gsps This Work 1 order down 1 10 Conversion rate [x100msps]

System: DVD player Current electrical system is complicated and needs analog and memory. High-speed Analog-Digital Analog Optical Disc Optical Head Driver Head Amp Pre Amp Analog Front End Red Laser Photo-receptive Compound Red Laser Unit Read Channel CD DEM ODC Memory 4M DRAM Demodulation ECC AV Decoder Copy Protection 32bit MCU DRAM Embedded 16M SDRAM MPEG 2 Video AC-3 3 Audio Media Core Processor MPEG Algorithm Video Output AC-3 3 Output Stereo Output Servo DSP Servo DSP System Controller MCU System Controller MCU Console Panel First-Gen. Third-Gen. OS API Second-Gen. Fourth-Gen. 9/28/2007 A. Matsuzawa 29

Full DVD system integration in 0.13um tech. Advanced mixed signal SoC has been successfully developed. Okamoto, et al., ISSCC 2003 0.13um, Cu 6Layer, 24MTr CPU System Controller VCO ADC CPU2 Front-End Analog FE +Digital R/C PRML Read Channel Servo DSP AV Decode Processor Pixel Operation Processor IO Processor Gm-C Filter Back -End Analog Front End 9/28/2007 A. Matsuzawa 30

Cost reduction in DVD Recorder One-chip integration for hole DVD system has been realized. This makes circuit board simpler and contribute to the cost down, as well as performance up. 2000 Model 2003 Model 9/28/2007 A. Matsuzawa 31

Scaled CMOS technology Current Scaled CMOS technology is very artistic. Matsushita s 0.13um CMOS technology Gate SiO 2 Seven lattices Si 100nm Transistor Cu Interconnection 9/28/2007 A. Matsuzawa 32

CMOS as analog device CMOS has many issues as analog device, but also has a variety of circuit techniques Switch action ++ -- Low Input current ++ -- CMOS Bipolar Comment High gm - + CMOS is ¼ of Bip. Low Capacitance + - This results in Cp issue f T + + Almost same Only CMOS can realize switched capacitor circuits Voltage mismatch -- ++ CMOS is 10x of Bip. 1/f noise -- ++ CMOS is 10x to 100x of Bip. Low Sub. effect - + Offset cancel ++ -- Analog calibration ++ -- Digital calibration ++ -- Embed in CMOS ++ -- CMOS has a variety of techniques to address the self issues 9/28/2007 A. Matsuzawa 33

GHz operation by CMOS Cutoff frequency of MOS becomes higher than that of Bipolar. Over several GHz operations have attained in CMOS technology Frequency (Hz) 100G 50G 20G 10G 5G 2G 0.35um Cellular Phone 0.25um 0.18um CDMA 0.13um f T 5GHz W-LAN f T : CMOS f T : Bipolar (w/o SiGe) /10 (CMOS ) RF circuits f T /60 (CMOS ) Digital circuits f f T Tpeak gm 2πC vsat 2πL in eff 1G 500M IEEE 1394 D R/C for HDD 200M 100M 1995 2000 2005 Year 9/28/2007 A. Matsuzawa 34

CMOS technology for over GHz networking Digital consumer needs over GHz wire line networking. CMOS has attained 5Gbps data transfer. World first 1394b transceiver For 1Gbps networking 0.25um 3AL_CMOS Test chip for 5Gbps wire line 0.18um 4AL_CMOS 5Gbps Eye pattern 9/28/2007 A. Matsuzawa 35

Basic issue of analog in LSL technology Scaling can realize higher integration and higher speed yet low power for digital circuits. In contrast, analog performance is used to be degraded with scaling. Architectural and circuit technology development has been needed. Performance (Log) Scaling 1 Design Rule (Log) Integration Speed 9/28/2007 A. Matsuzawa 36 1 L 2 1 L 1.5 Dynamic range = 1.5 L 0.7x Scaling Rule Signal swing Noise + Mismatch+Distortion

Wireless systems The number of wireless standards are increasing PAN LAN Cellular PDC W-CDMA 2005 (384k) HSDPA GSM (14M) GPRS EDGE cdma2000 cdma2000-1x EV-DV 1x(144K) EV-DO(2.4M) (5.2M) IEEE802.20(4M) 4G PHS A-PHS IEEE802.11b 802.11a/g 802.11n (11M) (54M) (100M) ZigBee Bluetooth IEEE802.15 UWB 2010 Data rate 9/28/2007 A. Matsuzawa 37

Technology edge RF CMOS LSI Many RF CMOS LSIs have been developed for many standards Wireless LAN, 802.11 a/b/g 0.25um, 2.5V, 23mm 2, 5GHz Discrete-time Bluetooth 0.13um, 1.5V, 2.4GHz M. Zargari (Atheros), et al., ISSCC 2004, pp.96 K. Muhammad (TI), et al., ISSCC2004, pp.268 9/28/2007 A. Matsuzawa 38

Current status of RF CMOS chip RF CMOS was a university research theme, however currently becomes major technology in wireless world. Current products Bluetooth: 2.4GHz, CSR etc., major Wireless LAN: 5GHz, Atheros etc., major CDMA : 0.9GHz-1.9GHz, Qualcomm, becomes major Zigbee: 2.4GHz, not yet, however must use CMOS TAG: 2.4GHz, Hitachi etc., major Major Cellular phone standard, GSM uses SiGe-BiCMOS technology 9/28/2007 A. Matsuzawa 39

Why CMOS? Low cost Must be biggest motivation CMOS is 30-40% lower than Bi-CMOS High level system integration CMOS is one or two generation advanced CMOS can realize full system integration Stable supplyment and multi-foundries Fabs for SiGe-BiCMOS are very limited. Slow price decrease and limited product capability Easy to use Universities and start-up companies can use CMOS with low usage fee, but SiGe is difficult to use such programs. 9/28/2007 A. Matsuzawa 40

Multi-standard issue Reconfigurable RF circuit is strongly needed for solving multi-standard issue. Future cellular phone needs 11 wireless standard!! Multi-standards and multi chips IMT-2000 RF GSM RF IMT-2000 BB GSM BB Current Bluetooth RF GPS RF Bluetoth BB GPS BB MCU Power Unification Future Yrjo Neuvo, ISSCC 2004, pp.32 Reconfigurable RF DSP Unified wireless system 9/28/2007 A. Matsuzawa 41

Scalable circuit design for wireless systems Scalable and reconfigurable design is needed for addressing the multi-standard wireless systems Changeable: ADC/DAC resolution and bandwidth 9/28/2007 A. Matsuzawa 42

Basics of analog to digital and digital to analog conversion 9/28/2007 A. Matsuzawa 43

Basic mixed signal system Mixed signal systems has DSP, ADC, DAC, and pre/post filter basically. The signals are converted between time continuous and time discrete. Time continuous Time discrete Time continuous AGC Pre Filter (low pass) ADC DSP DAC Post Filter (low pass) Clock 9/28/2007 A. Matsuzawa 44

Sampling theory The signal has bandwidth of fm. Periodical sampling pulse has a period of T. Signal Voltage x(t) F(x(t)) Time Time domain -fm +fm Frequency domain Sampling Pulse j 1 T / 2 j v( t) = δ ( t nt ) T T v( t) = Vne, Vn = v t e dt T ( ) T / 2 n= Fourier expansion fc=1/t n= 2πnt 0 fc 2fc 3fc T: period 4fc Time domain Frequency domain V n = T 1 j2πn, 1 v( t) = T Qe n= e 2πnt = 1 2πnt j T 9/28/2007 A. Matsuzawa 45

Sampling Sampling process can be treated as the product of the signal and the sampling pulse Sampled signals have multi-sidebands at Nfc Signal x x(t) x(t) X(t)v(t) x( t) v( t) = n= x ( nt ) δ ( t nt ) x Time Sampling Pulse v( t) = n= δ ( t nt ) T: period v(t) Sampling F Time ( x( t) v( t) ) = X ( f ) ( X ( nfc + f ) + X ( nfc f )) n= 1 0 fc 2fc 3fc 4fc Frequency 9/28/2007 A. Matsuzawa 46

Frequency spectrum in sampled data. x t v t = πnt 1 j 1 2 ( ) ( ) x( nt ) δ ( t nt ) T πnt e v( t) = e = 1+ 2 cos Qcos x = n= T n= T n= 1 T 1 v( t) = ( 1+ 2cos( 2πfct ) + 2cos( 2 2πfct ) + 2cos( 3 2πfct ) +...) T 1 x( t) v( t) = ( x( t) + 2x( t)cos( 2πfct ) + 2x( t)cos( 2 2πfct ) + 2x( t)cos( 3 2πfct ) +...) T + e 2 2 jx jx Thus x(t)v(t) can be regarded as a AM modulated signal that the career signal of which frequency is nfc and the modulated signal is x(t) If simply assuming x(t) is single tone: x o cos (2 f a t) Sampled signal has a sideband of +/- f a at around nf c xo = x( t) v( t) cos T n= ( 2πfat ) + 2 cos( 2πfat ) cos( 2πfct ) 1 Qcos Acos B = 1 2 ( cos( A + B) + cos( A B) ) xo = cos T n=1 ( 2πf ) + ( cos( 2 ( + ) ) + cos( 2 ( ) )) at π nfc fa t π nfc fa t 9/28/2007 A. Matsuzawa 47

Signal reconstruction from sampled data F If signal bandwidth is less than fc/2, signal can be reconstructed perfectly. ( x( t) v( t) ) = X ( f ) + { X ( nfc + f ) + X ( nfc f )} Low pass filter n= 1 Nyquist condition F(x(t)v(t)): Fourier transform of x(t)v(t) X(f): Fourier transform of the analog signal fc/2 f m < f 2 c Signal non-overlap 0 fc 2fc fm fc+fm 2fc+fm fc-fm 2fc-fm fm f 2 c Signal can be separated to reconstruct Signal overlap 0 fc 2fc fm fc+fm fc-fm 2fc-fm 2fc+fm Signal can not be separated 9/28/2007 A. Matsuzawa 48

Reconstruction from sampled signals Sampled signal can be reconstructed to be continuous signal through low pass filter. Sampled signal Ideal Low pass filter Reconstructed signal 0dB x(t) x Pass Stop x Time Sampled signal: x( t) v( t) = n= x ( nt ) δ ( t nt ) c/2 Time Angular frequency Ideal Low pass filter: ωc 1 ω G( ω ) = 2 y( t) = ωc x( nt ) v( t nt ) 0 ω > n= 2 v( t) = ( πfct) sin πfct For the unit impulse signal y t = sin ( ) x( nt ) n = π ( πfc( t nt )) fc( t nt ) 9/28/2007 A. Matsuzawa 49

Reconstruction by sampling function Signal can be reconstructed by the convolution between sampling signal and sampling function. Original signal S( t) = ( πfct) sin πfct Sampling T = 1 fc Sampling function y( t) = x( nt ) S( t nt ) = n y t = sin ( ) x( nt ) n= π ( πfc( t nt )) fc( t nt ) Reconstruction 9/28/2007 A. Matsuzawa 50

Aliasing effect Signals of which frequencies are higher than fc/2 are folded to the lower frequencies L.T. fc/2. Nose which spreads wide frequency is also folded to lower frequency and accumulated. Low pass filter is needed Noise Caution!! Frequencies are folded Sampled signal is conventionally Noisy f f alias alias = = f sig nf ( n + 1) f c f : nf sig c : f sig < ( 2n + 1) 2 ( 2n + 1) f c 2 f f c sig < ( n + 1) fc Accumulated Noise 9/28/2007 A. Matsuzawa 51

Special technique: Under sampling By using under sampling technique, we can obtain modulated signal from very high carrier frequency. However, very low SNR due to noise accumulation. Under sampling technique 2GHz carrier 8MHz signal Bandwidth is 8MHz 20MHz sampling fc=20mhz 2GHz Carrier 9/28/2007 A. Matsuzawa 52

Reconstruction process Reconstructed signals has also folding frequency components. Thus DAC need post low pass filter. The interpolation technique can relax the required LPF spec. Interpolated signals Sampled signals Required LPF spec. Conversion period Conversion frequency Reconstructed signals and interpolation Folding noise Original signal Spectrum of reconstructed signals Folding noise Spectrum of over sampled signals 9/28/2007 A. Matsuzawa 53

Aperture effect in DAC Due to the aperture effect, the higher frequency component of the output signal from DAC Is decreased. Sometime some technique is needed. Ideal impulse train Actual Step pulse train in DAC output x DSP DAC x Time Time Signal intensity Aperture effect f sin π fc A( f ) = f π fc Frequency characteristics of DAC High frequency signal of DAC is decreased Use aperture correction filter that has inverse frequency characteristics. Reduce the pulse width by using small duty pulse Increase the conversion frequency using over sampling technique 9/28/2007 A. Matsuzawa 54

Frequency spectrums in ADC and DAC Input signal to ADC Folding Signal in ADC and DSP Re-folding Signal from DAC without the aperture effect Aperture effect Signal from DAC with the aperture effect 9/28/2007 A. Matsuzawa 55

Quantization ADC has a finite resolution number and the signal is quantized. This causes error called quantization error. Analog to Digital Converter Ideal line + Digital output Minimum step (1LSB) Quantization step Input signal Quantization noise Quantized signal Quantized signal = Input signal + Quantization noise Ideal quantization error Analog input Effective full-scale Nominal full-scale LSB (Least Significant Bit) 0 to 2 N -1 0 to 2 N Quantization error 9/28/2007 A. Matsuzawa 56

Quantization noise and SNR Quantization causes noise and this noise power reduces with increase of resolution number. Principal signal to noise ratio (db) of N bit ADC is about 6N+2. The higher resolution of ADC realizes the higher SNR for signal processing. Ideal quantization error Probability density of quantization error Signal intensity Full scale: S N = 2 q Noise power N Signal power 1, p( x) = q 0, x 0.5q x > 0.5q 1 ( 3 2 0.5q 2 q q = x p x) dx = 0.5q S = N 1 2 q 2 2 Signal to Noise Ratio 2 2 Step: q S SNRrms / rms = 10log N = 6.02N + 1.76( db) q = 20log 2 N + 10 log(1.5) 9/28/2007 A. Matsuzawa 57

SNR increase by increasing fsc We can increase SNR by increasing of conversion frequency with low pass filter. Signal =2MHz Conversion clock Quantization noise 2x conversion rate Noise After LPF Signal =2MHz fc/2 =5MHz fc= 10MHz Frequency Conversion clock Half noise power Is removed Quantization noise Total Noise power is same, but power density is lower SNR 3dB higher SNR by 2x higher fc rms / rms = 6.02N + 1.76 + 10log fc 2 f b fc: Conversion frequency fc/2 fc= fb: Bandwidth of LPF fb=5mhz =10MHz 20MHz Frequency 9/28/2007 A. Matsuzawa 58