Digital Systems Laboratory 1 IE5 / WS 2001

Digital Systems Laboratory 1 IE5 / WS 2001 university of applied sciences fachhochschule hamburg FACHBEREICH ELEKTROTECHNIK UND INFORMATIK digital and microprocessor systems laboratory In this course you are going to work out four labs. The topics of the labs relate directly to the corresponding course DS. The digital designs have to be developed and implemented in hardware with XILINX-Foundation software tool. The design entry will be performed with VHDL coding. All developments will be implemented with XILINX-CPLD XC9500 hardware. This outline gives information about the recommended reading, the necessary lab preparation, the work library of the development PCs and the final documentation. You will have to work with the following handouts: 1. Lab descriptions which are listed in the table. 2. Instructions to handle XILINX-Foundation. This is a red line paper with information about the software icons you have to choose for design development steps. 3. Instructions to work with the VHDL simulator ModelSim XE. 4. Course handout XILINX XC9500 CPLD Device Architecture. Survey to four labs during WS 2001 (please remark the special time scheduling for November/December): Lab no. Topic 1 Design of a traffic light controller for a pedestrian crossing. Lab goals: Implementation of a finite state machine (FSM) in interconnection with a controlled counter. 2 Design of a controlled 8-bit shift register. Lab goals: Implementation of a parallel-load / serial-parallel converter. 3 Design of a 8-bit serial two's complementer. Lab goals: Implementation of a synchronously clocked system which consists of four connected components. 4 Design of a simple controller/data path architecture for the serial two's complementer which receives a 10-bit input word: start bit, 8 data bits, stop bit. Lab goals: Implementation of a digital system which is build up by components and handshake interfacing: FSM controller and a data path unit (DPU). Recommendations for lab preparation! Each lab has to be prepared appropriately in order that you are able to: present a written/drawn concept for the digital circuit, present a VHDL model (compiled *.vhd file on a disk) for the design you have to implement, present a concept for the hardware verification. Important notes which have to be reminded during the labs: Start to login to the lab PC with the local PC name (DIP<number of PC>). You don t need to login with a password. You have to copy your VHDL design files into the work directory C:\Fndtwrk. You are not allowed to change any existing path or implement any new work directory. With each start of the PC a new work directory c:\fndtwrk will be created. This prepared work directory contains several useful files (*.ucf; seg7.vhd;*.do; *.cmd). You should not expect that your development results will be available on the PC at the next day. Therefore you should use the file fi archive project option in XILINX-Foundation tool. Please remember that VHDL filenames and the including entity names should be identically in order to avoid misunderstandings of information yielded by the software tools. You have to choose entity, project, and command file names with less or equal 8 characters, because otherwise design implementation may cause problems. No a, u, o are allowed for proper operation. 1 SWR 01 1

During all labs the development results have to be verified by VHDL or timing simulations before design implementation will be tested. You have to edit appropriate *.cmd or *.do command files because design debugging will be more efficient. Guide through the lab records (write-ups): Each lab has to be accomplished by a documentation. Following parts should be included: You have to explain the development of block diagrams, decision charts, state diagrams, ASM charts, logic functions and VHDL code semantics. The meaning of all VHDL signals and variables have to be made plausible, i. e. with identically named interconnection lines in a speaking block schematic. In order to convince with your lab results you have to add comments on all command files, simulation timings, with which you have tested your design. We also expect comments on all element groups of the schematics or logic equations (i. e. combinational logic, unexpected latches, flip-flops and three-state drivers). Pinout of the implemented digital circuit. Finish the lab documentation with a schematic of the complete test system (device under test, signal generator and oscilloscope). 2

university of applied sciences fachhochschule hamburg FACHBERCH ELEKTROTECHNIK UND INFORMATIK digital and microprocessor systems laboratory Student group: Professors comment: Record editor: Date: Group members: Professor: 1. Lab: Traffic Light Controller The controller for traffic lights at a pedestrian crossing has to be developed. A pedestrian who wants to cross a road has to push a button (PB) at a traffic light sign post. A sequence of light changes gives green or red lights to the pedestrian (PEGR, PDRE) and green, yellow or red lights to the drivers directions (DRGR, DRYE, DRRE). The sequence of traffic light states is described with table 1. The number of cycles of a chosen clock period determines the duration of each state. A sequence controller has to be build up with a synchronous Mealy state machine. The FSM will be switched on State PB Function Cycles DRRE DRYE DRGR PDRE PDGR S0 0 Initial state, waiting 0 0 0 0 0 S1 was 1 Push button has been pressed, system switched on 5 0 0 1 1 0 S2 X Drivers direction yellow 2 0 1 0 1 0 S3 X Drivers dir. red 5 1 0 0 1 0 S4 X Pedestrians dir. green 30 1 0 0 0 1 S5 X Pedestrians dir. red 10 1 0 0 1 0 S6 X Drivers dir. red/yellow 2 1 1 0 1 0 S7 X Drivers dir. green 15 0 0 1 1 0 Table 1: Sequence of traffic light states and number of clock cycles. with the pedestrians push button PB. The duration of each state has to be controlled by a synchronous 5-bit counter (Q[4:0]). Parallel to the next state calculation (Si / Si+1) the counter is reset synchronously by the FSM output CLR. In order to reduce the number of CPLD macrocells a state encoding has to be chosen which is described by the following state diagram. reset Reset 0xxxx/0 x00100/1 x00001/1 x00100/1 1xxxx/0 x00100/0 x00001/0 000000 000110 001010 010010 x01110/0 100110 x00001/0 111010 x01001/0 110010 x11101/0 110001 x01110/1 x00001/1 x01001/1 x11101/1 B 5 DRRE DRYE DRGR PDRE PDGR PB Q4 Q3 Q2 Q1 Q0/ CLR 3

The development should begin with a block diagram which describes all interfaces of two components. Both components have to be modelled and tested separately. The traffic controller system has to be described then with a structural model which contains instantiations of both components. Template of a structural model with components: -- Template for a structural model entity TRAFFIC_CONTROL is -- external ports. port(reset, CLK, PB : in bit; OUTP : out bit_vector(4 downto 0)); end TRAFFIC_CONTROL; architecture STRUCTURE of TRAFFIC_CONTROL is signal CLR_I: BIT; signal Q_I: BIT_VECTOR(4 downto 0); -- component-declaration: used IC-type component COUNTER_T_C port( CLR, CLK : in BIT ; QOUT : out BIT_VECTOR ); end component; component LIGHT_CONT -- light controller Mealy-FSM port( RESET, PB, CLK : in BIT ; COUNT : in BIT_VECTOR(4 downto 0); CLR : out BIT ; LIGHTS: out bit_vector(4 downto 0)); end component; begin -- component instantiation: socket interfacing INST_1: COUNTER_T_C -- connector of component => internal signal or external interface port map(clr => CLR_I, CLK => CLK, QOUT => Q_I); INST_2: LIGHT_CONT port map(reset => RESET, PB => PB, CLK => CLK, COUNT => Q_I, CLR => CLR_I, LIGHTS => OUTP); end STRUCTURE; Single Steps Develop a 5-bit counter VHDL code with a synchronous reset and symbolic signal delays (after 20 ns) in signal assignments. Counter Develop a two-process FSM model VHDL code. FSM Develop a structural VHDL model as described above. Synthesis and design implementation. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim and check the signal propagation from clock edge to selected outputs. Build up the device under test with an XS-95 board. Connect the control signals to the traffic light model. Measurements of signal propagation delay has to be performed. Documentation VHDL code and a corresponding decision chart. VHDL code and a block diagram. VHDL code and corresponding block diagram. Pin out and comments on logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 4

university of applied sciences fachhochschule hamburg FACHBERCH ELEKTROTECHNIK UND INFORMATIK digital and microprocessor systems laboratory Student group: Professors comment: Record editor: Date: Group members: Professor: 2. Lab: 8-Bit Parallel-Load Shift Register A Johnson counter contains the basic structure of a shift register which is made up by a chain of D-FFs. Beginning with the LSB of a register (a number of D-FFs) each D-FF output can be connected to the data input of the D-FF with next higher weight. This chain of D-FFs includes the ability to shift the bits of the register to the left (LSB to MSB) or to the right (MSB to LSB). For example, a sequence of bits can be converted into a word by shifting the bits into a register and moving the bits along at each clock edge. After a sufficient number of clock edges, namely the number n of D-FFs, the n bits of a word are available as a single word. This is known as serial-in, parallel-out register. During the shift processing all bits which have been stored before will be lost. Applications of shift registers will be found in serial communication interfaces. The receiver input device will clock in a data stream of sequenced bits and a parallel word will be accessed by internal processes. A sender will clock out a parallel stored word over a serial register output. Simple multiply and division operations can be performed by a shift register. A multiplication by two will be done with a shift left by one bit. A VHDL-module which models a shift register type SN74HC166 has to be implemented with a CPLD XC95108 (compare attached TI data sheet pages). Describe the main functionality with a clocked process. The priority of control inputs is described by the data sheet function table. Start with development of a decision chart which resumes following order of input signal checking: 1. Asynchronous and low active clear. 2. Clock edged check of an internal signal which is build up with an ORing of two inputs clock CLK and clock inhibit CLK INH. 3. Synchronous load with SH_LD_N = 0. 4. Shift enable with SH_LD_N = 1. Shift of serial input SER from LSB to MSB output QH which means shift left. Therefore you should use the label SEL for serial data input. Additional requirements: 1. All 8 register bits should be accessible at the module output. 2. Append a controlled tristate output driver to the all register outputs. The enable signal should be EN. In order to apply a high impedance state the IEEE-library has to be included to the VHDL code (compare counter lab DC I) and the signal type std_logic has to be used. Implementation advice: The shift left operation can be done by taking the lowest (8-1) bits of Q[7:0] and concatenating the serial input bit SEL to the LSB position and assign it to Q[7:0]. Pseudo-random generator (PSRG, compare J. Wakerly: Digital Design; page 730-733): Another shift register or ring counter application that is simple in terms of next state logic is the linear feedback shift register (LFSR). The next state logic is formed by XOR gates. The sequence of states appears to be random. In order to avoid a stop of sequence an appropriate set condition has to be applied and a self correcting circuit has to be connected to the load input. 5

Single Steps Develop a shift register VHDL code according to the datasheet. Append a tri-state driver process to the shift register VHDL code. Develop a LFSR VHDL code with signal feedback from the shift register output. Synthesis and design implementation of the shift register with tri-state outputs. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim and check the signal propagation from clock edge to selected outputs. Build up the device under test with an XS-95 board. Connect the shift register signals to an external LED device.. Documentation VHDL code and a corresponding decision chart. VHDL code and a block diagram of both components. VHDL code and block diagram. Pin out and comments on logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 3. Lab: Serial Two's Complementer 6

university of applied sciences fachhochschule hamburg FACHBERCH ELEKTROTECHNIK UND INFORMATIK digital and microprocessor systems laboratory Student group: Professors comment: Record editor: Date: Group members: Professor: A Mealy state machine (FSM) receives an serial bit stream X which consists of 8-bit blocks without any separating bits. The data bits are supplied to the circuit synchronously beginning with the LSB. Serial two's complementing (X Y) is performed by the FSM according to the following algorithm: Appearing zeros X = 0 will be copied to the output Y= 0. The first detected one X = 1 will also be copied Y = 1. All other following bits after the first one have to be inverted Y = X. Examples : 1. X = 0 1 1 0 0 1 0 1 (LSB) 2. X = 1 1 1 0 0 0 1 0 (LSB) Y = 1 0 0 1 1 0 1 1 Y = 0 0 0 1 1 1 1 0 System operation according to figure 1: The output bit stream Y of the Mealy state machine FSM will be registered by a 8-bit shift register SRG_8 (shift right). After the 8 th bit (MSB) has been shifted into the SRG_8 the full 8-bit data word will be stored by a 8-bit data buffer D_B with the next clock edge. Concurrently to this process of shifting a 3-bit counter C_3B is counting all bits of the received 8-bit blocks. From the counter RCO signal an unknown block? derives the store enable signal LOAD. The unknown function LOAD = f(rco) has to be identified. From the start all synchronously clocked components receive an asynchronous reset. When the sender retrieves the reset it will connect the first LSB to the X input of the FSM. With the next clock edge the 2 nd bit is available and after the MSB has appeared all 8-bit blocks will follow in a closed sequence. X Y 8 8 FSM SRG_8 D_B SHIFT_REG DATA CLK 3 COUNT C_3B RCO? LOAD Figure1: Block diagram of the serial two's complementer with four synchronously clocked components. Lab preparation: a) Develop a Mealy state diagram which describes the two's complementer FSM. Derive a two process state machine VHDL code. b) Develop appropriate VHDL codes for all other components (comp. figure 1) accordingly to the VHDL templates you have experienced during the DC I and DS courses. c) The system verification shall be performed by a synthezisable testbench VHDL code. This testbench SRG_TB is build up by a shift register which shifts out to the left a stream of 24 bits. The MSB of the SRG_TB is connected to the X input of the FSM. The global asynchronous reset is connected to the SRG_TB as well. 7

Single Steps Develop a two process FSM VHDL code. Connect all VHDL codes (figure 1) in one design entity including the testbench shift register Synthesis and design implementation of the complete design entity. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim. Build up the device under test with an XS-95 board. Connect the DATA signal vector and the LOAD signal to an external LED device. Documentation VHDL code and the corresponding state diagram. VHDL codes. Table with a proof of the two's complementer operation. Pin out and comments on logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 8

university of applied sciences fachhochschule hamburg FACHBERCH ELEKTROTECHNIK UND INFORMATIK digital and microprocessor systems laboratory Student group: Professors comment: Record editor: Date: Group members: Professor: 4. Lab: Controller/ Path Architecture The serial two's complementer we have dealt with in lab 3 has to be completed in order to develop a more practical receiver device for synchronous communication. Now the data bit stream consists of 10 bits: 1 start bit (low level), 8 data bits (LSB first), 1 stop bit (high level) (comp. figure 1). If the sender line is deactivated the line level will be high X = 1. With this kind of defined bit frame the receiver operation can be designed more self controlled. CLK bits Start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Stop bit Figure 1: bit frame with a leading start bit (low level) and an appended stop bit (high level). Now the FSM can become the controller of all receiver system components (comp. figure 1 lab 3). A beginning communication is identified by the FSM with a first high low transition on X. With the next clock edge the FSM will perform a transition from its waiting state to the receiving state. With the transition to the receiving state the FSM will set the enable signals to the bit counter C_B and to the shift register SRG_8. When the bit counter has incremented up to 8 all data bits have been shifted into the SRG_8. With the counter state 8 and a stop bit high level is identified the load signal to the data buffer D_B can be set immediately by the FSM. The 8 data bits will be loaded into the data buffer with the next clock edge and a FSM state transition to the waiting state takes place. If no correct stop bit appears no loading will happen and the shifted data will be lost. In such a case an error signal can be send back to the sender. During the waiting state a synchronous reset signal is generated by the FSM and connected to the bit counter and the shift register. Lab preparation: a) Draw a block diagram with all interfacing between the FSM controller and all other components of the data path. The bit counter RCO signal should be connected to the FSM which reduces the number of interface lines. Mark control and status signals. b) Develop a state diagram which describes the two's complementer FSM with additional control outputs. Derive a two process state machine VHDL code. c) Develop appropriate VHDL codes for all other components of the drawn block diagram. d) The system verification shall be performed by a synthezisable testbench VHDL code. This testbench SRG_TB is build up by a shift register which shifts out to the left a stream of 24 bits. The MSB of the SRG_TB is connected to the X input of the FSM. The global asynchronous reset is connected to the SRG_TB as well. 9

Single Steps Develop a two process FSM VHDL code. Connect all VHDL codes (block diagram) in one design entity including the testbench shift register Synthesis and design implementation of the complete design entity. Apply implementation options : Simulation: ModelSim VHDL Timing simulation with ModelSim. Build up the device under test with an XS-95 board. Connect the DATA signal vector, the LOAD signal and the state D-FF outputs to an external LED device. Documentation Block diagram of the controller/data path structure. FSM VHDL code and the corresponding state diagram. VHDL codes. Table with a proof of the two's complementer operation. Pin out and comments on logic equations, check the *.rpt file. result print out and comments on worst case signal delays. Hand drawing of used equipment and measured signals. The results have to be explained to the professor or to the technical assistant. 10