a AN-605 APPLICAION NOE One echnology Way P.O. Box 906 Norwood, MA 006-906 el: 7/39-4700 Fax: 7/36-703 www.analog.com Synchronizing Multiple AD95 DDS-Based Synthesizers by David Brandon INRODUCION Many applications require the generation of two or more sinusoidal or square wave signals with a known phase relationship between them. he AD95 DDS IC from Analog Devices is capable of providing such signals. his application note offers detailed instructions on how to synchronize two or more of these devices and considers possible sources of phase error. For a quadrature application, see the AD954 DDS with its built-in quadrature configuration; however, this application note would also apply to the AD954 as well. OPIMUM LAYOU A = B = C DDS NO. A B DDS NO. C DDS NO. 3 For successful synchronization, the user must have control over the timing relationship between and the rising edge of the EX I/O UPDAE CLK. he goal is to have all DDSs operating on the same SYSEM CLK count and not off by ± or more counts from each DDS. herefore, the EX I/O UPDAE CLK must be made synchronous with the. DDS NO. DDS NO. DDS NO. 3 For phase errors due to DAC output filtering mismatches, the AD95 features programmable phase adjust that can null out these types of mismatches. REF CLOCK he first requirement for successful synchronization of multiple AD95s is that there must be minimal phase error between the inputs to all DDSs. Any difference in-phase between the edges will result in a proportional phase difference at the DDS outputs. herefore, the user must employ a careful clock distribution practice in the layout of the PCB (see Figure ). he AD95 input circuitry has an option of using differential inputs or a single-ended configuration. Differential mode is recommended for its optimum switching characteristics. he edges should have minimum input jitter and fast rise/fall times (less than ns is recommended). A slow rise time on can increase the phase error time because the voltage trip point of the input circuit varies from device to device. Figure. Distribution I/O UPDAE CLOCK he I/O UPDAE CLK is responsible for transferring the contents of the I/O port buffer to the programming registers where the data becomes active. his clock has two modes of operation in which the DDS can supply the I/O UPDAE CLK, or the user can supply it. For synchronization reasons, external mode is highly recommended. Internal mode was not given consideration for complexity reasons. AD95 I/O INERFACE DEAILS Once a fast-edged and properly routed signal is provided, the next timing requirement is the coincident transfer of the data into the DDS programming registers. he I/O UPDAE CLK transfers the contents of the I/O port buffer to the programming registers where data becomes active. Synchronization of multiple DDSs requires that the EX I/O UPDAE CLK s rising edge occur simultaneously at all DDSs, just like the. In addition, the rising edge of the EX I/O UPDAE CLK must occur at the proper time with respect to. 003 Analog Devices, Inc.
he AD95 can be programmed in serial or parallel mode. Figure depicts the parallel mode. If shown, the serial mode would display an additional 7-bit shift register and other support circuitry in front of the parallel data path. However, the main reason for showing this diagram is to view the paths of and EX I/O UPDAE CLK. A few things to note in Figure are how the SYSEM CLK is derived and the inversion of in singleended mode. Also note, an asynchronous EX I/O UPDAE CLK will be made synchronous to the SYSEM CLK via the edge detection circuitry (see Figure 3). However, it is incumbent upon the user to make it synchronous with the to avoid a SYSEM CLK count mismatch between DDSs. Depending on the setting of the mode (singleended or differential) and/or the use of the on-chip multiplier (PLL), the timing relationship between and EX I/O UPDAE CLK will change. hese timing changes will be addressed later. I/O POR BUFFERS ADDRESS PROGRAMMING REGISERS DAA RD 6 READBACK MUX 30 ADDRESS WR 6 D E C O D E 40 OF 40 OF 40 D L A C H EN UPDAE REGS (SEE IMING FOR EDGE DEEC BELOW) 0 M U X OF 40 D Q F/F CK DDS EX I/O UPDAE CLOCK EDGE DEEC B DIFFERENIAL MODE M U 0 X MULIPLIER 0 M U X DIFF/SINGLE SYSEM CLOCK Figure. AD95 Parallel Interface Block Diagram I/O POR BUFFERS CONENS ARE REGISERED INO PROGRAMMING REGISERS FIRS SYSEM O SEE EX I/O UPDAE CLK FORMS RISING EDGE OF UPDAE REGS FORMS FALLING EDGE OF UPDAE REGS SYSEM CLK 0 3 EX I/O UPDAE CLK UPDAE REGS Figure 3. Ext I/O Update CLK's Edge Detect iming
From the timing in Figure 3, it is essential that a proper time relationship exist between EX I/O UPDAE CLK and the SYSEM CLOCK for synchronization to occur. If this time relationship is met, then all SYSEM CLOCKs are on the same count across all DDSs and not off by ± or more SYSEM CLOCK counts. he user would control this relationship with the control of the rising edge of the EX I/O UPDAE CLK with respect to the. his timing relationship will be addressed in the SYNCHRO- NIZAION INSRUCIONS section. RESE BACKGROUND A RESE must be given after power-up and prior to transferring any data to the DDS. his places the DDS output into a known phase, which becomes the common reference point that allows the synchronization of multiple DDSs. RESE forces the AD95 s phase accumulator state to become COS(0). When new data is sent simultaneously to multiple DDSs, a coherent phase relationship can be maintained, or the relative phase offset between multiple DDSs can be predictability shifted by means of the phase offset adjustment register. he AD95 has 4 bits of phase-offset adjustment that amounts to a phase resolution of 0.0. he phase-offset feature is located between the phase accumulator and the phaseto-amplitude converter. SYNCHRONIZAION INSRUCIONS Figure 4 presents one possible reference design for the successful synchronization of multiple DDSs. his example shows how to place two DDSs into the same phase relationship. In Figure 4, the D flip-flop enables the EX I/O UPDAE CLK to be synchronous with the and provides a setup time. Proper operation may require additional time delay in the path. his delay depends on the CK to Q propagation time of the flipflop. he recommended timing relationship between the EX I/O UPDAE CLK (Pin 0) and the (Pin 69) is depicted in Figures 5 and 6, depending on single-ended or differential mode. iming for the multiplier enabled is depicted in Figures and 9. Here are some general instructions and recommendations for placing two DDSs into the same phase relationship (refer to Figure 4). Note that there are two sets of instructions, with and without the multiplier enabled. Instructions (without the AD95 s multiplier enabled) to synchronize two DDSs.. Power up all devices and apply the common.. Send a common RESE with a minimum high time of 0 periods. 3. Program all DDSs for EX I/O UPDAE CLK mode (bypass digital multipliers and inverse sync, if desired). 4. Program DDS No. to the desired frequency and a phase offset of 0 without issuing an EX I/O UPDAE CLK. 5. Program DDS No. to the exact same frequency and a phase offset of 0 without issuing an EX I/O UPDAE CLK. HREE SAE EX I/0 UPDAE CLK RESE MICROPROCESSOR OR FPGA WRB NO. WRB NO. DELAY CK D FLOP EN D Q DAA/ADDRESS BUS AD95 NO. DAA/ADDRESS WRB EX I/O UPDAE CLK RESE RESE EX I/O UPDAE CLK WRB AD95 NO. ZERO PHASE DIFFERENCE DAA/ADDRESS Figure 4. Application Circuit 3
EX I/O UPDAE CLK MUS OCCUR WIHIN HIS RANGE (PIN 69) EX I/O UPDAE CLK (PIN 0) VALID 0.5ns.ns AVOID HESE WINDOWS OF IME WIH RESPEC O HE RISING EDGE OF HE EX I/O UPDAE CLK AND HE RISING EDGE OF NOE: EX I/O UPDAE CLK'S RISING EDGE IMING IS RELAIVE O 'S RISING EDGE. Figure 5. Proper iming Relationship between and EX I/O Update CLK in Differential Mode EX I/O UPDAE CLK MUS OCCUR WIHIN HIS RANGE (PIN 69) EX I/O UPDAE CLK (PIN 0) VALID.5ns AVOID HESE WINDOWS OF IME WIH RESPEC O HE RISING EDGE OF HE EX I/O UPDAE CLK AND HE FALLING EDGE OF NOE: EX I/O UPDAE CLK'S RISING EDGE IMING IS RELAIVE O 'S FALLING EDGE. HIS IS DUE O HE INVERSION OF HE IN SINGLE-ENDED MODE. SEE FIGURE FOR INVERSION. Figure 6. Proper iming Relationship between and EX I/O Update CLK in Single-Ended Mode 6. See the diagrams above for the recommended timing between EX I/O UPDAE CLK and. Choose the appropriate diagram given differential or single-ended mode. 7. Assert a common EX I/O UPDAE CLK. his will result in the DAC outputs becoming active simultaneously at the correct frequency and phase offset as programmed. USING HE MULIPLIER (PLL) ON HE AD95 he multiplier of the AD95 must be used with care when synchronizing multiple DDSs because the PLL lock time will vary from device to device. his means that the number of SYSEM CLK cycles delivered to the phase accumulator during the PLL lock interval is not predictable. herefore, the tuning word must be zero during this time period, which is the default if preceded with a RESE. A tuning word of zero prevents the phase accumulator from incrementing while the PLL locks. Since all the devices are clocked by a common and the PLLs are phase locked to, all SYSEM CLK signals should also be in-phase, assuming a proper signal is routed to each DDS as discussed previously. A typical PLL lock time is approximately 400 µs. Due to variations in IC processing and temperature effects on lock time, it is recommended to allow at least.0 ms for locking to occur (refer to Figure 7). 4
EK SOP:.00MS/s DAC OUPU PLL LOCK IME : 37 s @: 0 s Note: he multiplier will lock to the falling edge of ; therefore, the EX I/O UPDAE CLK signal should be referenced to the falling edge of in differential mode and to the rising edge in single-ended mode. he recommended timing relationship between the rising edge of the EX I/O UPDAE CLK (Pin 0) and the (Pin 69) is depicted in Figures and 9. 3 EX I/O UPDAE CLK VCO INPU CH 50.0mV CH 00.0mV M 50 s CH3 700mV CH3.00V Figure 7. ypical PLL Lock ime.5ns (PIN 69) EX I/O UPDAE CLK MUS OCCUR WIHIN HIS RANGE IF SYSEM CLK IS @ 300MSPS OR ELSE REFER O HE NOE BELOW EX I/O UPDAE CLK (PIN 0) VALID @300MSPS NOE: HE VALID IMING RANGE WILL INCREASE WIH A DECREASE IN HE SYSEM CLK FREQUENCY HE EDGE CAN BE MOVED O HE LEF PROPORIONALLY WIH A DECREASE IN SYSEM CLK FREQUENCY HE EDGE IS FIXED AS HE OUER LIMI FOR I/O UPDAE CLK (MAX.ns FROM FALLING EDGE OF ) NOE: HE RISING EDGE OF EX I/O UPDAE CLK IS RELAIVE O HE FALLING EDGE OF DUE O HE FAC HA HE PLL LOCKS O HE FALLING EDGE OF. Figure. Proper iming Relationship Using the Multiplier in Differential Mode EX I/O UPDAE CLK MUS OCCUR WIHIN HIS RANGE IF SYSEM CLK IS @ 300MSPS OR ELSE REFER O HE NOE BELOW.ns (PIN 69) EX I/O UPDAE CLK (PIN 0) @ 300MSPS VALID NOE: HE VALID IMING RANGE WILL INCREASE WIH A DECREASE IN SYSEM CLK FREQUENCY HE EDGE CAN BE MOVED O HE LEF PROPORIONALLY WIH A DECREASE IN SYSEM CLK FREQUENCY 5 HE EDGE IS FIXED AS HE OUER LIMI FOR I/O UPDAE CLK (MAX.5ns FROM RISING EDGE OF ) Figure 9. Proper iming Relationship Using the Multiplier in Single-Ended Mode
INSRUCIONS WIH HE AD95 S MULIPLIER ENABLED O SYNCHRONIZE WO DDSs.. Power up all devices and apply the common.. Send a common RESE with a minimum high time of 0 periods. 3. Program all DDSs for EX I/O UPDAE CLK mode (bypass digital multipliers and inverse sync, if desired). 4. Program all DDSs for PLL mode along with the multiplier value. 5. Send a EX I/O UPDAE CLK and wait.0 ms for PLLs to lock. 6. Program DDS No. to the desired frequency and a phase offset of 0 without issuing an EX I/O UPDAE CLK. 7. Program DDS No. to the exact same frequency and a phase offset of 0 without issuing an EX I/O UPDAE CLK.. See the diagrams below for the recommended timing between EX I/O UPDAE CLK and. Choose the appropriate diagram for dif ferential or single-ended mode. IMPORAN: Users must remember to keep the multiplier enabled as they write each new tuning word and/or phase offset. 9. Assert a common EX I/O UPDAE CLK. his will result in the DAC outputs becoming active simultaneously at the correct frequency and phase offset as programmed. SUMMARY With proper care and procedure, synchronization can be achieved among multiple DDSs. he following illustrations show how two AD95s are synchronized to one another. In Figure 0, the frequency is set to 00 MHz, and in Figure, it is 300 MHz. Both are in non- PLL mode. For Figure, is set to 75 MHz with the multiplier programmed for 43 (System Clock = 300 MHz). Figure 3 shows two DDSs remaining in quadrature, even as the frequency changes are made. Quadrature is denoted by the cursor positioning in Figure 3. 3 DDS NO. OUPU DDS NO. OUPU FWS LAENCY HROUGH DEVICE GIVEN HE CONFIGURAION (INV SINC AND DIG MUL BYPASSED) EX I/O UPDAE 00MHz REFERENCE CLOCK (NON-PLL MODE) 4 CH 50.0mV CH 50.0mV M 00ns CH3.V CH3.00 CH4.00V : 370ns @: 366ns Figure 0. DDS Synchronization (Conditions: V CC = 3.3 V, = 00 MHz, Non-PLL Mode, 5ºC) DDS NO. OUPU DDS NO. OUPU FWS LAENCY HROUGH DEVICE GIVEN HE CONFIGURAION (INV SINC AND DIG MUL BYPASSED) : 3.0ns @: 9.0ns EX I/O UPDAE 3 300MHz REFERENCE CLOCK (NON-PLL MODE) 4 CH 50.0mV CH 50.0mV M 5ns CH3.0V CH3.00V CH4.00V Figure. DDS Synchronization (Conditions: V CC = 3.3 V, = 300 MHz, Non-PLL Mode, 5ºC) 6
DDS NO. OUPU DDS NO. OUPU : 3.0ns @:.5ns :.3 s @:.64 s EX I/O UPDAE 3 75MHz REFERENCE CLOCK (PLL MODE 4 = 300MHz) 4 CH 50.0mV CH 50.0mV M 5ns CH3.0V CH3.00V CH4.00V Figure. DDS Synchronization (Conditions: V CC = 3.3 V, = 75 MHz, PLL (4 ) Mode Enable, 5ºC) CH 00mV CH 00mV M 500ns CH4.70V Figure 3. DDS Quadrature Synchronization (Conditions: V CC = 3.3 V, = 40 MHz, Non-PLL Mode, 5ºC) 7
PRINED IN U.S.A. E03074 0 /03(0)