FPGA based Satellite Set Top Box prototype design

9 th International conference on Sciences and Techniques of Automatic control & computer engineering FPGA based Satellite Set Top Box prototype design Mohamed Frad 1,2, Lamjed Touil 1, Néji Gabsi 2, Abdessalem Ben Abdelali 1, Abdellatif Mtibaa 1,2 1. Laboratoire d'electronique et de Microélectronique de la FSM ". 2. Ecole Nationale d Ingénieurs de Monastir, Avenue Ibn ElJazzar, 5019 Monastir, Tunisie. mhamed.frad@gmail.com ; neji_elgabsi@yahoo.fr ; lamjedtl@yahoo.fr ; abdelalienis@yahoo.fr ; abdellatif.mtibaa@enim.rnu.tn Abstract. In this paper we propose a study of a digital satellite Set Top Box (STB) with multiple tuner using FPGA technologies. A study about the DBS tuner module is provided to ease the interface problem with the Xilinx XUP board which is used as a development system. One of the major challenges involved in this study is to connect necessary intellectual property (IP) cores for the STB design to the IBM PowerPC 405 core integrated into the Virtex-II Pro devices and to exploit µclinux real time operating system to manage the device keywords. Digital Video Broadcasting (DVB), Set Top Box (STB), System on Programmable chip (SoPC), PowerPC, Real time operating system (RTOS) 1. Introduction Recent advances in Field Programmable Gate Array technologies have made it possible to design powerful and easily customizable Systems on Programmable Chip (SoPCs). An obvious advantage of this latter is the great flexibility in hardware configuration. In fact suitable kinds of processors and intellectual property cores can be often chosen for each application. The processors can handle software tasks as needed and hardware blocks permits to accelerate the time critical treatments. Thus, design of embedded applications becomes more flexible and efficient. In this paper, we aim to take the advantage of new FPGA families to implement a part of a satellite digital set-top box and to port an embedded operating system to manage the hardware and offer high flexibility. This allows providing affordable and high performance cost effective solutions for demanding set top box applications, including data broadcasting, interactive TV and web browsing. For experimentation we have exploited the resources of the XUP Virtex-II Pro platform. STA'2008-IRM-467, pages 1-9 Academic Publication Center of Tunis, Tunisia

2 STA 2008 IRM 467, pages 1 à 9 2. Interactive television concept The digital television offers a revolutionary platform for a number of new services and applications. It allows not only broadcasting data but also all introducing kinds of interactive services such as video in demand (VoD) which let the viewer to watch TV program or movie at any time he wants and web services which permit users to send email, chat, and surf the Internet from their televisions. Viewers can communicate with each other when watching TV programs, exchanging their opinion about TV shows in real time. Interactive programming (figure 1) is an interesting topic coming with interactive services. In fact, viewers are able to choose from a number of a different video feeds as well as the main live feed via an interactive mosaic. For example, viewers can then follow simultaneous football matches displayed on the screen TV side by side, without missing any important episodes. They could also get in-vision statistics including the current score and also pull up information on the goals. [1] In this context, we aim to design a set top box hardware prototype and to use suitable operating system permitting to integrate the desired services. Fig. 1. Interactive programming mosaic.

FPGA based Satellite Set Top Box prototype design - 3 3. Multiple tuners satellite set-top box prototype In this paragraph we describe the different elements and solutions for a suggested multiple tuners architecture. This architecture aim to provide a cost effective satellite set top box allowing the viewer more complete information about programming availability on all broadcast channel. In fact, it provides the user with options to customize the plurality of channels displayed.it has the ability to simultaneously tune to more one channel which has the advantage of being able to view programs from separate channels at the same time through picture thumbnails. Fig. 2. Multiple tuners satellite set-top box. The initial prototype, presented by figure 2, is based on three branches. Each branch includes a tuner, a demodulator, a descrambler, an MPEG A/V decoder configured to receive and to decode videos signals from the transport demultiplexor. The first tuner is controlled by a microprocessor via the I2C bus according to input from a remote control, to select one of the broadcast signals. First tuner, in turn, passes the selected broadcast signal to QPSK demodulator. The packets of data are then provided to a descrambler then to a transport demultiplexor which separates and processes audio, video and data packets. The separated audio and video packets are provided to an MPEG audio/video (A/V) decoder which decompresses video and audio signals and converts them to analog form. In the same way, PIP tuner is tuned to a particular channel by the microprocessor via I2C bus and broadcast signal subject the same treatments. Third tuner is reserved for recording functionality (PVR) allowing user to store a desired TV program at predefine time, and viewer can replay it whenever he wants. The digital DBS tuner module BS2F7V0194 is a solution which includes a direct conversion RF tuner and an integrated circuit STV0299B which performs digital demodulation, half-nyquist filtering and forward error correction FEC. So, it we have exploited this solution to ease the architecture of the multiple tuners satellite set top box. The digital DBS tuner module is controlled by I2C bus for selecting frequency on which to lock, setting the polarizations, selecting low or

4 STA 2008 IRM 467, pages 1 à 9 high KU band, QPSK demodulator, 8-bit data bus (transport stream TS), loop-trough for redirecting input signal to next device. It is compulsory to associate an LNB supply as a hardware control circuit as shown in figure 3. BS2F70194 Fig. 3. Complete RF-to-digital front end. [2] The XUP Virtex-II Pro platform is exploited to implement different IP cores and control signals such as the DVB descrambler, MPEG-2 transport demultiplexor, the PAL/NTSC encoder, the GPT PWM (General purpose timers, pulse with modulation) and the I2C bus according to the principle shown in figure 4. LNB in Stereo audio via AC97 codec XSGA video port LNB out Tuner Reset Fig. 4. Digital DBS tuner based STB hardware architecture.

FPGA based Satellite Set Top Box prototype design - 5 The FPGA used in the XUP board integrates two hard PowerPC 405 processors. These processors provide high performance and lower power consumption and can support a system frequency of 300 MHz. PowerPC 405 could be interconnected to chip cores from multiple sources thanks to the IBM CoreConnect (Figure 5). Fig. 5. Foundation of IBM PowerPC, with CoreConnect. [3] 4. Experimentation Modular design has become a very common practice among system designers due to the increased complexity of systems and the need for reusing each of the different components that form these systems. Modern system level design tools provide environments and specifications in which offer many advantages to system design, to create the hardware and the software environment of our satellite set top box, we have used the Xilinx Embedded Development Kit (EDK) [6]. This latter contains Embedded System Tools (EST), documentation, and Hardware IPs for the Xilinx embedded processors and peripherals. 4.1. Proposed architecture As shown in figure 4, an interface problem between the Xilinx XUP board and the DBS tuner module. To resolve this problem, we have specified the nature of pins and the hardware control circuit associated. Thereafter, an interface module has been chosen to ensure the communication between the XUP board, the Control hardware and the digital DBS tuner. Moreover we have taken the advantage of the video port, the serial port and the audio codec of the XUP board to design our hardware platform.

6 STA 2008 IRM 467, pages 1 à 9 4.2. Creating the STB hardware system The first step is to create a hardware platform which contains the PowerPC, buses, and peripherals attached to this processor and next we select the desired peripherals. Different Xilinx IP cores are provided by the development tool library (EDK) such as the UART Lite, the GPIO (General Purpose Input/output), the interrupt controller and the audio codec. The IPs cores which are not offered by the library of EDK are added as custom IP. They were validated by Modelsim then synthesized by ISE tools for the target device XC2VP30. The custom IPs cores are: I2C bus MPEG-2 transport demultiplexor/ DVB descrambler. The PAL/ NTSC encoder. GPT PWM (General purpose timers, pulse width modulation (GPT, PWM)). Synthesis results of this IPs are given in the following table 1. Table 1. Synthesis results of IPs cores. IP cores Number of slices Number of 4 inputs LUTs I2C bus 48 91 MPEG-2 transport demultiplexor/ DVB descrambler 319 477 PAL/NTSC encoder 19 37 GPT PWM 4 8 Examples of simulation result are given in figures 6 et 7. Figure 8 represents the user interface using EDK tool. Fig. 6. I2C bus simulation result.

FPGA based Satellite Set Top Box prototype design - 7 Fig. 7. GPT PWM simulation result. Fig. 8. The project interface. 4.3. Creating the STB hardware system The operating system is one of the most important software resources in our set top box. It offers services such as schedulers, synchronization mechanisms, and threads. A set-top box operating system has time constraints and requires handling sophisticated tasks in a small memory space. So, it must be fast, reliable, modular, highly configurable and capable to operate in real-time environment. A number of real time operating systems have emerged to drive the next generation of advanced set-top box [5]. Linux is one of the attractive operating system for several reasons: Open Source and Royalty Free. Small in Size: The kernel image of an embedded Linux is usually about 2MB to 8MB. µclinux is an example of real time operating system (RTOS) designed specifically for deeply embedded applications such as telecommunication, switchers, routers and interactive TV terminals. In fact, µclinux distribution is devoted to processors which don t benefit of memory management unit (MMU) and float processor unit (FPU).

8 STA 2008 IRM 467, pages 1 à 9 The C library which is necessary for programs users compilation was Remark 1. In the printed volumes, illustrations are generally black and white (halftones), and only in exceptional cases, and if the author is prepared to cover the extra cost for color reproduction, are color pictures accepted. If color illustrations are necessary, please send us color-separated files if possible. Color pictures are welcome in the electronic version at no additional cost. The C library which is necessary for programs users compilation was lightened in order to keep the embedded systems more efficient. Therefore, most µclinux features are suitable for the satellite receiver. In the present paragraph we will port an embedded operating system to manage the hardware and offer design flexibility. In fact, The XPS allows us to add software applications to available processors. The applications can be compiled with GCC like compilers. µclinux has been considered as the suitable real-time operating system (RTOS). The next flow, figure 9, shows the indispensable steps of µclinux implementation. 1. Kernel preparation 3. Hardware platform creation 2. µclinux BSP installation Fail Copy of the autoconfig.in file with UNIX in order to convert it to UNIX file Windows Memory test Windows/Linux OK Linux 4. Kernel image creation Windows Copy of the kernel image «image.bin" with windows Widows/Linux Linux 5. Downloading kernel image to the target Board Fig. 9. µclinux flow chart.

FPGA based Satellite Set Top Box prototype design - 9 5. Conclusion This paper was dedicated to present a study of a digital set top box architecture including multiple tuners using FPGA technologies. After introducing interactive television concept, we have discussed the architecture of a multiple tuners set top box prototype which is based on the use of XUP platform. This latter integrates two PowerPC 405 processors and the IBM CoreConnect which are useful for our design. In the experimental part, we have presented some synthesis and simulation results of different IPs cores used for our design and given the key steps to include a real time operating system. This study is still at an early age. Currently we are connecting some IPs cores to the PowerPC and porting the appropriate operating system. The next major task is to complete the others parts of our digital set top box and to integrate interactive applications algorithms. References 1. Karyn Y. Lu, "Interaction design principles for interactive television", Master of Science in Information Design and technology, Georgia Institute of Technology, May 2005. 2. Silicon Laboratories, "SiRX Single-Chip RF Front-End for Digital Satellite TV", < http://www.silabs.com>. 3. Xilinx, "Xilinx Inc" 2003, < http://www.xilinx.com>. 4. C. Peng, P. Cesar and P. Vuorimaa, "Integration of applications into digital television environment", In Proceedings of the 7th International Conference on Distributed Multimedia Systems, Taipei, Taiwan, September 26.28, 2001, pp 266.272. 5. H-L. J. LIN, "Evaluating Hardware/Software partitioning and embedded Linux port of the Virtex II-PRO development system", master of science in computer engineering, Washington State University, School of Electrical Engineering and Computer Science, MAY 2006.