igital esign Lab EEN 315 Section H Project #2 dd & Shift Multiplier Group #6 Sam razin (Partner: rian Grahn) Lucas lanck, T University of Miami pril 7, 2008 1
bstract The purpose of this project was to take another step in higher- level logic design and create a functional add- and- shift multiplier circuit. Important points of the project were the comprehension and usage of the shift register, as well as the capability to compile several other Is to collaborate their abilities to complete the circuit. The key results were displayed on the E2 board utilizing LEs, switches and push buttons that we assigned using Quartus. The major conclusion that we came to from this project was that the organization of most significant to least significant bits pertaining to I pin assignments is for some reason still not an industry standard, the answer to why we ll never know. 2
Table of ontents Overview... 4 Objectives... 4 Equipment... 4 escription... 4 Specifications... 6 esign Synthesis... 6 omplete Logic iagram... 6 onclusion... 7 3
Overview To complete this project, one should be fully aware of the capabilities and uses of a shift register, as well as a full adder. The most difficult aspect of this assignment was to fully understand the mechanics of the dd & Shift algorithm while putting it into actual practice. Past that, the rest is just assembly and testing of your circuit. Objectives The objective of this lab was to construct the dd & Shift circuit, and to properly transfer the pin assignments to the E2 board and test the circuit manually. These objectives were carried out using the Quartus software and the E2 instructional learning hardware. Equipment The I s that we used for this lab were: - One 2:1 ata Selector/Multiplexors - One 4:1 ata Selector/Multiplexors - One 74163 Synchronous 4- bit ounter - Two 7494 Shift Registers - One 74198 Shift Register - Five N Gates - One 7483 Full dder escription To begin building this project, we first had to fully examine the concept of the dd & Shift multiplication. Once we fully understood the way that the algorithm was supposed to work, we had to map out on paper the way we wanted it to work in our circuit. eing able to use the I Shift Register was a big convenience, having just built one by hand in the previous project. side from this, all we needed to do was to configure the right parts in the right order. The difficult part in completing the assignment however would come in the wiring; but the right parts had to be chosen first. To begin, we knew we would be comparing two 4- bit numbers, (the multiplicand and the multiplier) every time the multiply algorithm would be performed, so in order to represent these numbers and be able to handle them, we set up two, 4- bit shift registers. Next, we installed a Modulo- 4 counter into our circuit, as we would want the dd & Shift function to go through only four times, (once for each bit in our multiplicand and multiplier) and then finish. This was done by slightly modifying a four- bit 74163 Modulo- N counter. With these Is in place, we had a better idea of how the first half of the circuit would work. The top Shift Register would act as the multiplicand, and the bottom, the multiplier. 4
Each of the multiplicand s outputs would be run to an N gate, and to the other output of the N gate, a line consolidating all four outputs from the multiplier s Shift Register would be run. This single line out would be the product of a 4:1 MUX receiving the outputs directly from the multiplier Shift Register. The control lines for the MUX would come from the counter, mainly the two mid- significant bit lines of the 74163 s output. This was done for a very specific reason, for which I will have to zoom out to the scope of the full circuit momentarily to explain. What the circuit needed to eventually do was to be able to multiply the two Shift Registers together, and then shift the entire product down a bit. To start the multiplication sequence, we first had to design a Start signal. To do this, we sent a 1 to all of the lear pins for our Shift Registers. To call the Start (reset), we merely switched the send to those pins to 0, and then back to 1. We designed our circuit such that each of these two steps requires a clock cycle, and this being the case, we needed at least seven pulses to get all four multiplications done before the hold signal kicked in. This MUX feeds the N gates the multiplier input bit- by- bit, but because we needed this process to happen twice as slowly, we chose to put the MUX s select lines as the two mid- significant bits instead of the two least significant bits. This would half the processing time for the second Shift Register to feed its input. The output of the 4:1 MUX ends up dictating the N gates output directly, saying either that the output would be the same as that of the multiplicand Shift Register, or 0 ; exactly what we would want an dd & Shift circuit to do. The N gates would then be sent to the Full dder, although the order of significance is switched between the two, hence the messy connections below in the diagram. The four N outputs would serve as 1-4 inputs into the dder, and the second set of inputs, 1-4, would end up being fed back into the dder from the final stage- Shift Register, (which for explanations sake would initially be all 0 s). The sum of the Full dder is sent straight into the four most- significant bits of the 8- bit Shift Register. The four MS outputs are the ones mentioned above, being sent back into the inputs of the Full dder. This was to prepare the adder for another instance of receiving a 1 from the N gates, and having to again add the multiplicand to the current sum. The first three of the least- significant bits were sent back into their own inputs, excluding the actual LS, creating a feedback scenario. This was to maintain a sound Shift Register atmosphere, taking the bits as they came in and shifting them down one by one, filling out a full 8- bit sum. The input of the LS would be sent from the arry out send from the Full dder. This was to ensure that a proper carry- over digit from the dder was properly accounted for by the LS of the final Shift Register. The 8- bit shift register was controlled by two control lines, and the main goal in handling this I was to allow for four dd & Shift calculations, and then holding the final product. This became the inherent design for our hold signal. In order for the Shift Register to work, both control lines needed to have 1. To initialize the register, the first select line was sent from the NOTed product of the most and least- significant bits from the counter, which unless at 9, would be 1. The second control line was sent from the output of the 2:1 MUX, which would alternate from 0 to 1 depending on the least- significant bit of the counter. This alternating would allow the Shift Register to add once from the adder, and shift once within itself. This is the basis of our two- part dd & Shift algorithm. Specifications 5
There were no specific guidelines or design specifications for this project. The hold and start functions had to be created, but the premise of this project was for accurate and succinct design, leaving most of the decisions up to us. esign Synthesis Very little logic had to be written out to complete this project. The majority of this assignment tested our ability to design a functional circuit that could perform the dd & Shift functions, utilizing Shift Registers and a Full adder. omplete Logic iagram Shift Register lr LK Q Q Shift Register lr LK Q Q 4:1 lock Ground Full dder 1 1 2 2 3 S3 3 S4 4 4 0 4 E F G H Shift Register 74198 LK Q Q Q E Q F Q G Q H 74163 ounter 2:1 Q Q EN 6
onclusion Our main response from this project was more positive than negative, although it took us a while to hack through the logic and bit significances of all of the different Is. ebugging and testing the circuit were by far the most challenging aspects of the project. The wiring required was, for the most part, spelled out completely for us in the lab description. I enjoyed learning to use Quartus, seeing as it helped greatly in the organization and testing of our circuit, and the E2 features were a nice visual reinforcement of our work in this lab. 7