STV6412A. Audio/video switch matrix. Features. Description

STV642A Audio/video switch matrix Features I ² C bus control Standby mode with interrupt signal output Video section 4 CVBS inputs, 3 CVBS outputs (one with selectable chroma trap filter) 3 Y/C inputs, 2 Y/C outputs 6 db gain on all CVBS/Y and C outputs Integrated 5 Ω buffers Y/C adder 2 RGB/FB inputs, tri-state RGB/FB output with 6 db adjustable gain (from +3dB to +9dB) Video muting on all outputs 2 slow blanking inputs/outputs Sync bottom clamp on all CVBS/Y and RGB inputs, average clamp on C Inputs Bandwidth: 5 MHz Crosstalk: 5 db minimum Audio Section 4 stereo inputs, 3 stereo outputs mono-sound output stereo-to-mono sound capability /6/9 db selectable gain on one stereo input Full range volume control with soft control Audio muting on all outputs Description LQFP64L(4 x 4 x.4 mm) (Low-profile Quad Flat Package) Order code: STV642ADT The STV642A is a highly integrated I ² C buscontrolled audio and video switch matrix, optimized for use in digital set-top box applications. It provides all the audio and video routings required in a full two SCART set-top box design. September 29 Doc ID 9754 Rev 2 /3 www.st.com 3

Contents STV642A Contents General overview............................................ 3. Pin connections............................................. 3.2 Block diagrams.............................................. 6 2 Electrical characteristics..................................... 8 2. Absolute maximum ratings..................................... 8 2.2 Thermal data............................................... 8 2.3 Latch up................................................... 8 2.4 Recommended operating conditions............................. 8 2.5 Audio section characteristics................................... 9 2.6 Video section characteristics.................................. 2.7 Chroma section characteristics................................ 2 2.8 Blanking section............................................ 2 2.9 I²C bus characteristics....................................... 4 3 I2C bus selection........................................... 6 3. I2C bus addresses.......................................... 6 3.2 Power-on reset bus register initial conditions................... 2 4 Input/output groups........................................ 23 5 Application diagram........................................ 27 6 Package mechanical data.................................... 28 7 Revision history........................................... 3 2/3 Doc ID 9754 Rev 2

STV642A General overview General overview. Pin connections Figure. Pinout dagram LOUT_TV FILTER AOUT_RF VOUT_RF VccB 5 BOUT_TV VccB 4 GOUT_TV GNDB R/COUT_TV VccB 3 Y/CVBSOUT_TV VccB 2 COUT_VCR VccB Y/CVBSOUT_VCR Table. FBOUT_TV FBIN_VCR FBIN_ENC C_GATE VDD ADD SCL SDA GND IT_OUT SLB_TV R/CIN_VCR SLB_VCR GIN_VCR Vcc2 BIN_VCR Pin description DECA NC BIN_ENC LIN_ENC GIN_ENC RIN_ENC R/CIN_ENC LIN_AU CIN_ENC RIN_AU YIN_ENC GND Y/CVBSIN_ENC DECV CVBSIN_AU Vcc ROUT_TV Vccao LOUT_VCR ROUT_VCR LOUT_CINCH ROUT_CINCH NC GNDA VccA RIN_TV LIN_TV CVBSIN_TV RIN_VCR LIN_VCR Y/CVBSIN_VCR GND Pin no. Symbol Description V CC +5 V supply 2 CVBSIN_AU CVBS input from auxiliary 3 DECV Video decoupling capacitor 4 Y/CVBSIN_ENC Y/CVBS input from encoder 5 GND Ground 6 YIN_ENC Y input from encoder 7 RIN_AU Audio right input from auxiliary 8 CIN_ENC Chroma input from encoder 9 LIN_AU Audio left, input from auxiliary R/CIN_ENC Red/Chroma input from encoder RIN_ENC Audio right, input from encoder 2 GIN_ENC Green input from encoder 3 LIN_ENC Audio left, input from encoder Doc ID 9754 Rev 2 3/3

General overview STV642A Table. Pin description (continued) Pin no. Symbol Description 4 BIN_ENC Blue input from encoder 5 NC Not connected 6 DECA Audio decoupling capacitor 7 GND Ground 8 Y/CVBSIN_VCR Y/CVBS input from VCR SCART 9 LIN_VCR Audio left, input from VCR SCART 2 RIN_VCR Audio right, input from VCR SCART 2 CVBSIN_TV CVBS input from TV SCART 22 LIN_TV Audio left, input from TV SCART 23 RIN_TV Audio right, input from TV SCART 24 V CCA Audio supply voltage - or - audio supply decoupling 25 GNDA Audio ground 26 NC Not connected 27 ROUT_CINCH Audio right output to cinch 28 LOUT_CINCH Audio left output to cinch 29 ROUT_VCR Audio right output to VCR SCART 3 LOUT_VCR Audio left output to VCR SCART 3 V CCAO Audio output supply voltage - or - main audio supply voltage 32 ROUT_TV Audio right output to TV SCART 33 LOUT_TV Audio left output to TV SCART 34 FILTER Chroma trap filter 35 AOUT_RF Audio (L+R) output to RF modulator 36 VOUT_RF CVBS video output to RF modulator 37 V CCB5 Video output buffer supply pin 38 BOUT_TV Blue output to TV SCART 39 V CCB4 Video output buffer supply pin 4 GOUT_TV Green output to TV SCART 4 GNDB Video buffer ground 42 R/COUT_TV Red/Chroma output to TV SCART 43 V CCB3 Video output buffer supply pin 44 Y/CVBSOUT_TV Y/CVBS output to TV SCART 45 V CCB2 Video output buffer supply pin 46 COUT_VCR Chroma output to VCR SCART 47 V CCB Video output buffer supply pin 48 Y/CVBSOUT_VCR Y/CVBS output to VCR SCART 4/3 Doc ID 9754 Rev 2

STV642A General overview Table. Pin description (continued) Pin no. Symbol Description 49 FBOUT_TV Fast blanking output to TV SCART 5 FBIN_VCR Fast blanking input from VCR SCART 5 FBIN_ENC Fast blanking input from encoder 52 C_GATE External MOS command for C_VCR bidirectional mode 53 V DD +5 V I 2 C supply 54 ADD I 2 C address selection 55 SCL I 2 C bus clock 56 SDA I 2 C bus data 57 GND Ground digital 58 IT_OUT Interrupt output 59 SLB_TV Slow blanking input/output from TV SCART 6 R/CIN_VCR Red input (or C input) from VCR SCART 6 SLB_VCR Slow blanking input/output from VCR SCART 62 GIN_VCR Green input from VCR SCART 63 V CC2 +2 V supply 64 BIN_VCR Blue input from VCR SCART Doc ID 9754 Rev 2 5/3

General overview STV642A.2 Block diagrams Figure 2. STV642A block diagram FBIN_ENC FBIN_VCR FBIN_ENC FBIN_VCR FBOUT_TV BIN_ENC BIN_VCR GIN_ENC GIN_VCR R/CIN_ENC R/CIN_VCR CIN_ENC CVBSIN_AU Y/CVBSIN_VCR YIN_ENC Y/CVBSIN_ENC CVBSIN_TV LIN_AU LIN_ENC LIN_TV RIN_AU RIN_ENC /6/9 db /6/9 db RGB switch RIN_TV LIN_VCR RIN_VCR BIN_ENC BIN_VCR GIN_ENC GIN_VCR R/CIN_ENC R/CIN_VCR Mute Mute R/CIN_VCR CIN_ENC R/CIN_ENC Mute CVBSIN_AU Y/CVBSIN_VCR YIN_ENC Y/CVBSIN_ENC Mute 6 db C switch 6 db Y/CVBS switch Mute Mute CIN_ENC R/CIN_ENC 6 db Mute CVBSIN_AU CVBSIN_TV Y_ENC Y/CVBSIN_ENC Mute LIN_AU LIN_ENC LIN_TV RIN_AU RIN_ENC RIN_TV Mute LIN_AU LIN_ENC LIN_VCR LIN_TV RIN_AU RIN_ENC RIN_VCR RIN_TV Mute VCR switch TV switch FB switch C switch 6 db Y/CVBS switch -62 db 3 to 9 db 3 to 9 db 3 to 9 db /6 db -62 db /6 db Trap Slow blank monitor interrupt signal Stereo/mono /6 db /6 db /6 db Stereo/mono I²C bus decoder BOUT_TV GOUT_TV R/COUT_TV VOUT_RF FILTER Y/CVBSOUT_TV C_GATE COUT_VCR IT_OUT SLB_TV SLB_VCR Y/CVBSOUT_VCR LOUT_VCR ROUT_VCR ROUT_CINCH LOUT_CINCH AOUT_RF LOUT_TV ROUT_TV ADD SDA SCL 6/3 Doc ID 9754 Rev 2

STV642A General overview Figure 3. Functional block diagram SCART TV RF MOD AU MICRO R/C G B FAST BLANK CVBS AUDIO L AUDIO R CVBS/Y AUDIO L AUDIO R SLOW BLANK CVBS AUDIO L+R CVBS AUDIO L AUDIO R INTERRUPT STV642A R, G, B, FB switches CVBS/Y switches Chroma switches Audio switches Slow blank, I/O control AUDIO L AUDIO R R/C G B FAST BLANK CVBS/Y C AUDIO L AUDIO R Y R/C G B FAST BLANK CVBS/Y AUDIO L AUDIO R CVBS/Y C AUDIO L AUDIO R SLOW BLANK SCART2 VCR CINCH output Encoder Doc ID 9754 Rev 2 7/3

Electrical characteristics STV642A 2 Electrical characteristics 2. Absolute maximum ratings Symbol Parameter Value Unit V CC2 Supply voltage for: - Slow blanking sections 3.2 V V CCAO - Audio drivers 3.2 V V CCA - Internal digital audio parts V V DD - Digital parts 6 V V cc, V CCBi - Video sections 6 V V I Voltage at pin I to GND: - Audio pins, V CCA V V ESD 2.2 Thermal data 2.3 Latch up At an ambient temperature of 25 C, all pins meet the following specifications: I trigger = 2 ma or I trigger = 2 ma. Pin 58 (IT_OUT) does not meet this specification and the trigger current must be limited to - ma. 2.4 Recommended operating conditions - Video pins, V CC or V CCBi V - Bus pins, 5.5 V - Slow blanking pins, V CC2 V Maximum ESD voltage allowed. pf capacitor discharged through.5 kω serial resistor (human body model) ±4 kv T oper Operating ambient temperature, +7 C T stg Storage temperature -2, +5 C Symbol Parameter Value Unit R th(j-a) Junction-ambient thermal resistance (maximum) 48 C/W T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. 8/3 Doc ID 9754 Rev 2

STV642A Electrical characteristics Table 2. Supply voltages Symbol Parameter Test condition Min. Typ. Max. Unit V DD Digital supply voltage 4.75 5 5.25 V V CCAO Audio operating supply voltage - Decoupling capacitor on V CCA - Connected to V CCA.2 8.5 V CC Video operating supply voltage 4.75 5 5.25 V V CC2 Slow blanking control supply voltage.2 2 2.8 V 2 9 2.8 9.5 V V Table 3. Active mode (all channels ON) Symbol Parameter Test condition Min. Typ. Max. Unit I DD Digital supply current V DD = 5 V 4.5 ma I CCA Audio supply current V CCAO = 2 V, no load 9 5 ma Total video supply current V CC = 5 V, no load 43 6 ma I CCV I CC2 Table 4. (V CC +V CCB +V CCB2 +V CCB3 +V CCB4 +V CCB5 ) 2 V Supply Current Standby mode (all channels OFF) 2.5 Audio section characteristics V CC2 = 2 V SLB input mode SLB output mode, no load Symbol Parameter Test condition Min. Typ. Max. Unit I DD Digital supply current V DD = 5 V 4.5 ma I CCAstd Audio supply current V CCA = 2 V, no load 3 ma I CCVstd Total video supply current V CC = 5 V ma Table 5. T amb = 25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Audio section characteristics Symbol Parameter Test condition SVR Supply voltage rejection V RIPPLE = 5m V RMS at f = Hz, Gain= db, DECA filter cap = 47 µf DECA filter cap = 22 µf Min. 2.5 Typ. 6 7 8 SVRK Supply voltage rejection V RIPPLE = 5m V RMS at f = khz, Gain = db 7 8 db V INDC Input DC Level V CCA = 9 V V CCA/2 V 4 Max. ma Unit db db V INAC Input signal amplitude 2 V RMS R IN Input resistance 3 5 kω Doc ID 9754 Rev 2 9/3

Electrical characteristics STV642A Table 5. Audio section characteristics (continued) Symbol Parameter Test condition Min. Typ. Max. Unit R INmatch Input resistance matching ±2 ± % F RANGE Flatness CS Bandwidth Spread of gain in audio band Channel separation, from audio inputs between L & R of TV outputs 2.6 Video section characteristics -3 db,.5 V RMS, R LOAD = kω, gain = db -.5 V RMS, 2 Hz to 2 khz, gain = db V IN =.5V RMS, f = khz, on one input, R LOAD = kω, gain = db 5 khz.5 db Ci Channel isolation from video inputs V IN = V pp, f = 5 khz, on one point 85 db V OUT Output DC Level V CCA = 9 V V CCA/2 V V OFF DC offset change Switching between inputs ±5 mv R OUT Output resistance 6 2 W PHD ASN eni Phase ddifference S/N Ratio Equivalent RMS Input voltage noise f = khz, V RMS input on each input channel f = khz, V RMS input (gain = db) weighted CCIR 468-4 quasi peak BW = 2 Hz, 2 khz flat, gain = db T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. 8 7 9 74 db db 3 deg. 7 db 5 µv.5 V G db gain RMS, R LOAD = kω, gain = -.5 +.5 db db G STEP Gain step -62 db to +6 db ( see Figure 2) 2 db Gain matching between different G MATCH V inputs of one output IN =.5 V RMS, khz, Gain = db -.5.5 db G MATCH2 THD THD6 THD9 Gain matching between left/right outputs of one input channel Total harmonic distortion ENC input at db ENC input at 6 db ENC input at 9 db V IN =.5 V RMS, khz, Gain = db -.5.5 db V OUT =.5 V RMS, khz, LPF @ 8 khz V CL Output clipping level THD =.2%, khz 2. 2.3 V RMS V R L Output load resistance IN = V RMS, THD =.3%, 2 2.25 kω Gain = db Mute Mute suppression V IN =.5 V RMS, on one point -9 db...... % % % /3 Doc ID 9754 Rev 2

STV642A Electrical characteristics Table 6. Video section characteristics Symbol Parameter Test condition Min. Typ. Max. Unit V DCIN DC input level Bottom synch pulse 2 V I CLAMP Clamping current at VDCIN -4 mv 2 ma I LEAK Input leakage current VIN = VDCIN + V µa C IN Input capacitance 2 pf V IN Max input signal VCC = 5 V.5 V PP DYN Dynamic output signal VCC = 5 V 3 V PP BW Flatness CTi CTo Bandwidth at -3 db Y/CVBS RGB Y/C mixer (on VOUT-RF) VIN = VPP VIN = VPP VIN = VPP, VINC = muted Spread of gain in video band (5 khz - 5 MHz) Y/CVBS VIN = VPP RGB VIN = VPP Y/C Mixer (on VOUT-RF) VIN = VPP, VINC = muted Crosstalk isolation between input channel Crosstalk isolation between output channel VIN = VPP at f = 4.43 MHz, on one point VIN = VPP at f = 4.43 MHz, on one point, RLOAD = 5Ω 2 2 8 5 5 +/-.5 +/-.5 +/-.5 MHz MHz MHz db db db 6 db 5 db R OUT Output resistance 5 Ω G RGB Gain at RGB outputs V IN = V pp, gain set to 6 db 5.5 6 6.5 db G RGBM Gain matching between R, G, B V IN = V PP, gain set to 6 db -.3.3 db G RGBSTE Step of gain 3 db to 6 db.75.25 db P G YCVBS Gain on Y,/CVBS channels V IN = V PP 5.5 6 6.5 db G YCVBSM Gain matching between Y, CVBS inputs V IN = V PP -.5.5 db DC OUT DC output voltage Bottom sync pulse.6 V DC OUT RF RF output voltage Bottom sync pulse V DPHI Differential phase V IN = V PP at f = 4.43 MHz 5 deg. DG Differential gain V IN = V PP at f = 4.43 MHz 5 % Mute Mute suppression V IN = V PP at f = 5 MHz on one point -55 db LNL Luminance non-linerarity.3 3 % VSN Video S/N ratio Refer to Note 65 db Note: S/N = 2 log (V OUT Black to White =.7 V PP / V Noise (mv RMS ) weighted CCIR 567). Doc ID 9754 Rev 2 /3

Electrical characteristics STV642A 2.7 Chroma section characteristics T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Table 7. Chroma section characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit V DCIN DC input level 3 V R IN Input resistance 3 5 kω C IN Input capacitance 2 pf V IN Max input signal.5 V PP DYN Dynamic output signal 3 V PP DC OUT DC output VCR voltage 2.2 V CBW Chroma Bandwidth C IN = V PP at -3 db MHz CTi CTo Crosstalk isolation between input channel Crosstalk isolation between output channel 2.8 Blanking section V IN = V PP at f = 4.43 MHz, on one input V IN = V PP at f = 4.43 MHz, on one input, R LOAD = 5 Ω T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V 55 db 5 db R OUT Output resistance 5 W G OUTC Gain at OUTC V IN = V pp 5.5 6 6.5 db G CM Gain matching between C inputs V IN = V PP -.5.5 db Mute CToYdel Mute suppression Chroma to luma delay, source Y/C V IN = V PP at f = 4.43 MHz, on one input Pin other than VOUT_RF, V PP @ 4.43 MHz, -55 db 2 ns CToYdel Chroma to luma delay, source Y/C Pin VOUT_RF 2 ns Table 8. R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Slow blanking section Symbol Parameter Test condition Min. Typ. Max. Unit Input mode SLBlow Input low level threshold 2.5 3.25 4 V SLBhigh Input high level threshold 7.5 8.25 9 V I IN Input current 5 µa Output mode SLBlow Output low level (int. TV).2.5 V 2/3 Doc ID 9754 Rev 2

STV642A Electrical characteristics Table 8. Slow blanking section (continued) Symbol Parameter Test condition Min. Typ. Max. Unit SLBmed Output medium level (ext. 6/9) 5 5.75 6.5 V SLBhigh Output high level (ext. 4/3) 2 V Table 9. Fast blanking section Symbol Parameter Test condition Min. Typ. Max. Unit Input mode FBlow/high Input low/high level threshold.4.7.9 V I IN Input current 2 µa Output mode FB LOW Output low level.5 V R LOAD = 5 Ω FB HIGH Output high level 3. 3.4 3.8 V FB DEL FB TRANS Table. Fast blanking RGB delay FB transitions at FB output Rise Time Fall Time C_Gate function output At 5% on digital RGB transients, at 2 V on FB rise transient, at V on FB fall, C LOAD = pf maximum C LOAD = pf maximum between % and 9% between 9% and % 5 ns Symbol Parameter Test condition Min. Typ. Max. Unit C_GATE-H Pull-up resistor value to V CCB 2 kω C_GATE-L Output low level I IN = ma I IN = ma Interrupt output (refer to Note ) Symbol Parameter Test condition Min. Typ. Max. Unit IT-Leak High level leakage External pull-up to 5 V µa IT-Low Output low level (active) I IN = ma I IN = ma Table. Address selection input Symbol Parameter Test condition Min. Typ. Max. Unit ADDsel_L Address selection low level.2 V ADDsel_H Address selection high level 2.5 V DD V I LEAK Leakage current µa.3.7.3.7 ns ns V V V V Note: The interrupt is forced to a low level when a change is detected on slow blanking inputs. It can be used in standby mode to wake up the microprocessor. It is released when the I 2 C bus register is read. Doc ID 9754 Rev 2 3/3

Electrical characteristics STV642A 2.9 I²C bus characteristics T amb = 25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6Ω, R LOUTA = kω, R GV = 5Ω, R LOUTV = 5Ω, unless otherwise specified. Table 2. I²C bus characteristics Symbol Parameter Test condition Min. Typ. Max. Unit SCL V IL Low level input voltage -.3.5 V V IH High level input voltage 2.3 5.5 V I LI Input leakage current V IN = to 5.5 V - µa SDA V IL Low level input voltage -.3.5 V V IH High level input voltage 2.3 5.5 V I LI Input leakage current V IN = to 5.5 V - µa C I Input capacitance pf t R Input rise time.5v to 3V µs t F Input fall time 3 V to.5 V 3 ns V OL Low level output voltage I OL = 3 ma.4 V Timing t F Output fall time 3 V to.5 V 25 ns C L Load capacitance 4 pf t LOW Clock low period 4.7 µs t HIGH Clock high period 4 µs t SU,DAT Data setup time 25 ns t HD,DAT Data hold time 34 ns t SU,STO Setup time from clock high to stop 4 µs t BUF Start setup time following a stop 4.7 µs t HD,STA Start hold time 4 µs t SU,STA Start Setup time following clock low to high transition 4.7 µs Note: The device can also operate at 4 khz and is capable of interfacing with +3.3 V or + 5 V logic levels. 4/3 Doc ID 9754 Rev 2

STV642A Electrical characteristics Figure 4. I ² C bus timing (start, stop) Doc ID 9754 Rev 2 5/3

I2C bus selection STV642A 3 I 2 C bus selection Data transfers follow the usual I 2 C format; that is, after the start condition (S), a 7-bit slave address is sent, followed by an eight-bit data direction bit (W). An 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register. The IC s I 2 C bus decoder enables the automatic incrementation mode in write mode. String format Write only mode (S = Start condition, P = Stop condition, A = Acknowledge) S Slave address A Sub-address A Data A P Read only mode S Slave address A Data A P Slave address Address A6 A5 A4 A3 A2 A A Value Auto increment mode S Slave address 3. I 2 C bus addresses Table 3. Reg addr (hex) Audio A Sub-address A Data A Data A Write address:, read address: Selection pin grounded address: =, write address = 94(hex), read address = 95(hex) Selection pin to supply address: =, write address = 96(hex), read address = 97(hex) Input signal summary (write mode) TV stereo mono... Datan A P Sub-address Sub-address + Sub-address + N Data d7 d6 d5 d4 d3 d2 d d VCR stereo Mono TV /6 db TV volume-62 db to db - 2 db steps Soft volume mode Not used (see Note ) VCR audio switch control CINCH audio gain TV/CINCH audio switch control 6/3 Doc ID 9754 Rev 2

STV642A I2C bus selection Table 3. Reg addr (hex) Input signal summary (write mode) (continued) Data d7 d6 d5 d4 d3 d2 d d Video 2 VCR Chroma muted VCR video and Chroma switch control TV Chroma muted TV video and Chroma switch control 3 RGB and FB tri-state RGB gain RGB switch control Fast blanking mode/input selection Miscellaneous 4 IT enable SLB mode Not used (see Note ) Note: Unused data must be set to. VCR-C output control 5 VCR slow blanking TV slow blanking STB-BY 6 Table 4. Reg. addr (hex) RF outputs TV outputs TV audio output Description Soft volume change Level adjustment 6 db extra gain TV stereo or mono mode CINCH outputs Bits 5 VCR outputs VCR-C gate control RF trap filter control ENC audio Input gain /6/9 db AU inputs TV inputs RF adder control VCR R/C sub clamp VCR inputs TV R or C output selection ENC R/C sub clamp ENC inputs Data d7 d6 d5 d4 d3 d2 d d Active Disabled Comments db -62 db (-2 db/step) db +6 db = stereo = mono Doc ID 9754 Rev 2 7/3

I2C bus selection STV642A Table 5. Reg. addr (hex) Audio selection & VCR audio output Data Description Bits d7 d6 d5 d4 d3 d2 d d Comments TV & CINCH audio output selection 3 Muted Encoder L/R selected VCR L/R selected AU L/R selected TV L/R selected Not allowed Not allowed Not allowed CINCH audio gain db Follow TV gain VCR audio output selection VCR stereo or mono mode Table 6. TV & VCR video selection Reg. addr (hex) 2 Description TV video output selection TV Chroma output control VCR video output selection 2 Bits 3 3 VCR Chroma output control Data d7 d6 d5 d4 d3 d2 d d Muted Encoder L/R selected TV L/R selected AU L/R selected = stereo = mono Comments Y/CVBS muted & Chroma muted Y/CVBS_ENC & R/C_ENC Y_ENC & C_ENC Y/CVBS_VCR & R/C_VCR CVBS_AU & Chroma muted Not allowed Not allowed Not allowed Chroma defined by d2dd Chroma force to mute Y/CVBS muted & Chroma muted Y/CVBS_ENC & R/C_ENC Y_ENC & C_ENC CVBS_TV & Chroma muted CVBS_AU & Chroma muted Not allowed Not allowed Not allowed Chroma defined by d6d5d4 Chroma force to mute 8/3 Doc ID 9754 Rev 2

STV642A I2C bus selection Table 7. Reg. addr (hex) RGB & fast blanking outputs Data Description Bits d7 d6 d5 d4 d3 d2 d d Comments 3 Table 8. Reg. addr (hex) 4 Fast blanking control 2 RGB selection 2 RGB gain 2 RGB and fast blanking control RF & miscellaneous control Description Bits R/C TV output selection RF output: adder control and chroma sub-carrier filter selection C_Gate output control C_VCR output control Slow blanking mode IT enable Data d7 d6 d5 d4 d3 d2 d d 2 FB forced to low level FB forced to high level FB from encoder FB from VCR Muted RGB_ENC selected RGB_VCR selected Not allowed +6 db gain +5 db gain +4 db gain +3 db gain + db extra gain +3 db for weak input signals RGB and FB outputs high impedance state RGB and FB outputs active Comments Red signal selected Chroma signal selected CVBS to RF output Y + C to RF output Filter not active Filter active High level Low level Tri-state mode (high impedance) Active Normal mode SLB TV is driven by SLB VCR No interrupt flag IT enable Doc ID 9754 Rev 2 9/3

l I2C bus selection STV642A Table 9. Reg. addr (hex) Slow blanking & inputs contro Data Description Bits d7 d6 d5 d4 d3 d2 d d Comments 5 Table 2. Reg. addr (hex) 6 Encoder R/Csub clamp VCR R/Csub clamp Encoder input level adjustment Slow blanking TV SCART Slow blanking VCR SCART ENC inputs VCR inputs TV inputs AU inputs VCR outputs Standby modes Description CINCH outputs TV outputs 2 2 2 Bits RFmod outputs Data d7 d6 d5 d4 d3 d2 d d Full stop Bottom level clamp Average level clamp Bottom level clamp Average level clamp db for normal audio inputs +6 db for weak audio inputs +9 db for weak audio inputs Input mode only Output < 2 V Output 6/9 format Output 4/3 format Input mode only Output < 2 V Output 6/9 format Output 4/3 format Inputs active Inputs disabled Inputs active Inputs disabled Inputs active Inputs disabled Inputs active Inputs disabled Comments Audio & video outputs ON Audio & video outputs OFF Audio & video outputs ON Audio & video outputs OFF Audio & video outputs ON Audio & video outputs OFF Audio & video outputs ON Audio & video outputs OFF Only I 2 C bus and slow blanking detection parts are supplied. 2/3 Doc ID 9754 Rev 2

STV642A I2C bus selection Table 2. Reg. addr (hex) Output signals (read mode) Data Description Bits d7 d6 d5 d4 d3 d2 d d Comments Slow blanking TV SCART 2 Input <2 V Input 6/9 format Input 4/3 format Slow blanking VCR SCART 2 Input <2 V Input 6/9 format Input 4/3 format Interrupt flag No change since read One change has been detected (refer to Note ) Note: The interrupt flag will be cleared when this register is read. To prepare for a new interrupt, a must be re-written in the IT enable bit (Reg. 4, d7). 3.2 Power-on reset bus register initial conditions Reg. addr (hex) Power-on reset is active when the supply V DD is less than 3.5 volts. Non-significant bits () are pre-set to. Data d7 d6 d5 d4 d3 d2 d d Comments Audio TV and cinch outputs are in stereo mode, db gain adjustment. TV, cinch and VCR audio outputs are muted. VCR output is in stereo mode. 2 VCR, TV and RFmod video outputs are muted. 3 Fast blanking is forced to. RGB outputs are muted and in high impedance. 4 C_GATE is high. C_VCR is high impedance. 5 Encoder and VCR R/Csub bottom level clamp, RGB outputs 6 db gain, and slow blanking parts are in read mode. 6 All internal blocks are ON. Doc ID 9754 Rev 2 2/3

I2C bus selection STV642A Figure 5. Volume control characteristics ±.5 db 8 3 Step Number -36 ±.5 db -62 db + 2 db -.5 db 22/3 Doc ID 9754 Rev 2

STV642A Input/output groups 4 Input/output groups Figure 6. Bottom clamped video inputs (pins 2, 4, 6, 2, 4, 8, 2, 62, and 64) Figure 7. R/C clamped video inputs (pins and 6 V CC 5V V CC 5V 5 kω 2V + V D R/C inputs may be configured either as a bottom clamped input or as an average clamped input. In either case, the simplified input schematic is very close to one of the graphics shown above. Protected ppad tri Figure 8. Fast blanking inputs (pins 5, 5) Figure 9. Average clamped video inputs (pin 8) V CCB 5V Protected pad tri V CC 5V Protected ppad I B VCC 5 V 25 kω 25 kω tri 3V Doc ID 9754 Rev 2 23/3

Input/output groups STV642A Figure. C gate logical output (pin 52) Figure. Fast blanking output (pin 49) V DD 5V V CCB 5V V CCB 5V V CCB 5V 8 kω 5 ohms Protected pad Protected pad Figure 2. Video outputs (pins 38, 4, 42, 44, 46, 48) Protected pad ib V CC 5V V CCB,2...7 5V Protected pad Figure 3. Audio inputs (pins 7, 9, 3, 9, 2, 22, 23) V CCA 9V Protected pad Figure 4. Slow blanking I/O (pins 59, 6) Figure 5. Trap filter (pin 34) V CC 2 V kω V CC2 2 V V CC 5V 25 kω kω Protected pad kω I B 5 kω Ω V CCB5 5V V CC /2 55 kω Protected pad 24/3 Doc ID 9754 Rev 2

STV642A Input/output groups Figure 6. Audio outputs (pins 27, 28, 29, 3, 32, 33,35) Figure 7. Interrupt output (pin 58) V CCAO I2 V V DD 5V Float 6 W 4 Ω Protected pad Protected pad Figure 8. 2 C bus (SDA) (pin 56) Figure 9. I 2 C bus (ADD) (pin 54) V DD 5V Protected Pad Figure 2. I²C bus (SCL) (pin 55) V DD 5V Protected pad Float Acknowledge kω Protected pad Protected pad Float kω V DD 5V Float kω Doc ID 9754 Rev 2 25/3

Input/output groups STV642A Figure 2. Power supply connection V CC B V CC B2 V CC B3 V CC B4 V CC B5 V CC A V CC A V CC V CC 2 V DD Float 47 45 43 39 37 3 24 63 53 2 V V 2 V 5V 4 GNDP 25 7 5 57 GNDA GNDref GNDV GDD These symbols represent some huge diode and Zener-like components used for ESD protection of the device. They are not supposed to be paths for any current in normal operation mode. 26/3 Doc ID 9754 Rev 2

STV642A Application diagram 5 Application diagram Note: Figure 22. The application diagram presented here is an example only and is subject to change without notice. The real application diagram will depend on application conditions and constraints. Application diagram Modulator 4.43MHzTrap STV642A For more details refer to the STV642 Application Note. Doc ID 9754 Rev 2 27/3

Package mechanical data STV642A 6 Package mechanical data Figure 23. 64 pin, LQFP64L (low-profile quad flat package) (4 x 4 x.4 mm) Table 22. Dimensions LQFP64L package dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A.6.63 A.5.5.2.6 A2.35.4.45.53.55.57 b.3.37.45.8.5.8 c.9.2.35.79 ccc..39 D 5.8 6. 6.2.622.63.638 D 3.8 4. 4.2.543.55.559 D3 2..472 e.8.35 E 5.8 6. 6.2.622.63.638 28/3 Doc ID 9754 Rev 2

STV642A Package mechanical data Table 22. LQFP64L package dimensions (continued) Millimeters Inches Dimensions Min. Typ. Max. Min. Typ. Max. E 3.8 4. 4.2.543.55.559 E3 2..472 L.45.6.75.8.24.3 L..39 Degrees k minimum 3.5 typical 7 maximum Doc ID 9754 Rev 2 29/3

Revision history STV642A 7 Revision history Table 23. Document revision history Date Revision Changes 24-Jan-26 Initial release. 24-Apr-27. Reformatted to the new corporate template. Corrections to Figure 22: Application diagram on page 27 and addition of application diagram disclaimer. 9-Jun-27.2 Changed package type from TQFP64 to LQFP64L. Updated Figure 23: 64 pin, LQFP64L (low-profile quad flat package) (4 x 4 x.4 mm) on page 28. Updated Table 22: LQFP64L package dimensions on page 28. -Jul-27.3 Minor corrections. 2-Sep-29 2 Minor corrections. 3/3 Doc ID 9754 Rev 2

STV642A Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. 29 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 9754 Rev 2 3/3