Registers & ounters Logic and igital System esign - S 33 Erkay Savaş Sabanci University
Registers Registers like counters are clocked sequential circuits A register is a group of flip-flops Each flip-flop capable of storing one bit of information An n-bit register consists of n flip-flops capable of storing n bits of information besides flip-flops, a register usually contains combinational logic to perform some simple tasks In summary flip-flops to hold information combinational logic to control the state transition 2
ounters A counter is essentially a register that goes through a predetermined sequence of states FF FF flip-flops FFN ombinational logic 3
Uses of Registers and ounters Registers are useful for storing and manipulating information internal registers in microprocessors to manipulate data ounters are extensively used in control logic P (program counter) in microprocessors 4
4-bit Register R REG clear R 2 2 2 2 3 3 R 3 3 clock R clear 5
Register with Parallel Load Load R R 2 2 R 3 3 clock clear R 6
Loading Register clock load inputs 7
Register Transfer - load R n R2 R2 R clock clock R load R2 8
Register Transfer - 2 n-bit adder n n load R R2 clock R R + R2 9
atapath & ontrol Unit ontrol signals ontrol inputs ontrol Unit Status signals atapath ata outputs ontrol outputs ata inputs
Shift Registers A register capable of shifting its information in one or both directions Flip-flops in cascade serial input SI SO serial output clock The current state can be output in n clock cycles
Serial Mode A digital system is said to operate in serial mode when information is transferred and manipulated one bit a time. SI SO SI SO shift register A shift register B clock shift control clock shift control clk clk clk T T 2 T 3 T 4 2
Serial Transfer Suppose we have two 4-bit shift registers Timing pulse Shift register A Shift register B initial value After T After T 2 After T 3 After T 4 B A 3
Serial Addition In digital computers, operations are usually executed in parallel, since it is faster Serial mode is sometimes preferred since it requires less equipment clock shift control SI shift register A SO a b _in FA S serial input SI shift register B SO reset 4
Example: Serial Addition A and B are 2-bit shift registers reset clock shift control SR-A SR-B serial input _in 5
6 esigning Serial Adder - X X X X X X X X K J S y x Flip-flop inputs Output Next state Inputs Present state (t+) = J + K J = xy K = x y = (x + y) S = x y
esigning Serial Adder - 2 J = xy K = x y = (x + y) S = x y clock shift control SI shift register A SO = x S serial input SI shift register B SO = y J K reset 7
Universal Shift Register apabilities:. A clear control to set the register to. 2. A clock input 3. A shift-right control 4. A shift-left control 5. n input lines 6. A parallel-load control 7. n parallel output lines 8. A shift-control 8
Universal Shift Register parallel outputs A 3 A 2 A A clear clk s s 2 3 4 MUX 2 3 4 MUX 2 3 4 MUX 2 3 4 MUX 2 serial input for shift-right parallel inputs serial input for shift-left 9
Universal Shift Register Mode ontrol s s Register operation No change Shift right Shift left Parallel load 2
ounters A counter is basically a register that goes through a prescribed sequence of states upon the application of input pulses input pulses are usually clock pulses Example: n-bit binary counter count in binary from to 2 n - lassification. Ripple counters flip-flop output transition serves as the pulse to trigger other flip-flops 2. Synchronous counters flip-flops receive the same common clock as the pulse 2
Binary Ripple ounter 3-bit binary ripple counter 2 3 4 5 6 7 Idea: to connect the output of one flip-flop to the input of the next high-order flip-flop We need complementing flip-flops We can use T flip-flops to obtain complementing flip-flops or JK flip-flops with its inputs are tied together or flip-flops with complement output connected to the input. 22
4-bit Binary Ripple ounter count T R A count R A T R A R A T R A 2 R A 2 logic- clear T R A 3 clear R 23 A 3
4-bit Binary Ripple ounter count T R A Suppose the current state is T R A What is the next state? A = ( ) A = ( ) T R A 2 A 2 = ( ) A 3 = logic- T R A 3 next state: Binary count-down counter clear 24
State diagram B Ripple ounter 25
26 B Ripple ounter State transitions A A A 2 A 3
B Ripple ounter with JK FFs count J K A J K A J K A 2 J K A 3 logic- 27
Multi-digit B ounter A 3 A 2 A A A 3 A 2 A A A 3 A 2 A A B ounter B ounter B ounter count pulses 3-digit B counter 28
Synchronous ounters There is a common clock that triggers all flip-flops simultaneously If T = or J = K = the flip-flop does not change state. If T = or J = K = the flip-flop does change state. esign procedure is so simple no need for going through sequential logic design process A is always complemented A is complemented when A = A 2 is complemented when A = and A = so on 29
4-bit Binary Synchronous ounter count enable J K A J K A Polarity of the clock is not essential J K A 2 J K clock A 3 to next stage 3
Up-own Binary ounter When counting downward the least significant bit is always complemented (with each clock pulse) A bit in any other position is complemented if all lower significant bits are equal to. For example: Next state: For example: Next state: 3
Up-own Binary ounter up down T A T A T A 2 The circuit clock 32
33 Synchronous B ounter Better to apply the sequential circuit design procedure y T T 2 T 4 T 8 A A 2 A 4 A 8 A A 2 A 4 A 8 Flip-Flop inputs output Next state Present state
Synchronous B ounter The flip-flop input equations T = T 2 = A 8 A T 4 = A 2 A T 8 = A 8 A +A 4 A 2 A Output equation y = A 8 A ost Four T flip-flops four 2-input AN gates one OR gate one inverter 34
Binary ounter with Parallel Load count load J K A J K A 2 J K A 2 clock carry output clear 35
Binary ounter with Parallel Load Function Table clear clock load ount Function X X X clear to X load inputs count up no change 36
Other ounters Ring ounter Timing signals control the sequence of operations in a digital system A ring counter is a circular shift register with only one flip-flop being set at any particular time, all others are cleared. shift right T T T 2 T 3 initial value 37
Ring ounter Sequence of timing signals clock T T T 2 T 3 38
Ring ounter To generate 2 n timing signals, we need a shift register with 2 n flip-flops or, we can construct the ring counter with a binary counter and a decoder count T T T 2 T 3 2x4 decoder 2-bit counter ost: 2 flip-flop 2-to-4 line decoder ost in general case: n flip-flops n-to-2 n line decoder 2 n n-input AN gates 39
Johnson ounter A k-bit ring counter can generate k distinguishable states The number of states can be doubled if the shift register is connected as a switch-tail ring counter X Y Z T X Y Z T clock 4
Johnson ounter ount sequence and required decoding sequence number 2 3 4 5 6 7 8 Flip-flop outputs X Y Z T Output X T XY YZ ZT XT X Y Y Z Z T 4
ecoding circuit Johnson ounter S S S 2 S 3 S 4 S 5 S 6 S 7 X Y Z T clock 42
Unused States in ounters 4-bit Johnson counter 43
44 Johnson ounter Outputs Inputs T Z Y X T Z Y X
K-Maps XY ZT XY ZT X = T Y = X XY ZT XY ZT Z = XY + YZ T = Z 45
Remedy Unused States in ounters Z = Y(X+Z) X Y Z T clock 46
Unused States in ounters State diagram 47