Stand-alone or In-System Programming Applications for AT18F Series Configurators 1. Overview The AT18F Series Configurators, which include AT18F010-30XU (1M), AT18F002-30XU (2M), AT18F040-30XU (4M), and AT18F080-30XU (7M) devices, are pin-compatible/functional compatible with Xilinx XxxS Series Platform Flash PROMs. These devices can be used to configure Xilinx Spartan -II, Spartan-IIE, Spartan-3, Spartan-3E, Spartan-3A, Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4LX/FX/SX, and Virtex-5-LX/LXT/SXT Series FPGAs, as well as AT40KAL Series FPGAs. This application note provides the application circuit diagrams and programming methods to program and configure and s in its Master Serial mode. To perform stand-alone (drop-in) programming of the AT18F Series Configurators, the user could simply select the device algorithm in the programming software to program the configurator with s AT18F-DK3 programming kit or any industrial standalone programmers (third-party programmers such as BP, Data I/O, Hi-Lo, etc.) that supports AT18F Series Configurators. Intel MCS hex object file (*.mcs) that is generated for a compatible density of Xilinx Platform Flash PROM can be used to program the AT18F Series Configurator for application. For AT40KAL FPGA applications, an MCS file (also called *.hxr), which is generated from IDS software, can also be renamed to *.mcs in order to use it as an Intel MCS86 hex object file in order to program the AT18F Series Configurator for configuring AT40KAL Series FPGAs. After the configurator is programmed, it can be dropped into the target system board to configure the FPGA such as shown in Figures 1-2 and 1-3. AT18F Series Configurators Application Note Figure 1-1. Stand-alone (Drop-in) Programming Method for ATF18FX Series Configurator Programming Software Target System: AT18F AT18FX Stand-alone Programmer: AT18F-DK3 or Third-party Programmers that Support the AT18F Series Configurators
Figure 1-2. Stand-alone (Drop-in) Programming Circuit for AT18F Series Configurator in AT40KAL FPGA Application VCCJ 3.3V AT40KAL FPGA MODE PINS (M2, M1, M0) VCCO C CON INIT RESET Note: 1. For the appropriate voltage setting refer to the device datasheet. Figure 1-3. Stand-alone (drop-in) Programming Circuit for AT18F Series Configurator in Application VCCO (2) VCCO (2) VCCO (2) Note (3) C Notes: 1. For the appropriate voltage setting refer to the device datasheet. 2. Different families of might have different mode pin labels. Connecting all configuration mode pins to circuit ground () will setup the Master Serial Mode of the FPGA for configuration loading. Refer to the appropriate FPGA datasheet for more details. 3. Different external Pull-up resistor value might be required on pin of the FPGA, refer to FPGA datasheet for details. 2 Stand-alone/ISP for the AT18F
LED Stand-alone/ISP for the AT18F For Stand-alone (Drop-in) Programming, since the configurator is pre-programmed in standalone programmer before dropping into the target board to configure the FPGA, JTAG pins (,,, and pins) will not be used in such case. However, connecting JTAG pins to JTAG ISP header as shown in the JTAG ISP circuit is also valid to use for drop-in (Stand-alone programming) of the configurator. To perform In-System Programming (ISP) through JTAG (Joint Test Action Group) interface, an JTAG ISP cable is required in order to provide communication between the programmer and the configurator as shown in Figure 1-4. Figures 1-5, 1-6 and 1-7 show the recommended ISP circuits. JTAG Configurator Programming System (JCPS) software, which supports AT18F-DK3 programming kit can be downloaded from web site at: http://www.atmel.com/dyn/products/tools.asp?family_id=625 For In-System Programming of the AT18F Series Configurator with the FPGA in the JTAG chain, you can follow the tutorial in the help menu of the JCPS software to set the FPGA in 6-bit or 10-bit Bypass mode depends on the FPGA family. Also, Figures 1-6 and 1-7 only show the AT18F Series Configurators connected in the JTAG chain as the first device, and the FPGA connected in the JTAG chain as the second device. However, such connection order can be inverted to have the FPGA connected in the JTAG chain as the first device, and the Configurator connected in the JTAG chain as the second device. Figure 1-4. JTAG In-System Programming Method for AT18F Series Configurator (1) Programming Software ISP DOWNLOAD CABLE Color Stripe Cable Converter AT18FX Target System: AT18F Note: 1. JCPS Software does not support Xilinx JTAG programming cable. The JTAG ISP cable ATDH1151VPC or the JTAG ISP cable with a cable converter, included in the AT10F- DK3 Development Kit, must be used for programming AT18F Series devices. 3
Figure 1-5. JTAG In-system Programming Circuit Diagram for AT18F Series Configurator in AT40KAL Series FPGA Application AT40KAL FPGA JTAG ISP Header C MODE PINS (M2, M1, M0) VCCJ CON INIT RESET Note: 1. For the appropriate voltage setting, refer to the device datasheet. Figure 1-6. JTAG In-system Programming Circuit for AT18F Series Configurator to Configure VCCO (1,2) VCCO (1,2) VCCO (1,2) Note (3) C JTAG ISP Header VREF Notes: 1. For the appropriate voltage setting, refer to the device datasheet. 2. Different families of might have different mode pin labels. Connecting all Configuration mode pins to circuit ground () will setup the Master Serial Mode of the FPGA for configuration loading. Refer to the appropriate FPGA datasheet for details. 3. Different external Pull-up resistor value might be required on pin of the FPGA. Refer to FPGA datasheet for details. 4. Ground pins () in JTAG ISP header are optional pins. These pins are not required for programming the device on the exiting target boards. However, for new design, it is recommended to have such connection to have common ground between target board and the programmer. Also, Serial resistors on,, and lines are depending on VCCJ setting (Resistor = 0 ohm for VCCJ = 2.5V, and Resistor > 68 Ohms for VCCJ = 3.3V). 4 Stand-alone/ISP for the AT18F
Stand-alone/ISP for the AT18F Cascaded Configurators can be used to configure multiple FPGAs in Master Serial and Slave Serial modes as shown in Figure 1-7. This circuit not only can be used for JTAG In-System programming of the AT18F Series Configurators with JTAG ISP cable, it can also be used for drop-in (stand-alone) programming after both AT18F Series Configurators are pre-programmed by stand-alone programmer. Figure 1-7. JTAG In-system Programming Circuit for Cascaded AT18F Series Configurators to Configure Multiple s (1) (1) VCCJ VCCO VCCINT Device #2 Device #1 VCCO (2) VCCO (2) VCCO (2) (1) Note (3) DOUT C C JTAG ISP Header O O VREF Notes: 1. For the appropriate voltage setting, refer to the device datasheet. 2. Different families of might have different mode pin labels and mode pin settings. Reference to datasheet to setup Master Serial mode and Slave Serial mode for FPGA configuration loading. 3. Different external Pull-up resistor value might be required on pin of the FPGA. Refer to FPGA datasheet for details. 4. Ground pins () in JTAG ISP header are optional pins. These pins are not required for programming the device on the exiting target boards. However, for new design, it is recommended to have such connection to have common ground between target board and the programmer. Also, Serial resistors on,, and lines are depending on VCCJ setting (Resistor = 0 Ohm for VCCJ = 2.5V, and Resistor > 68 Ohms for VCCJ = 3.3V). Important Note All circuit connection diagrams in this document are only provided as reference. Designer s should study the AC/DC characteristics of the devices in order to construct the circuit for their own applications 5
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