Chapter 7 Multi-Level Gate Circuits NAND and NOR Gates iaojun Qi Multi-Level Gate Circuits Design Find the inputs and outputs Find the relationship between inputs and outputs (i.e., For each input combination, find the corresponding output. You may build a truth table to do it.) Simply the function Implement the circuit Some Terminologies The number of levels of gates: The maximum number of gates cascaded in series between a circuit input and the output. AND-OR circuit: A two-level circuit composed of a level of AND gates followed by an OR gate at the output. OR-AND circuit: A two-level circuit composed of a level of OR gates followed by an AND gate at the output. OR-AND-OR circuit: A three-level circuit composed of a level of OR gates followed by a level of AND gates followed by an OR gate at the output. Some Terminologies (Cont.) Circuit of AND and OR gates implies no particular ordering of the gates. The output gate may be either AND or OR. The four common forms for the final implementation are: AND-OR circuit NAND-NAND circuit OR-AND circuit NOR-NOR circuit Four-Level Realization of Z Three-Level Realization of Z
Find a circuit of AND and OR gates to realize f(a,b,c,d)= m(1,5,6,10,13,14) Minimized SOP: F=a c d+bc d+bcd +acd F=a c d+bc d+bcd +acd =c d(a +b)+cd (a+b) Find the minimized POS by circling 0 s F = c d +ab c +cd+a b c F=(c+d)(a +b+c)(c +d )(a+b+c ) F=(c+d)(a +b+c)(c +d )(a+b+c ) F=(c+d)(a +b+c)(c +d )(a+b+c ) =[c+d(a +b)][c +d (a+b)] =(c+a d+bd)(c +ad +bd )
Summary For this particular example: The best 2-level solution had an AND gate at the output. The best 3-level solution had an OR gate at the output. In general, to be sure of obtaining a minimum solution, one must find both the circuit with the AND-gate output and the one with the OR-gate output. NAND and NOR Gates NAND and NOR gates are generally faster and use fewer components than AND or OR gates. Any logic function can be implemented using only NAND gates or only NOR gates. NAND gate or NOR gate forms a functionally complete set since any switching function can be expressed in terms of NAND gate or NOR gate. Similarly, the set AND, OR, and NOT forms a functionally complete set since any Boolean function can be expressed in terms of SOP and POS using only the AND, OR, and NOT operations. N-input NAND gate: F=( 1 2 n ) = 1 + 2 + + n N-input NOR gate: F=( 1 + 2 + + n ) = 1 2 n OR can be realized using AND and NOT AND and NOT are a functionally complete set of gates. NAND Gate Realization of NOT, AND, and OR What is the NOR Gate Realization of NOT, AND, and OR, respectively?
Design of 2-Level Circuits using NAND and NOR Gates Procedure for designing a minimum 2-level NAND-NAND circuit 1. Find a minimum SOP expression for F. 2. Draw the corresponding 2-level AND-OR circuit. 3. Replace all gates with NAND gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literals. Design of 2-Level Circuits using NAND and NOR Gates Procedure for designing a minimum 2-level NOR-NOR circuit 1. Find a minimum POS expression for F. 2. Draw the corresponding 2-level OR-AND circuit. 3. Replace all gates with NOR gates leaving the gate interconnections unchanged. If the output gate has any single literals as inputs, complement these literals. 4 Basic Forms for 2- Level Circuits 4 Basic Forms for 2- Level Circuits Section 7.3, p. 187 AND-OR to NAND-NAND Transformation It shows that the NAND-NOR form can realize only a product of literals and not a sum of products. Therefore, the other eight possible 2-level forms (AND- AND, OR-OR, OR-NOR, AND-NAND, NAND-NOR, NAND- OR, NOR-NAND, NOR-AND) are degenerate in the sense that they cannot realize all switching functions.
Design of Multi-Level NANDand NOR-Gate Circuits The procedure to design multi-level NAND-gate circuits is: 1. Simplify the switching function to be realized. 2. Design a multi-level circuit of AND and OR gates. The output gate must be OR. AND gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as OR-gate inputs. 3. Number the levels starting with the output gate as level 1. Replace all gates with NAND gates, leaving all interconnections between gates unchanged. Leave the inputs to levels 2, 4, 6, unchanged. Invert any literals which appear as inputs to levels 1, 3, 5, Design of Multi-Level NANDand NOR-Gate Circuits The procedure to design multi-level NOR-gate circuits is: 1. Simplify the switching function to be realized. 2. Design a multi-level circuit of AND and OR gates. The output gate must be AND. AND gate outputs cannot be used as AND-gate inputs; OR-gate outputs cannot be used as OR-gate inputs. 3. Number the levels starting with the output gate as level 1. Replace all gates with NOR gates, leaving all interconnections between gates unchanged. Leave the inputs to levels 2, 4, 6, unchanged. Invert any literals which appear as inputs to levels 1, 3, 5, Design of 2-Level, Multiple- Output Circuits Solution of digital design problems often requires the realization of several functions of the same variables. Although each function could be realized separately, the use of some gates in common between two or more functions sometimes leads to a more economical realization. Multi-Level Circuit Conversion to NAND Gates =ABC +ACD+A CD Karnaugh Maps for Equations (7-22) Realization of Equations (7-22)
Multiple-Output Realization of Equations (7-22) f1 = a bd+abd+ab c +b c f2 =c+a bd f3=bc+ab c +abd Determination of Essential Prime Implicants for Multiple-Output Realization Determination of Essential Prime Implicants for Multiple-Output Realization 1. Each minterm must have a flag to show which function it is a minterm of. 2. Two minterms can be combined only if they possess one or more common flags in addition to being logically adjacent. The resulting term from the combination carries only those flags that are common to both terms that were combined. 3. A term can be checked off from the list of terms only if all the flags that the term possesses appear in the resulting term when two terms are combined. Minimize Step 1: A( P, Q, R, S) = B( P, Q, R, S) = C( P, Q, R, S) = Minterm Minterm Index Functions 0 0000 AC 2 0010 ABC 4 0100 B 6 0110 B 10 1010 AC 12 1100 A 14 1110 C 15 1111 C m(0,2,10,12) m(2,4,6) m(0,2,10,14,15) Note that 0 can be combined only with 2, resulting with (0, 2) with a flag of AC. 0 and 4 cannot be combined since they have no common flag. Furthermore, 2 cannot be checked off since all the three flags of 2 cannot be attached to (0, 2) but 0 can be checked off.
Step 2: The following list shows the result of combining these terms. Term PQRS Flag (0,2) 00-0 AC (2,6) 0-10 B (2, 10) -010 AC (4,6) 01-0 B (10,14) 1-10 C (14, 15) 111- C Step 3: PI Flag (2) ABC (12) A (0,2) AC (2,6) B (2, 10) AC (4,6) B (10,14) C (14,15) C A 0 2 10 12 * * * B 2 4 6 * C 0 2 10 14 15 * * From this chart, we can see that all Prime Implicants (PIs) except (2), (2, 6) and (10, 14) are essential. The following are the minimum covers: Function A: (0, 2), (12), and (2, 10) Function B: (4, 6) and select (2, 6) as nonessential PI. Function C: (0,2), (14,15) and select (2,10) as nonessential PI. Multiple-Output NAND and NOR Circuits If all of the output gates are OR gates, direct conversion to a NAND-gate circuit is possible. If all of the output gates are AND gates, direct conversion to a NORgate circuit is possible. Multi-Level Circuit Conversion to NOR Gates