Switching Theor and Logical Design Class 3 Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -85
Toda Fundamental concepts of digital sstems (Mano Chapter ) Binar codes, number sstems, and arithmetic (Ch ) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch ) Combinatoric logical design including LSI implementation (Chapter 4) Haards, Races, and time related issues in digital design (Ch 9) Flip-flops and state memor elements (Ch 5) Sequential logic analsis and design (Ch 5) Snchronous vs. asnchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memor and Programmable logic (Ch 7) Minimiation of sequential sstems Introduction to Finite Automata Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -86
Boolean Functions in Terms of Minterms A logical function is TRUE if an of it s minterms are true: m m 4 m 7 F(,,) = Σ(,4,7) = + + = m + m 4 + m 7 Algebraic manipulation of the literal epression of the function is one wa to minimie it, manipulation of minterms is another Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -87
Two Variable Minterm Map Represent Boolean functions in terms of minterms in a Karnaugh map: m m m 2 m 3 Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -88
Two Variable Minterm Map Represent Boolean functions in terms of a Karnaugh map: m m m 2 m 3 Consider the XOR function F(, ) = = ' + ' = m + m 2 Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -89
Two Variable Minterm Map Represent Boolean functions in terms of a Karnaugh map: m m m 2 m 3 Consider the XOR function F(, ) = = ' + ' = m + m 2 Set the non-asserted minterms to ero Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -9
Minimiing Function of Two Variables F(, ) = ' + = m + m = ( ' + ) 2 3 = Covering adjacent minterms with a single region defines the variables needed to represent the function Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -9
Minimiing Function of Three Variables m m m 3 m 2 m 4 m 5 m 7 m 6 Minterms are numbered in Gra code order adjacent minterms differ in onl one variable If the function is asserted (i.e., TRUE) for both of these adjacent minterms, then the terms defined b those minterms do not depend on the variable that is changing between them Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -92
Three Variable Map m m m 3 m 2 m 4 m 5 m 7 m 6 Consider F(,,)=Σ(,3,7) F(,, ) = m + m + m 3 7 F(,, ) = = = = ' ' + ' + ' ' + ' + ' + '( ' + ) + ( ' + ) ' + Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -93
Three Variable Map m m m 3 m 2 m 4 m 5 m 7 m 6 Observations: All minterms must be covered Number of variables defining a sum term inversel proportional to number of minterms covered Number of sum terms required to define function equal to number of separate regions Maimie region sie Minimie number of regions Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -94
Three Variable Map For a 3-variable map: Covering 4 minterms with one 4-minterm region defines the function in terms of a single variable Covering the same 4 minterms with 2 2- minterm regions defines the function in terms of two terms, each requiring two variables. Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -95
Three Variable Map Adjacenc sometimes eists in subtle was: These four minterms are obviousl adjacent to each other. Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -96
Three Variable Map Adjacenc sometimes eists in subtle was: These four minterms are obviousl adjacent to each other. But so are these, if we consider the map to wrap around on itself Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -97
Four Variable Map w m m m 3 m 2 w w w w m 4 m 5 m 7 m 6 w w w w m 2 m 3 m 8 m 9 m 5 m 4 m m w w w w w w w w w The 4-variable map etends the concept of the 2- and 3-variable map Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -98
Minimiing Four Variable Map w m m m 3 m 2 m 4 m 5 m 7 m 6 m 2 m 3 m 8 m 9 m 5 m 4 m m w Minimie F(w,,,)=Σ(,2,3,5,7,8,,,3,5) F(w,,,)=+ + Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -99
Five Variable Map w w m m m 3 m 2 m 6 m 7 m 9 m 8 m 4 m 5 m 7 m 6 m 2 m 2 m 23 m 22 m 2 m 3 m 5 m 4 m 28 m 29 m 3 m 3 w w m 8 m 9 m m m 24 m 25 m 27 m 26 v= v= 5-variable map is etension of 4-variable map, adjacenc must be considered between pairs of 4-variable maps Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -
Minimiing Five Variable Map w w v w w v= w v= Minimie F(v,w,,,)=Σ(,8,9,,6,7,24,25,27,29,3) F(v,w,,,)=w+ +v Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -
Si Variable Map Keeping track of what minterms are adjacent becomes tedious Ensuring the maimum coverage for each term is challenging w m m m 4 m 5 m 2 m 3 m 8 m 9 w m 3 m 2 u= m 7 m 6 m 5 m 4 m m w m 32 m 33 m 36 m 37 m 44 m 45 m 4 m 4 m 35 m 34 m 39 m 38 m 47 m 46 m 43 m 42 w 6-variable maps usable, but perhaps the design needs to be modularied instead w v= v= w m m m 3 m 2 u= m 48 m 49 m 5 m 5 m 4 m 5 m 2 m 3 m 7 m 6 m 5 m 4 m 52 m 53 m 6 m 6 m 55 m 54 m 63 m 62 m 8 m 9 m m w m 56 m 57 m 59 m 58 w Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -2
Product of Sums Covering s Instead of s A function of N variables, F(v,v 2,,v N ), can be represented b a Karnaugh map with 2 N cells. (v,v 2,,v N ) = (,, ), (,, ),, (,,,) F( ), and it s Karnaugh map have K minterms ( s) and 2 N -K materms ( s) If K > 2 N -K, it might be easier to cover the materms rather than the minterms. E.g.: w w v= v= Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -3
Product of Sums Covering s Instead of s w w w w v= v= F(v,w,,,) has 4 terms F(v,w,,,) = w + w + vw +w v= v= F(v,w,,,) has 7 terms F(v,w,,,) = w + + v + + w + w + w Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -4
Don t Care Conditions Sometimes, not all possible output values are specified in sstem design, e.g.: Calculator, Clock, or Counter Circuit w=8 =4 =2 = f a e g b d c 2 3 4 BCD data 7 segment LCD 5 6 7 8 9 Consider the horiontal line in the middle of the displa (segment g): F g (w,,,)=σ(2,3,4,5,6,8,9), but we don t care what happens to minterms,, 2, 3, 4, or 5, since the displa will not be sent those states Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -5
Don t Care Conditions w\ w\ X X X X X X X X X X X X F(w,,,) = + + + w F (w,,,) = w + We are free to assign whatever values we want to for minterms,, 2, 3, 4, and 5. Assign them a value X to indicate the ma be covered, or not, whichever results in the simplest epression Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -6
Logical Completeness. AND, OR, NOT can implement an Boolean function The form a Logicall Complete set of operators Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -7
Logical Completeness. AND, OR, NOT can implement an Boolean function The form a Logicall Complete set of operators 2. NAND can implement AND and NOT directl: NOT = AND = Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -8
Logical Completeness. AND, OR, NOT can implement an Boolean function The form a Logicall Complete set of operators 2. NAND can implement AND and NOT directl: NOT = AND = 3. NAND can implement OR b DeMorgan s Law: = = NAND is logicall complete (so is NOR) Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -9
NAND Implementation of Sum of Products Consider an arbitrar Sum of Products: m A m B Σ(A,B,C) m C Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -
NAND Implementation of Sum of Products Consider an arbitrar Sum of Products: Add inversions at each term. This is allowed, since ( ) = m A m B Σ(A,B,C) m C Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -
NAND Implementation of Sum of Products Consider an arbitrar Sum of Products: Add inversions at each term. This is allowed, since ( ) = Convert output gate b DeMorgan s Law: m A m B Σ(A,B,C) m C Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -2
Wired-AND and Open Collector Tpical TTL totem-pole output circuit: +V +V I I out out I I TTL with Open Collector output circuit Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -3
Wired-AND and Open Collector Each gate asserts -output with no pull-up transistor, no gate can cause output to become. Eternal pull-up resistor needed Used for wiring multiple devices together on bus, but speed is limited +V +V +V +V Pull-up resistor Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -4
XOR Function Eclusive OR (XOR) = ' i + i ' w = (( w ) ) = ( w ) ( ) XOR applications: Addition, parit, data scramblers, encrption, shift register sequences Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -5
N-input XOR w = (( w ) ) = ( w ) ( ) These three designs are all logicall equivalent (for static signals) Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -6
Hard To Minimie Functions Consider this map: w w v= v= Isolated minterms cannot be grouped Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -7
Hard To Minimie Functions Consider this map: w w Cover part of the map with XOR Treat the rest normall F( v, w,,, ) = ( w')' i( v w ) + w' ' ' + w' v= v= Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -8
Hard To Minimie Functions Consider this map: w w Cover part of the map with XOR Treat the rest normall F( v, w,,, ) = ( w')' i( v w ) + w' ' ' + w' v= v= Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -9
Summar Fundamental concepts of digital sstems (Mano Chapter ) Binar codes, number sstems, and arithmetic (Ch ) Boolean algebra (Ch 2) Simplification of switching equations (Ch 3) Digital device characteristics (e.g., TTL, CMOS)/design considerations (Ch ) Combinatoric logical design including LSI implementation (Chapter 4) Haards, Races, and time related issues in digital design (Ch 9) Flip-flops and state memor elements (Ch 5) Sequential logic analsis and design (Ch 5) Snchronous vs. asnchronous design (Ch 9) Counters, shift register circuits (Ch 6) Memor and Programmable logic (Ch 7) Minimiation of sequential sstems Introduction to Finite Automata Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -2
Homework 3 due in Class 5 As alwas, show all work: Problems 3-5, 3-7, 3-8. Design a BCD to seven segment decoder for an 2 of the 6 segments (a-f) we did not discuss in class. Switching Theor and Logical Design Copright 24 Stevens Institute of Technolog -2