CMOS INTEGRATE CIRCUIT ESIGN TECHNIUES University of Ioannina Built In Self Test (BIST) ept. of Computer Science and Engineering Y. Tsiatouhas CMOS Integrated Circuit esign Techniques VLSI Systems and Computer Architecture Lab Overview. Embedded test pattern generation 2. Output response analysis 3. Linear feedback shift registers (LFSRs) 4. Circular BIST 5. Built in in logic blocks observer (BILBO) 6. The STAMPS architecture 7. LFSR reseeding and bit fixing 8. esign for iagnosis Built-In Self Test 2
A General Built In Self Test (BIST) Scheme Primary Inputs Chip Circuit Under Test () Primary Outputs Scan Chains Pattern Generator Control BIST Circuitry ROM + Test_Enable Signature Analyzer Pass/Fail In Built In Self Test schemes the test vectors are generated inside the chip and they are applied to the under the control of the BIST controller. The responses are compacted by the signature analyzer and the final value (signature), after test completion, is compared with the expected signature. In case of discrepancy the is characterized asdefective. Aproper signal (Pass/Fail) is activated to indicate a possible fault detection. Built-In Self Test 3 Pseudorandom Pattern Generation Linear Feedback Shift Registers LFSRs An alfsr acts as a pseudorandom pattern generator Flip () Flip () Flip (2) CK CK CK Step/Cycle [2...] 2 3 4 5 6 7 repetition! Built-In Self Test 4 2
The Linear Feedback Shift Register An LFSR is fully described by its characteristic polynomial. An LFSR with characteristic polynomial of Ν degree is capable to generate a maximal length cycle 2 Ν if its polynomial is a primitive polynomial. An Ν degree polynomial is primitive if it cannot be factored and it is divisible only by itself and, and it divides evenly the x k + polynomial only when for the integer k stands that k=2 N but not when k<2 N. Step [2] [] [] () () (2) 2 Flip x Flip x 2 Flip x 3 3 CK CK CK 4 5 6 P(x) =. x 3 +. x 2 +. x+ = x 3 +x+ 7 Built-In Self Test 5 LFSR Properties The maximal length cycle of an LFSR with a primitive characteristic polynomial is 2 Ν. In a maximal length cycle appears N+ times while appears N times. The sequence obtained at any stage j of the LFSR is one clock cycle delayed with respect to the sequence at stage j. Since the generated patterns by an LFSR have a predetermined distribution of grouping bits and the sequences from different stages are self correlated (pseudorandom patterns), some faults may be undetectable when this sequence of patterns is applied. These faults are called: random pattern resistant (RPR) faults. Built-In Self Test 6 3
LFSR in a Typical Test Configuration P(x)=x 4 +x 2 +x+ LFSR () () (2) (3) Flip x Flip x 2 Flip x 3 Flip x 4 CK CK CK CK Scan Chain Scan Chain 2 Scan Chain 3 Scan Chain 4 Built-In Self Test 7 Signature Analysis The most common signature analysis technique is the sequential compaction of the responses and the comparison of the final result (signature) with the expected one. The latter is derived by simulations on the. Usually, an LFSR is exploited for the response compaction. At the end of this operation the LFSR s contents is the signature of the circuit. A faulty circuit is expected to provide a different signature than this of a fault free circuit. Since response compaction may result in information loss, it is possible a faulty circuit to provide a signature identical to the expected one [the fault escapes detection (test escape) and the is characterized as fault free]. This type of information loss is called aliasing. The probability of aliasing using an LFSR of Ν stages is: P a =2 N Built-In Self Test 8 4
Output Response Compaction a) Bellmac architecture XOR L F S R b) Use of Multiple Input Shift Register MISR XOR Flip Flip Flip Flip M I S R Built-In Self Test 9 Random Pattern Resistant Faults % ΔFC rage Fault Cover RPR 2 3 4 5 6 7 8 # of Test Patterns Random Pattern Resistant (RPR) Fault Alleviation Techniques Weighted pseudorandom pattern generation Aliasing reduction (e.g. multiple LFSR or MISR, collect multiple signatures) LFSR reseeding Multiple polynomial LFSR (reconfigurable LFSRs) Use of extra deterministic tests stored in a ROM (bit fixing or bit flipping) Built-In Self Test 5
Reconfigurable LFSR (I) S S S2 () () (2) (3) Flip x Flip x 2 Flip x 3 Flip x 4 CK CK CK CK Multiple Polynomial LFSR (Reconfigurable LFSR) Standard Configuration Si (i) S i Z i S i Z i Mode Inactive (i) Active Built-In Self Test Reconfigurable LFSR (II) S2 S S x 4 (3) (2) () Flip Flip Flip x 3 x 2 x CK CK CK () Flip CK Multiple Polynomial LFSR (Reconfigurable LFSR) Modular Configuration Si () S i Z i S i Z i Mode Inactive Active Built-In Self Test 2 6
Equivalent LFSR esigns S S S2 () () (2) (3) Flip x Flip x 2 Flip x 3 Flip x 4 CK CK CK CK P(x)=x 4 +x 3 +x+ S2 S S x 4 (3) (2) () Flip Flip Flip x 3 x 2 x CK CK CK Flip CK () Built-In Self Test 3 Weighted LFSR Flip Flip Flip Flip Scan Chain Scan Chain 2 Scan Chain 3 Scan Chain 4 Built-In Self Test 4 7
Basic BIST Architectures (Ι) Inputs Outputs L F S R M I S R Chip Control ROM + XOR Test_Enable Pass/Fail Built-In Self Test 5 Basic BIST Architectures (ΙΙ) Chip Inputs can Input Boundary Sc Scan Chains Out tput Boundary Scan Outputs L F S R Control L F S R XOR + R O M Pass/Fail Built-In Self Test 6 8
Partitioning Autonomous BIST L F S R Sub Circuit C M U X M U X Sub Circuit C2 M I S R Built-In Self Test 7 Circular BIST STSR _ Combinational CL_ STSR_2 Combinational CL_2 Self Test Shift Register SI STSR _3 Combinational CL_3 SR_ SR_2 All STSRs operate Combinational either as LFSRs or MISRs Combinational Characteristic polynomial CL_4 +x m CL_5 m = # STSR Flip s STSR_4 STSR_5 SO Built-In Self Test 8 9
Circular BIST Flip j from logic to logic STSR Flip STSR FF N/T Z Mode Z j Normal S j j Test (LFSR MISR) S j S j+ UX M from scan FF to scan FF N/T j SR Flip B B Z Mode Reset S j Scan j Normal S j j Test (LFSR MISR) j B B from logic to logic SR FF j Z S j S j+ from scan FF to scan FF Built-In Self Test 9 Built In Blocks Observer BILBO Register A Combinational A Register B Combinational B Register C SI LFSR Combinational A BILBO Combinational B MISR C C2 SO C C2 Mode Scan LFSR + MISR Normal Built-In Self Test 2
BILBO Register Structure C 2 n BILBO Flip C2 SI SO BILBO Register 2 n Built-In Self Test 2 BILBO Normal Mode C 2 n BILBO Flip C2 SI SO C = C2 = 2 n Built-In Self Test 22
BILBO Scan Operation Mode C C2 SI 2 n BILBO Flip SO C = C2 = 2 n Built-In Self Test 23 C BILBO LFSR Operation Mode Constant Values 2 n BILBO Flip C2 SI SO C = C2 = 2 n Built-In Self Test 24 2
BILBO MISR Operation Mode C 2 n BILBO Flip C2 SI SO C = C2 = 2 n Built-In Self Test 25 XOR Cloud Chip The STUMPS Architecture Self Test Using MISR and a Parallel Shift Register Sequence Generator L F S R Linear Phase Shifter Primary Outputs tput Boundary Scan Out... m s... Input Boundary Sca an Primary Inputs Linear Phase Compactor XOR Tree M I S R Built-In Self Test 26 3
Linear Phase Shifter LFSR S S S2 () () (2) Flip Flip Flip CK CK CK Flip CK (3) Linear Phase Shifter To s Built-In Self Test 27 Linear Phase Compactor From s Linear Phase Compactor MISR Flip Flip Flip CK CK CK Flip CK Built-In Self Test 28 4
LFSR Reseeding Chip r bits L F S R Linear Phase Shifter r bit seed r bit seed k seeds r bit seed s s s M I S R s Fault coverage % Tester % k th seed 3 rd seed 2 nd seed st seed # test vectors Built-In Self Test 29 Chip LFSR and Bit Fixing Embedding eterministic Patterns L F S R OR AN Bit Bit Fixing i sca an chain sca an chain m s sca an chain Fix to signals Fix to signals M I S R Built-In Self Test 3 5
Chip LFSR and Bit Flipping Embedding eterministic Patterns L F S R XOR Bit Flipping i sca an chain sca an chain m s sca an chain Bit flipping when the value is M I S R Built-In Self Test 3 esign for iagnosis As iagnosis we define those operations that are performed in order to locate defects in an integrated circuit. This information is used to improve themanufacturingprocess or thequality of the design and consequently to increase the yield. esign for testability techniques may increase the difficulty to diagnose faults. A main problem comes from the output compaction schemes. Hardware assisted, software assisted (the inject and evaluate paradigm) and signal profiling fl based techniques are exploited dfor fault diagnosis. In all diagnosis techniques, special diagnosis vectors (or the existing test vectors) are used for defect location. Built-In Self Test 32 6
Compressed Pattern iagnosis Chip LFSR & Linear Phase Shifter Mask Pattern AN ecoder Response Compaction & MISR Y. Huang et al, ITC, 25 Built-In Self Test 33 References Principles of Testing Electronics Systems, S. Mourad and Y. Zorian, John Wiley &Sons, 2. Essentials of Electronic Testing: for igital, Memory and Mixed Signal VLSI Circuits, M. Bushnell and V. Agrawal, Kluwer Academic Publishers, 2. igital Systems Testing and Testable esign, M. Abramovici, M. Breuer and A. Friedman, Computer Science Press,99. Bit Fixing in Pseudorandom Sequences for Scan BIST, N. Touba and J. McCluskey, IEEE Tran. on CA of Integrated Circuits and Systems, vol. 2, no.4, pp. 546 555, 2. System on Chip Test Architectures, L T Wang, C. Stroud and N. Touba, Morgan Kaufmann, 28. Built-In Self Test 34 7