ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2
Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs, or A combinational circuit with memory elements is called a sequential circuit. Combinational loutputs t Sequential Circuits Combinational Circuit Memory Elements Inputs 2
A synchronous sequential circuit employs signals that affect the storage only at discrete instants of time. Inputs Combinational i Circuit Flip-flops Outputs Clock pulses 3
Digital Logic with Feedback if we alter gate circuits so as to give signal feedback from the output to one of the inputs, strange things begin to happen!!. Let s take an OR gate as an example. X Z Z When X is, the output could be either or, depending on the circuit's prior state. The proper way to complete the above truth table would be to insert the word latch in place of the question mark, showing that the output maintains its last state when X is. X Z LATCH 4
Any digital circuit employing feedback is also called a multi-vibrator. The previous example (OR gate) is a bistable multi-vibrator which has two stable status. There are circuits which do not have any stable status which h is called abstable. bl For example, consider the following example (an inverter with the output fed directly back to the input): Y Y The result is a high frequency (several megahertz) oscillator, if implemented with a solid-state (semiconductor) inverter gate. If implemented with relay logic, the resulting oscillator will be considerably slower, cycling at a frequency well within the audio range. The buzzer or vibrator circuit i thus formed was used extensively in early radio circuitry, as a way to convert steady, low-voltage DC power into pulsating DC power which could then be stepped up in voltage through a transformer to produce the high voltage necessary for operating the vacuum tube amplifiers. 5
Memory Element Memory elements like other logic circuits can be realized with basic gates. The most important memory element is the flip-flop. To understand the structure of a flip-flop we start with designing Latches. Before that, we need to understated the meaning of propagation delay Propagation Delay In any logic gate or circuit, there is a delay between the time you change the inputs and the time you see the effects of the inputs on the outputs. This delay is called the propagation delay. X NOT Y X Y=X Y Propagation Delay (e.g., -8 Sec.) 6
S R Latch with NAND Gates It operates with both inputs normally at unless the state of the latch has to be changed. S R S R Set State Store Reset Store Disallowed After S= & R= After S= & R= Instable Stable 7
S R Latch with Control Input S CLK R CLK S R Next State of X X No change; Store state No change, Store state =; Reset state =, set state Disallowed 8
D Latch Having a disallowed state in SR latch can be resolved using D latch. D CLK CLK D Next State of X No change; Store state =; Reset State =; Set state 9
Flip-Flops (Edge-triggered latches) The latch responds to the data inputs (S-R or D) only when the input is enabled. In many digital applications, however, it is required to limit the responsiveness of a latch circuit to an input activated in a very short period of time. One method of enabling a latch circuit is called edge triggering, where the circuit's data inputs have control only during the time that the enable input is transitioning from one state to another. Response to positive level Response to positive-edge (rising edge) Response to negative-edge (falling edge)
D Flip-Flops In order to generate a very narrow clock pulse consider the following circuit X X Z X X XX Z Output before delay Real output t after delay
Now, we can integrate the previous circuit into a D latch circuit. The integrated circuit is called D Flip-Flop. D CLK CLK D Next state of D CLK X No change (store) = ; Reset State =; Set State 2
J-K Flip-Flops J S CLK K R J K CLK Toggle x x J K Clk 3
No change if j=k= Output toggles at each rising edge if j=k= J K CLK Transition to J value if j=k Output t toggle because j=k= Switch will be high, but it is already high, so no transition 4
Sequential Logic Design Method You need to answer these questions: Is the problem a sequential system? If yes, what does need to be stored? Determine the number of flip-flops. Find the state table Derive the flip-flop inputs and outputs from state stable Simplify logic equations Combinational Outputs Next States (FF s Inputs) Sequential Circuits Combinational Circuit Flip-Flops Flops CLK Present States (FF s Outputs) Inputs 5
Purpose: Design a Divide-by-2 counter Example Present State = Next state = D D CLK CLK.D D CLK The frequency of output is half of the input clock frequency. 6
Example Purpose: Design a Divide-by-8 id counter. In fact, we would like to count the number of pulses, however, we use three bits display to present the counter. The main use of this counter is in SHIFT REGISTERS. A register capable of shifting its binary information in one or both directions is called a shift register. The logical configuration of a shift register consists of a chain of flip-flops, with the output of one flip-flop connected to the inputs of the other flip-flop. All flip-flops receive common clock pulses, which activate ate the shift from one stage to the next. Present States Next States 2 2.D.D.D.D.D 2.D D CLK D CLK D CLK 2 7
CLK 2 Having truth table, the Boolean expressions can be obtained. 2 2 2 2. D 2 2 2 8
2 2 2. D 2 2 2 D. 9
D.D D CLK Pulse Generator.D D CLK 2.D D CLK 2 2
Example Purpose: Design a Divide-by-4 id counter using J-K KFlip-Flops J A Clk A K A J B Clk B K B Clk J A B K A B J B K B J A K A Clk J B Clk K B A B Clk +5v 2
Example Purpose: Design a Modulo-5 5Counter. It can count tfrom to 4 repeatedly..d Present state Next State 2 2.D.D D.D CLK.D D CLK X X X X X X X X X 2.D D CLK 2 Using K-map, the following equations are derived. 22
2 2 2 x x x D 2. 2 2 2 x x 2 x. D 2 2 2 x x x. D 2 23