EE 3401 Lecture 11 Sequential ircuits Overview of Sequential ircuits Storage Elements Sequential circuits Storage elements: Latches & Flip-flops Registers and counters ircuit and System Timing Sequential circuit description and analysis: State tables & State diagrams 1
Sequential ircuits A Sequential circuit contains: Storage elements: Latches or Flip-Flops ombinational Logic: implements a multiple-output switching function Next state function: Next State = f(inputs, State) Output function: two types Mealy : Outputs = g(inputs, State) Moore: Outputs = h(state) Inputs State ombinational Logic Storage Elements Outputs Next State Latches R (reset) S (set) S (set) Basic S-R latch R (reset) Basic S-R latch S R locked S-R latch latch 2
Edge-Triggered Flip-Flop The edge-triggered flip-flop is the masterslave flip-flop S R The change of is associated with the negative edge at the end of the pulse - negative-edge triggered flip-flop Triggered Flip-flop Behavior Example Use the characteristic tables to find the output waveforms for the flip-flops shown: lock Triggered? 3
Modeling of Flip-Flops Library IEEE; use IEEE.Std_Logic_1164.all; Flip-flop controlled by a clock pulse edge. entity FLOP is port (, LK : in std_logic; : out std_logic); end FLOP; architecture A of FLOP is process wait until LK event and LK= 0 ; <= ; end process; end A; Or: process (clk) if (clk= 0 ) then <= ; end if; end process; irect Inputs At power up or at reset, sequential circuit usually is initialized to a known state before it s operation one outside of the clocked behavior of the circuit, i.e., asynchronously. irect R/S inputs S For the example flip-flop shown 0 applied to R resets the flip-flop to the 0 state 0 applied to S sets the flip-flop to the 1 state R 4
Positive Edge-Triggered Flip-flop with Asynchronous Set/Reset library IEEE; use IEEE.std_logic_1164.all; entity ASYN_FF is port (, LK, SETN, RSTN : in std_logic; : out std_logic); end ASYN_FF; architecture RTL of ASYN_FF is process (LK, RSTN, SETN) if (RSTN = `1`) then <= `0`; elsif SETN ='1' then <= '1'; elsif (LK event and LK = 1 ) then <= ; end if; end process; end RTL; It has a sensitivity list If / elsif structure The last elsif has an edge No unconditional else branch Registers Register: the simplest storage component in a computer, a bit-wise extension of a flip-flop. Registers can be classified into Simple Registers Parallel-Load Registers Shift Registers 5
Simple Registers Fig.1 A 4-bit Register: top schematic, bottom graphical symbol. I 3 I 2 I 1 I 0 3 3 2 2 1 1 0 0 clk 3 2 1 0 lk I 3 I 2 I 1 I 0 3 2 1 0 A simple register consists of N flip-flops driven by a common clock signal. Has N inputs and N outputs in addition to the clock signal. Fig.2 A 4-bit register with asynchronous preset and clear Preset clk clear I 3 I 2 I 1 I 0 3 2 1 0 Preset I 3 I 2 I 1 I 0 3 3 2 2 1 1 0 0 clk lear 3 2 1 0 6
Library ieee; USE ieee.std_logic_1164.all; ENTITY simple_register IS GENERI ( N : INTEGER := 4); PORT ( I : IN ST_LOGI_VETOR (N-1 OWNTO 0); lock, lear, Preset : IN ST_LOGI; : OUT ST_LOGI_VETOR (N-1 OWNTO 0)); EN simple_register; ARHITETURE simple_memory OF simple_register IS BEGIN PROESS (Preset, lear, lock) BEGIN IF Preset = 0' THEN <= (OTHERS => 1');; ELSIF lear = '0' THEN <= (OTHERS => '0'); ELSIF (lock'event AN lock = '1') THEN <= I; EN IF; EN PROESS; EN simple_memory; Parallel Load Registers In the previous registers, new data is stored automatically on every rising edge of the clock. In most digital systems, the data is stored for several clock cycles before it is rewritten. For this reason it is useful to be able to control WHEN the data will be entered into a register. Use a control signal called Load or Enable.This allows loading into a register known as a parallelload register. 7
VHL ode for Parallel-load Register Library ieee; USE ieee.std_logic_1164.all; ENTITY load_enable IS GENERI ( N : INTEGER := 4); PORT ( : IN ST_LOGI_VETOR (N-1 OWNTO 0); lock, Resetn, load : IN ST_LOGI; : BUFFER ST_LOGI_VETOR(N-1 OWNTO 0)); EN load_enable; ARHITETURE rtl OF load_enable IS SIGNAL state : std_logic_vector(n-1 OWNTO 0); BEGIN PROESS (Resetn, lock) IS BEGIN IF Resetn = '0' THEN state <= (OTHERS => '0'); ELSIF (lock'event AN lock = '1') THEN IF load = '1' THEN state <= ; ELSE state <= state; EN IF; EN IF; EN PROESS; <= state; EN rtl; Timing diagram for parallel-load register 8
Serial-in/Parallel-out Shift Register Parallel Load Shift Register 9
ounters ounter: a special type of register that incorporates an incrementer or decrementer, which allows it to count upward or downward. We shall examine VHL code for the following counters: Up counter own counter VHL for Up-ounter Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY upcount IS GENERI ( N : INTEGER := 4 ); PORT ( lock, Resetn, Enable : IN ST_LOGI; : BUFFER ST_LOGI_VETOR (N-1 OWNTO 0)); EN upcount; ARHITETURE cnt OF upcount IS SIGNAL count : ST_LOGI_VETOR (N-1 OWNTO 0); BEGIN PROESS (Resetn, lock) BEGIN IF Resetn = '0' THEN count <= ( OTHERS => 0 ); ELSIF (lock'event AN lock = '1') THEN IF Enable = '1' THEN count <= count +1; ELSE count <= count; EN IF; EN IF; EN PROESS; <= count; EN cnt; 10
Timing iagram for Up-ounter Synchronous ounters Internal Logic Incrementer: +0 or +1 ontraction of a ripple carry adder with one operant fixed at 000X Symbol for Synchronous ounter TR 4 Incrementer 1 2 EN 0 1 3 2 3 O Symbol 11
Synchronous ounters (ontd.) ontraction of carry-lookahead adder Reduce path delays alled parallel gating Lookahead can be used on Os and ENs to prevent long paths in large counters EN 0 1 1 2 2 3 3 O Logic iagram-parallel Gating ounter with Parallel Load Load ount Action Load 0 0 Hold Stored Value 0 1 ount Up Stored Value 1 X Load ount 0 0 Add path for input data enabled for Load = 1 Load TR4 1 1 Add logic to: When Load = 1 disable count logic (feedback from outputs) When Load = 0 and ount = 1 enable count logic ount 0 1 2 3 0 1 2 3 O 2 2 3 3 lock arry Output O 12
B ounter architecture Behavioral of bcd_counter is signal regcnt : std_logic_vector(3 downto 0); count: process(reset,clk) is if ( reset='1' ) then regcnt <= "0000"; elsif ( clk'event and clk='1') then regcnt <= regcnt+1; if (regcnt = "1001") then regcnt <= "0000"; end if; end if; end process; end Behavioral; 13