36 OMPUTER HARWARE Registers, Register Transfers and ounters r. Fethullah Karabiber
Overview 2 Registers, Microoperations and Implementations Registers and load enable Register transfer operations Microoperations - arithmetic, logic, and shift Microoperations on a single register n Multiplexer-based transfers n Shift registers Register ells, Buses, & Serial Operations ontrol of Register Transfers ounters
Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state table More often, think of a register as storing a vector of binary values Frequently used to perform simple data storage and data movement and processing operations
Example: 2-bit Register How many states are there? How many input combinations? Output combinations? What is the output function? What is the next state function? Moore or Mealy? State Table: urrent State In In P A Q A Q Next State A(t+ ) A(t+ ) For In In = Output (=A A) A A What are the quantities above for an n-bit register? Y Y Y Y
Simple Register 5 Serial input SI Serial output SO lock (a) Logic diagram lock SRG 4 Sl SO (b) Symbol
Register esign Models ue to the large numbers of states and input combinations as n becomes large, the state diagram/ state table model is not feasible! What are methods we can use to design registers? Add predefined combinational circuits to registers n Example: To count up, connect the register flip-flops to an incrementer esign individual cells using the state diagram/state table model and combine them into a register n A -bit cell has just two states n Output is usually the state variable
Register Storage Expectations: A register can store information for multiple clock cycles To store or load information should be controlled by a signal Reality: A flip-flop register loads information on every clock cycle Realizing expectations: Use a signal to block the clock to the register, Use a signal to control feedback of the output of the register back to its inputs, or Use other SR or JK flip-flops, that for (,) applied, store their state Load is a frequent name for the signal that controls register storage and loading Load = : Load the values on the data inputs Load = : Store the values in the register
Registers with lock Gating The Load signal enables the clock signal to pass through if and prevents the clock signal from passing through if. Example: For Positive Edge-Triggered or Negative Pulse Master-Slave Flip-flop: lock Load Gated lock to FF What logic is needed for gating? Gated lock = lock + Load What is the problem? lock Skew of gated clocks with respect to clock or each other
Registers with lock Gating 9 Q REG lock lear lear R Q Q Q 2 Q 2 3 Q 3 R (b) Symbol 2 Q 2 Load lock (c) Load control input inputs (clock inputs of flip-flops) R 3 Q 3 lock R (a) Logic diagram Load inputs FUNAMENTALS, 4e (d) Timing diagram
Registers with Load-ontrolled Feedback A more reliable way to selectively load a register: Run the clock continuously, and Selectively use a load control to change the register contents. Example: 2-bit register with Load ontrol: For Load =, loads register contents (hold current values) For Load =, loads input values (load new values) Load In Hardware more complex than clock gating, but free of timing problems In lock 2-to- Multiplexers A Q Q A Y Y
Registers with Load-ontrolled Feedback EN Q EN Flip-flop with enable Q EN Q (a) 2 EN Q 2 EN 3 Load lock EN Q 3 (b) (c) 4e
Registers 2 Function Table Shift Load Serial input Shift Load Operation Q X No change Load parallel data Shift down from Q to Q 3 Q SHR 4 Shift Load Sl 2 3 Q Q Q 2 Q 3 (b) Symbol 2 3 Q 2 Q 3 lock
Registers 3 Function Table Mode control S S Register Operation Q i No change Shift down Shift up Parallel load S S MUX S S lock Mode S Mode S Left serial input S S LSI SHR 4 Q i 2 3 Q i Q 2 Q 2 Q i Right serial input 3 Q 3 RSI (b) Symbol lock (a) Logic diagram of one typical stage
Register Transfer Operations Register Transfer Operations The movement and processing of data stored in registers Three basic components: set of registers operations control of operations Elementary Operations -- load, count, shift, add, bitwise "OR", etc. Elementary operations called microoperations
Register Transfer Operations 5 The system is partitioned into 2 types of modules: atapath: performs data processing operations. ontrol unit: determines the sequence of those operations. atapaths are defined by their registers and the operations performed on binary data stored in the registers ontrol signals ontrol inputs ontrol unit Status signals atapath ata outputs ontrol outputs ata inputs
Register Notation R 7 6 5 4 3 2 (a) Register R 5 (b) Individual bits of 8-bit register 5 8 7 R2 P (H) P (L) (c) Numbering of 6-bit register (d) Two-part 6-bit register Basic Symbols for Register Transfers Symbol escription Examples Letters enotes a register AR, R2, R, IR (and numerals) Parentheses enotes a part of a register R2(), R2(7:), AR(L) Arrow enotes transfer of data R R2 omma Separates simultaneous transfers R R2, R2 R Square brackets Specifies an address for memory R M[ AR]
onditional Transfer If (K =) then (R2 R) is shortened to K: (R2 R) where K is a control variable specifying a conditional execution of the microoperation. K lock R n Load R2 Transfer occurs here t t lock K
Microoperations Logical Groupings: Transfer - move data from one register to another Arithmetic - perform arithmetic on data in registers Logic - manipulate data or use bitwise logical operations Shift - shift data in registers Arithmetic operations + Addition Subtraction * Multiplication / ivision Logical operations Logical OR Logical AN Logical Exclusive OR Not
Register Trasfers 9 TABLE 7-2 Textbook RTL, VHL, and Verilog Symbols for Register Transfers Operation Text RTL VHL Verilog ombinational assignment = <= (concurrent) assign = (nonblocking) Register transfer <= (concurrent) <= (nonblocking) Addition + + + Subtraction Bitwise AN ^ and & Bitwise OR or Bitwise XOR xor ^ Bitwise NOT (overline) not ~ Shift left (logical) sl sll << Shift right (logical) sr srl >> Vectors/registers A(3:) A(3 down to ) A[3:] oncatenation & {, }
Example Microoperations Add the content of R to the content of R2 and place the result in R. R R + R2 Multiply the content of R by the content of R6 and place the result in P. P R * R6 Exclusive OR the content of R with the content of R2 and place the result in R. R R R2
Example Microoperations (ontinued) Take the 's omplement of the contents of R2 and place it in the P. P R2 On condition K OR K2, the content of R is Logic bitwise Ored with the content of R3 and the result placed in R. (K + K2): R R R3 NOTE: "+" (as in K + K 2 ) and means OR. In R R + R3, + means plus.
ontrol Expressions The control expression for an operation appears to the left of the operation and is separated from it by a colon ontrol expressions specify the logical condition for the operation to occur ontrol expression values of: Logic "" -- the operation occurs. Logic "" -- the operation is does not occur. Example: X K : R R + R2 X K : R R + R2 + Variable K enables the add or subtract operation. If X =, then X = so X K =, activating the addition of R and R2. If X =, then X K =, activating the addition of R and the two's complement of R2 (subtract).
Arithmetic Microoperations Arithmetic Microoperations Symbolic designation escription R R + R2 R2 R2 R2 R2 + R R + R2 + R R + R R ontents of R plus R2 transferred to R omplement of the contents of R2 ( s complement) 2 s complement of the contents of R2 R plus 2 s complement of R2 transferred to R (subtraction) Increment the contents of R (count up) ecrement the contents of R (count down) Note that any register may be specified for source, source 2, or destination. These simple microoperations operate on the whole word
Adder/ Subtracter Unit 24 X K : Rß R+R2 XK : Rß R+R2 + Overflow output
Logical Microoperations Logic Microoperations Symbolic designation R R R R R2 R R R2 R R R2 escription Logical bitwise NOT ( s complement) Logical bitwise AN (clears bits) Logical bitwise OR (sets bits) Logical bitwise XOR (complements bits) Let R =, and R2 = Then after the operation, R becomes: R Operation R! R R! R " R2 R! R # R2 R! R $ R2
Shift Microoperations Examples of Shifts Eight-bit examples Type Symbolic designation Source R2 After shift: estination R shift left R sl R2 shift right R sr R2 Note: These shifts "zero fill". Sometimes a separate flipflop is used to provide the data shifted in, or to catch the data shifted out. Other shifts are possible (rotates, arithmetic).
Register ell esign Assume that a register consists of identical cells Then register design can be approached as follows: esign representative cell for the register onnect copies of the cell together to form the register Applying appropriate boundary conditions to cells that need to be different and contract if appropriate Register cell design is the first step of the above process
Register ell Specifications A register ata inputs to the register ontrol input combinations to the register Example : Not encoded n ontrol inputs: Load, Shift, Add n At most, one of Load, Shift, Add is for any clock cycle (,,), (,,), (,,), (,,) Example 2: Encoded n ontrol inputs: S, S n All possible binary combinations on S, S (,), (,), (,), (,)
Register ell Specifications A set of register functions (typically specified as register transfers) Example: Load: A B Shift: A sr B Add: A A + B A hold state specification Example: n ontrol inputs: Load, Shift, Add n If all control inputs are, hold the current register state
Example : Register ell esign Register A (m-bits) Specification: ata input: B ontrol inputs (X, Y) ontrol input combinations (,), (,) (,) Register transfers: X : A B v A Y : A B + A Hold state: (,)
Example : Register ell esign (continued) Load ontrol Load = X + Y Since all control combinations appear as if encoded (,), (,), (,) can use multiplexer without encoder: S = X S = Y = A i Hold A = A i B i + A i Y = 2 = A i B i v A i X = Note that the decoder part of the 3-input multiplexer can be shared between bits if desired
Sequential ircuit esign Approach Find a state diagram or state table Note that there are only two states with the state assignment equal to the register cell output value Use the design procedure in hapter 5 to complete the cell design For optimization: Use K-maps for up to 4 to 6 variables Otherwise, use computer-aided or manual optimization
Example Again State Table: Four variables give a total of 6 state table entries By using: Hold Ai v Bi Ai + Bi A i X = Y = X = B i = X = B i = n ombinations of variable names and values n on t care conditions (for X = Y = ) Y = B i = Y = B i = only 8 entries are required to represent the 6 entries
Example Again (continued) K-map - Use variable ordering X, Y, A i B i and assume a flip-flop i Ai X X X Bi X X Y
Example Again (continued) The resulting SOP equation: i = X B i + Y A i B i + A i B i + Y A i Using factoring and emorgan s law: i = X B i + A i (Y B i ) + A i (Y B i ) i = X B i + A i + (Y B i ) The gate input cost per cell = 2 + 8 + 2 + 2 = 4 The gate input cost per cell for the previous version is: Per cell: 9 Shared decoder logic: 8 ost gain by sequential design > 5 per cell Also, no Enable on the flip-flop makes it cost less
Register Transfer Structures Multiplexer-Based Transfers - Multiple inputs are selected by a multiplexer dedicated to the register Bus-Based Transfers - Multiple inputs are selected by a shared multiplexer driving a bus that feeds inputs to multiple registers Three-State Bus - Multiple inputs are selected by 3-state drivers with outputs connected to a bus that feeds multiple registers Other Transfer Structures - Use multiple multiplexers, multiple buses, and combinations of all the above
Multiplexer-Based Transfers Multiplexers connected to register inputs produce flexible transfer structures (Note: locks are omitted for clarity) The transfers are: K: R R K2 K: R R2 K2 R2 4 K S MUX 4 Load R R 4 (a) Block diagram
Multiplexer Approach Uses an n-input multiplexer with a variety of transfer sources and functions K K n.... edicated logic 4 Encoder.... edicated logic k Registers or shared logic 4 4 4...... S m S k k... n... MUX 4 Load R
Multiplexer Approach Load enable by OR of control signals K, K, K n- - assumes no load for Use Encoder + Multiplexer (shown) or n x 2 AN-OR to select sources and/or transfer functions K K n.... edicated logic 4 Encoder.... edicated logic k Registers or shared logic 4 4 4...... S m S k k... n... MUX 4 Load R
Multiplexer and Bus-Based Transfers for Multiple Registers Multiplexer dedicated to each register Shared transfer paths for registers A shared transfer object is a called a bus (Plural: buses) Bus implementation using: multiplexers three-state nodes and drivers In most cases, the number of bits is the length of the receiving register
edicated MUX-Based Transfers Multiplexer connected to each register input produces a very flexible transfer structure => haracterize the simultaneous transfers possible with this structure. S 2-to- MUX n S 2-to- MUX n Select S S S2 n n R R Load LL L2 S 2-to- MUX n n R2 (a) edicated multiplexers
Multiplexer Bus A single bus driven by a multiplexer lowers cost, but limits the available transfers => haracterize the simultaneous transfers possible with this structure. haracterize the cost savings compared to dedicated multiplexers Select Load n Select S S 3-to- MUX 2 n n n n Bus R R Load LL L2 Register Transfer S S L2 L L n R R2 R R, R2 R R R, R R Impossible n R2 (b) Single bus
Three-State Bus The 3-input MUX can be replaced by a 3-state node (bus) and 3-state buffers. ost is further reduced, but transfers are limited haracterize the simultaneous transfers possible with this structure. haracterize the cost savings and compare Load LOA R EN Load n R EN n n n Load L2 L L Enable E2 E E R R R2 EN EN n n n Bus n n (a) Register with bidirectional input output lines and symbol EN (c) Three-state bus using registers with bidirectional lines
Serial Transfers and Microoperations Serial Transfers Used for narrow transfer paths Example : Telephone or cable line n Parallel-to-Serial conversion at source n Serial-to-Parallel conversion at destination Example 2: Initialization and apture of the contents of many flip-flops for test purposes n Add shift function to all flip-flops and form large shift register n Use shifting for simultaneous Initialization and apture operations Serial microoperations Example : Addition Example 2: Error-orrection for s
Serial Transfer 45 Shift lock Register A SRG 4 Register B SRG 4 SI SO SI SO (a) Block diagram lock Shift inputs T T 2 T 3 T 4 (b) Timing diagram Example of Serial Transfer Timing pulse Shift Register A Shift Register B Initial value After T After T 2 After T 3 After T 4
Serial Microoperations By using two shift registers for operands, a full adder, and a flip flop (for the carry), we can add two numbers serially, starting at the least significant bit. Serial addition is a low cost way to add large numbers of operands, since a tree of full adder cells can be made to any depth, and each new level doubles the number of operands. Other operations can be performed serially as well, such as parity generation/checking or more complex error-check codes. Shifting a binary number left is equivalent to multiplying by 2. Shifting a binary number right is equivalent to dividing by 2.
Serial Adder The circuit shown uses two shift registers for operands A(3:) and B(3:). A full adder, and one more flip flop (for the carry) is used to compute the sum. The result is stored in the A register and the final carry in the flip-flop Serial In Serial In Load/Right Shift Registers A3 A2 A A Parallel Load B3 B2 B B Parallel Load A B FA Sum in out Q (lock and Load/Shift ontrol not shown) With the operands and the result in shift registers, a tree of full adders can be used to add a large number of operands. Used as a common digital signal processing technique. P
48 Serial Adder
ounters ounters are sequential circuits which "count" through a specific state sequence. They can count up, count down, or count through other fixed sequences. Two distinct types are in common usage: Ripple ounters lock connected to the flip-flop clock input on the LSB bit flip-flop For all other bits, a flip-flop output is connected to the clock input, thus circuit is not truly synchronous! Output change is delayed more for each bit toward the MSB. Resurgent because of low power consumption Synchronous ounters lock is directly connected to the flip-flop clock inputs Logic is used to implement the desired state sequencing
Ripple ounter ha pt er 7 - Pa rt 2 5 How does it work? When there is a positive edge on the clock input of A, A complements The clock input for flipflop B is the complemented output of flip-flop A When flip A changes from to, there is a positive edge on the clock input of B causing B to complement P A B lock Reset R R 2 3 A B
Ripple ounter (continued) The arrows show the cause-effect relationship from the prior slide => The corresponding P sequence of states => (B,A) = (,), (,), (,), (,), (,), (,), A B 2 3 Each additional bit,,, behaves like bit B, changing half as frequently as the bit before it. For 3 bits: (,B,A) = (,,), (,,), (,,), (,,), (,,), (,,), (,,), (,,), (,,),
Ripple ounter (continued) These circuits are called ripple counters because each edge sensitive transition (positive in the example) causes a change in the next flip-flop s state. The changes ripple upward through the chain of flip-flops, i. e., each transition occurs after a clock-to-output delay from the stage before. To see this effect in detail look at the waveforms on the next slide. lock pulse Reset R R R R
Ripple ounter (continued) Starting with = B = A =, equivalent to (,B,A) = 7 base, the next clock increments the count to (,B,A) = base. In fine timing detail: The clock to output delay t PHL causes an increasing delay from clock edge for each stage transition. Thus, the count ripples from least to most significant bit. For n bits, total worst case delay is n t PHL. P A B t PHL t PHL t phl
Synchronous ounters ha pt er 7 - Pa rt 2 54 To eliminate the "ripple" effects, use a common clock for each flip-flop and a combinational circuit to generate the next state. For an up-counter, use an incrementer => TABLE 7-8 ounting Sequence of Binary ounter Upward ounting Sequence ownward ounting Sequence Q 3 Q 2 Q Q Q 3 Q 2 Q Q lock A3 A2 A A Incrementer S3 S2 S S 3 Q3 2 Q2 Q Q
Synchronous ounters (continued) Internal details => Internal Logic XOR complements each bit AN chain causes complement of a bit if all bits toward LSB from it equal ount Enable Forces all outputs of AN chain to to hold the state arry Out Added as part of incrementer onnect to ount Enable of additional 4-bit counters to form larger counters ount enable EN lock (a) Logic diagram-serial gating Q Q Q 2 Q 3 arry output O
Synchronous ounters (continued) Q arry chain series of AN gates through which the carry ripples Yields long path delays alled serial gating Replace AN carry chain with ANs => in parallel Reduces path delays alled parallel gating Like carry lookahead Lookahead can be used on Os and ENs to prevent long paths in large counters Symbol for Synchronous ounter TR 4 EN Q Q Q 2 Q 3 O (c) Symbol EN Q Q 2 2 Q 3 3 O (b) Logic diagram-parallel gating
Other ounters See text for: own ounter - counts downward instead of upward Up-own ounter - counts up or down depending on value a control input such as Up/own Parallel Load ounter - Has parallel load of values available depending on control input such as Load ivide-by-n (Modulo n) ounter ount is remainder of division by n; n may not be a power of 2 or ount is arbitrary sequence of n states specifically designed state-by-state Includes modulo which is the B counter
ounter with Parallel Load Add path for input data Load enabled for Load = ount Q Add logic to: disable count logic for Load = disable feedback from outputs for Load = Q enable count logic for Load = and ount = The resulting function table: 2 Q 2 Load ount Action Hold Stored Value ount Up Stored Value 3 Q 3 X Load nc. lock arry Output O
ounter w/ Unused States 59 n flip-flops 2n binary states Unused states: states that are not used in specifying the sequential ckt maybetreatedasdon t-careconditionsor may be assigned specific next states Selfcorrecting counter: Ensure that when a ckt enter one of its unused states, it eventually goes into one of the valid states after one or more clock pulses so it can resume normal operation. n Analyze the ckt to determine the next state from an unused state after it is designed.
ounter w/ Unused States 6 Example: The simplified f-f input eqs: A A B B B Two unused states: &
ounter w/ Unused States 6 A Reset AB B lock Reset (a)
esign Example: Synchronous B Use the sequential logic model to design a synchronous B counter with flip-flops Input combinations through are don t cares Present State Next State Output Q 8 Q 4 Q 2 Q 8 = Q 8 (t+) 4 = Q 4 (t+) 2 = Q 2 (t+) = Q (t+) Y TABLE 7-9 State T able and Flip-Flop Inputs for B ounter
Synchronous B (continued) Use K-Maps to two-level optimize the next state equations and manipulate into forms containing XOR gates: = Q 2 = Q2 + QQ8 4 = Q4 + QQ2 8 = Q8 + (QQ8 + QQ2Q4) The logic diagram can be draw from these equations An asynchronous or synchronous reset should be added What happens if the counter is perturbed by a power disturbance or other interference and it enters a state other than through?
Synchronous B (continued) ha pt er 7 - Pa rt 2 64 Find the actual values of the six next states for the don t care combinations from the equations Find the overall state diagram to assess behavior for the don t care states (states in decimal) Present State Next State 9 4 Q8 Q4 Q2 Q Q8 Q4 Q2 Q 8 7 6 5 3 5 4 2 2 3
Synchronous B (continued) For the B counter design, if an invalid state is entered, return to a valid state occurs within two clock cycles Is this adequate? If not: Is a signal needed that indicates that an invalid state has been entered? What is the equation for such a signal? oes the design need to be modified to return from an invalid state to a valid state in one clock cycle? oes the design need to be modified to return from a invalid state to a specific state (such as )? The action to be taken depends on: the application of the circuit design group policy See pages 244 of the text.
66 Three ecade ecimal ounter
ounting Modulo N The following techniques use an n-bit binary counter with asynchronous or synchronous clear and/or parallel load: etect a terminal count of N in a Modulo-N count sequence to asynchronously lear the count to or asynchronously Load in value (These lead to counts which are present for only a very short time and can fail to work for some timing conditions!) etect a terminal count of N - in a Modulo-N count sequence to lear the count synchronously to etect a terminal count of N - in a Modulo-N count sequence to synchronously Load in value etect a terminal count and use Load to preset a count of the terminal count value minus (N - ) Alternatively, custom design a modulo N counter as done for B
A B ounter 68 Generate any count sequence: E.g.: design a B counter by using a counter w/ parallel load & async clear lock TR 4 Load ount Q Q Q Q 2 Q 2 Q 2 (Logic ) 3 Q 3 O Q 3
ounting Modulo 6: Synchronously Preset 9 on Reset and Load 9 on Terminal ount 4 A synchronous, 4-bit binary counter with a synchronous Load is to be used to make a Modulo 6 counter. Use the Load feature to preset the count to 9 on Reset and detection of count 4. lock Reset 3 Q3 2 Q2 Q Q P LOA LEAR This gives a count of 9,,, 2, 3, 4, 9,,, 2, 3, 4, 9, If the terminal count is 5 detection is usually built in as arry Out (O)
ounting Modulo 7: etect 7 and Asynchronously lear ha pt er 7 - Pa rt 2 7 A synchronous 4-bit binary counter with an asynchronous lear is used to make a Modulo 7 counter. Use the lear feature to detect the count 7 and clear the count to. This gives a count of,, 2, 3, 4, 5, 6, 7(short),, 2, 3, 4, 5, 6, 7(short), etc. lock 3 Q3 2 Q2 Q Q P LOA LEAR ON T O THIS! Existence of state 7 may not be long enough to reliably reset all flip-flops to. Referred to as a suicide counter! (ount 7 is killed, but the designer s job may be dead as well!)
ounting Modulo 7: Synchronously Load on Terminal ount of 6 A synchronous 4-bit binary counter with a synchronous load and an asynchronous clear is used to make a Modulo 7 counter Use the Load feature to detect the count "6" and load in "zero". This gives a count of,, 2, 3, 4, 5, 6,,, 2, 3, 4, 5, 6,,... Using don t cares for states above, detection of 6 can be done with Load = Q4 Q2 lock Reset 3 Q3 2 Q2 Q Q P LOA LEAR
4-bit Shift Register with Reset 72 library ieee; use ieee.std_logic_64.all; entity srg_4_r is port(lk, RESET, SI : in std_logic; Q : out std_logic_vector(3 downto ); SO : out std_logic); end srg_4_r;
4-bit Shift Register with Reset 73 architecture behavioral of srg_4_r is signal shift : std_logic_vector (3 downto ); begin process (RESET, LK) begin if (RESET = '') then shift <= " ; elsif (LK'event and (LK = '')) then shift <= shift(2 downto ) & SI; end if; end process; Q <= shift; SO <= shift(3); end behavioral;
4-bit Binary ounter with Reset 74 library ieee; use ieee.std_logic_64.all; use ieee.std_logic_unsigned.all; entity count_4_r is port(lk, RESET, EN : in std_logic; Q : out std_logic_vector(3 downto ); O : out std_logic); end count_4_r;
4-bit Binary ounter with Reset 75 architecture behavioral of count_4_r is signal count : std_logic_vector(3 downto ); begin process (RESET, LK) begin if (RESET = '') then count <= " ; elsif (LK'event and (LK = '') and (EN = '')) then count <= count + " ; end if; end process; O <= '' when count = "" and EN = '' else ' ; Q <= count; end behavioral;