Defect Reduction for Semiconductor Memory Applications Using Jet And Flash Imprint Lithography Zhengmao Ye, Kang Luo, Xiaoming Lu, Brian Fletcher, Weijun Liu, Frank Xu, Dwayne LaBrake, Douglas Resnick, Matt Shafran, Saul Lee, Whitney Longsine, Van Truskett, S. V. Sreenivasan February 26 th, 2013 Mark Melliar-Smith Chief Executive Officer mark@molecularimrints.com
Overview J-FIL memory strategy and roadmap Mask status Wafer defect data Defect mechanisms Short-run vs. long-run defect trends Approach to achieve >20 lot runs at low defectivity Conclusions Excellent overall progress towards manufacturing Mask plans and resist processes in place for 1x nm 2
J-FIL Memory Manufacturing Focusing on CMOS memory due to defect tolerance Multiple tools installed for system refinement and process integration Industry infrastructure: J-FIL Stepper installations Customer s Facility Equipment partner experienced in building and shipping J-FIL TM steppers High quality DNP commercial imprints replica masks available today Large semiconductor manufacturer has plans to ramp J-FIL TM into advanced memory production by 2015. 3
Semiconductor Platform Roadmap Wafer 2011 2012 2013 2014 2015 2016 Gen 2 Cluster (6 modules) Stepper Production CoO and <8nm O/L IM30 C Production Ramp 1x nm 10 nm Gen 2 (1 module) Stepper Production CoO and <8nm O/L IM30 Pilot Production 1x nm 10 nm Equip. Partner s Gen 1 Yield Targets and <10nm O/L Imprio 450 300mm and 450mm Capable IM20 Process Integration 24 nm 10 nm Development Line 2X nm 10 nm Mask Replication Mask Commercial Supply DNP Mask Shop Perfecta MR5000 2X nm 1X nm Legend ship module Molecular Imprints Module Equipment Partner Stepper Molecular Imprints Platform 4
Semiconductor J-FIL TM Collaboration Collaborative Relationships Memory IC Manufacturer Imprint Masks Imprint Resist Imprint Stepper Mask Shop Partner Resist Partner Equipment Partner Mask Replicator Material Formulation Imprint Modules Apps and Materials Molecular Imprints 5
J-FIL s Manufacturing Readiness ATTRIBUTE Feb 2011 Sep 2012 Current Status Mfg Target TEMPLATE Master CDU 1.2nm 1.2nm 1.2nm ~ 1nm Image Placement 4nm 2.5nm 2.5nm < 3nm Master Defectivity 10 def/cm 2 0 to 1 def/cm 2 0 def/cm2 < 0.1 def/cm 2 Replica Defectivity to be determined 5 def/cm 2 3 def/cm2 <1 def/cm 2 IMPRINT LER 2nm 2nm 2nm <2nm Overlay Accuracy 10nm 10nm 10nm < 8nm CDU on Wafer to be determined 0.5nm 0.5nm < 1 nm Throughput 5-7 wph 10 wph 10 wph 20wph Defects (short run, ~2 wafers) 10 def/cm 2 ~2 def/cm 2 ~2 def/cm2 <0.1 def/cm 2 Defects (long run, > 1 lot) to be determined <50 def/cm 2 <10 def/cm2 <1 def/cm 2 Data Source SPIE. SEMATECH Litho Forum MII Confidential 6
Overview J-FIL memory strategy and roadmap Mask status Wafer defect data Defect mechanisms Short-run vs. long-run defect trends Approach to achieve >20 lot runs at low defectivity Conclusions Excellent overall progress towards manufacturing Mask plans and resist processes in place for 1x nm 7
Mask Replication Master Masks Fabrication by e-beam Inspected by e-beam and repaired Replica Masks using J-FIL Enable low cost mask copies that can be used for all lines in memory fab Leads to low overall cost of ownership One replica is expected to be used to imprint ~500 wafers (20 lots) Master Mask Replicas created by imprint Wafers printed on J-FIL steppers 8
Mask Infrastructure Readiness Status 2012 Master/Replica @ 2x nm Target 2012 Units Master defectivity 0 0 with repair defects/cm 2 Replica added image placement < 2 <2 nm, 3σ Replica defect density <1 3 defects/cm 2 Relica CDU 2 1.5 nm, 3σ Defect repair of masters Yes In use Resist etch resistance* 30% over 2011 Baseline 15% improvement * Improved etch resistance is needed relative to Cr, and the etch process window is related to replica defects. DNP is primarily shipping replica masks 9
1xnm Mask Technology E-Beam Double Patterning 15nm master/replica mask feasibility 10
Overview J-FIL memory strategy and roadmap Mask status Wafer defect data Defect mechanisms Short-run vs. long-run defect trends Approach to achieve >20 lot runs at low defectivity Conclusions Excellent overall progress towards manufacturing Mask plans and resist processes in place for 1x nm 11
J-FIL Electrical Yield: Excellent Progress Electrical Defect Testing: Yield vs. Line Length 100% 80% Yield 60% 40% J-FIL 20% 0% 26nm HP 1 10 100 1000 10000 Line Length (mm) DNP presented yesterday that yields >90% have been achieved for 10 meter lines More progress expected with improvements in contamination control as discussed next, and with reduced mask replica defects. 12
Defect Mechanisms for 2xnm Features Separation step can cause pattern shear failure. Particularly challenging for sub- 25nm features at high throughput Solved using improved precision machine design, real-time algorithms for controlled separation and enhanced resists A. Surface contamination control is required to prevent fluid filling issues during the resist filling process B. Sub-30nm particles lead to plug defects, causing line breaks in the resist A. and B. are key areas of ongoing development 13
A. Surface Contamination on Wafers Soft contaminants are airborne organic contaminants that adsorb onto wafers causing local fluid flow disruption induced defects. These contaminants can cause high defects They do not cause repeaters, mask surface treatment promotes self-cleaning Imprint Specific Defects #/cm 2 100 90 80 70 60 50 40 30 20 10 0 DD increate rate: 0.0028 pcs/cm2 per imprint 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 Imprint Number Solution: Requires in-tool control of airborne contaminants 14
B. Sub-30 Particles Cause Line Breaks Single Line Break Observed in 2xnm Half-Pitch Lines Establish Root-Cause by Introducing Sub-30nm Polystyrene Particles Particles cause line break defects Can cause high defects, and lead to repeaters Mask cleaning (wet or dry) can recover most defects particles are predominantly soft organic particles Solution: Requires in-line resist filtration; and in-situ mask cleaning 15
In-Line Sub-10nm Filtration Sub-10nm inline multi-pass filtration installed in resist dispense system Has led to > two orders of magnitude reduction in defects at the 2x nm. Two new generations of resist filtration improvements are planned, should lead to much lower defectivity Ink Jet Vent Waste bottle Recirculation system & Reservoir Resist circulation Pump 10 nm filter 10 nm Filter New recirculation filtration system Hydra Vent Resist Re- Fill bottle 16
Mask Cleaning Addresses Line Plug Defects Defects Caused by Sub-30 Particles Defect Density 102% 100% 98% 96% 94% 92% 90% 2xnm features 0 1 2 Reclaim # Preliminary results indicate >90% mask defect removal rate with cleaning Implies mask plug defects are caused predominantly by soft polymeric contaminants Now incorporating in-situ VUV cleaning systems on the stepper to extend mask life 17
Short Run Defectivity: Total Defect Density Initial defectivity is from replica defects which will be <1/cm2 in 2013 Fluctuations in defect density are from surface contaminations Defect increase rate is from particles causing mask plugs Total defectivity at 2xnm CD is ~10 defect/cm 2 Defect increase rate: 8x10-4 /cm 2 per imprint (2 adders/cm 2 per lot) Defect increase rate key to mask life of >500 wafers (20 lots) To stay below 1 defect/cm 2, requires 0.05 adders/cm 2 per lot MII Confidential 18
Long Run Defectivity: Over 12 Wafers Initial defectivity is from replica defects which will be <1/cm2 in 2013 Fluctuations in defect density are from surface contaminations Defect increase rate is from particles causing mask plugs Device-like mask: 78% of each 26x33mm field consist of 2x nm fine features Defect level is ~13 defect/cm 2 with an increase rate of 5 adders/cm 2 per lot MII Confidential 19
Long Run Defectivity: Adders Over 1 Wafer Lot Trend of imprint defect adder per lot (25 wafers) Imprint Added Defect Density per Lot [#/cm2] 1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 426,563 3,281 1,680 3,380 437 DRIVERS: Resist filtration Separation development (HW/SW/Control/process) Resist improvement Imprint POR development 276 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 132 37 2011 2012 Q4 2012 4.7 Current (Q4 2012): Defect increase rate: 4.7 adders/cm 2 per lot (25 wafers) 2013 goal: 1 adder/cm 2 per 10 lots (250 wafers) 2014 goal: 1 adder/cm 2 per 20 lots (500 wafers) Timeline (month) MII Confidential 20
Approach to Achieve >20 lot Mask Life Mask life limitations dominated by soft particles in resist. Defect adder/cm 2 per lot Status, end of 2012 <5 Comments Manufacturing target <0.05 20 lot mask replica life 2013 goal 0.1 >10x improvement each from resist 2014 goal <0.05 filtration and inline mask cleaning Integrated in-stepper VUV mask cleaning is being implemented, based on >90% clean efficiency data expect to achieve an additional >10x improvement in mask life Established final steps towards mask life target for production 21
Overview J-FIL memory strategy and roadmap Mask status Wafer defect data Defect mechanisms Short-run vs. long-run defect trends Approach to achieve >10 lot runs at low defectivity Conclusions Excellent overall progress towards manufacturing Mask plans and resist processes in place for 1x nm 22
Conclusions Focusing on CMOS memory due to defect tolerance J-FIL has key advantages Sub-10nm direct replication Attractive cost structure due to low cost tool and mask replication Excellent progress in all aspects of patterning for manufacturing Plans in place for memory production ramp in 2015 1x nm direct patterning being investigated for mask, nominal resist process exists Post etch BPM pattern on disk Baseline resist and etch process exists at 12nm half-pitch due to progress in HDD BPM 23
Acknowledgements TEXAS-ETF 24