Through Silicon Via Testing Known Good Die (KGD) or Probably Good Die (PGD) Doug Lefever Advantest

Through Silicon Via Testing Known Good Die (KGD) or Probably Good Die (PGD) Doug Lefever Advantest

Single Die Fab Yield will drive Cost Equation. Yield of the device to be stacked 100% 90% 80% Yield of single-chip 99% The final yield 70% 60% 50% 40% 30% 20% 10% 70% 60% 50% 95% 90% 80% So of course we need to test the die before stacking. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Number of chips to be stacked

Must also consider both Backside Process & Test related Yield If Assume Backside Process Yield Loss = 1% (flip chip 1% after 20 years) If Assume Test Escapes = 1% (let s discuss today). 100% Yield of single-chip 90% 100% The final yield 80% 70% 60% 50% 98% 99% 98% 97% 96% 95% 94% 93% Then 5 die stack could have 10% final yield loss 40% 30% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SoC Number of chips to be stacked Memory

Conventional Test Flow Wafer Process Wafer Test Back Grinder Dicing Packaging Final Test Wafer Test Challenges High Pin = Added Test Yield Concerns

High Pin 30um or less Probe 25um or less Source: SWTW Proceedings 2006 Limitation: ermeasures: Issues: - Current Advanced Probe Cards have Pin & Limits due to MEMS & MLC/Organics - Use Dedicated Test Pads, Speed Scan DFT, Correlation based test - Use Non-contact probing - Test Pads take real estate & design time. - Cannot test I/O characteristics, test pad leakage concerns. - Non-contact probing requires transmitters and receivers, and power delivery must still be made by physical contact. Adds Test Yield Concerns

High Pin Probe < 50um Limitation: ermeasures: Issues: - Advanced Probe Cards have contact forces ~2g per contact - Die may require <1g - Probe before backside processes (BG, CMP, Etch) or - Use Non-contact probing - Backside processes may induce defects that may go untested. Adds Test Yield Concerns

High Pin V2 Io=1mA Tr=1nS Z0 = 50 Ohm 30cm To test system 1 0-1 0 5 10 15 20 25 30 35 40 45 Limitation: ermeasures: Issues: - Lack of Buffers in device creates drivability problem through fixture to ATE. - Active probe cards with buffer amp circuitry. - Probe cards require high density circuitry, unproven architecture. Adds Test Yield Concerns

High Pin Source: Protection of Through Silicon Via Signals Utilizing Temporary Backside Metallization, IBM Limitation: ermeasures: Issues: - s create paths to internal nodes of IC not previously exposed. - Circuit loading may be issue with structures. - Limit in machine model - Weak, small size flip-flop circuits on IC - Other: Current trigger and Source Pumping, - Test access point with many switches to s takes lots of space, adds capacitance and requires power. Adds Test Yield Concerns

High Pin 3D clock tree for optimized length and power Source: Test Strategies for 3D Die-Stacked Integrated Circuits Lewis & Lee, Georgia Institute of Technology Limitation: ermeasures: Issues: - If logic is partitioned on different layers, single die may not be fully testable. - DFT, Scan Chains - Comment: IDMs may go this route, but fabless design model may not support repartitioning due to design and software complexities. - Not much choice.

High Pin Example: If 1 Die = 1000 If PPM = 10 Die Yield = 99% Source: Optimized Filling Process Reduces Cost, Nexx Systems Limitation: ermeasures: Issues: - If wafer test before backside processing, cannot be contacted. - If backside processing before wafer test, no probing or material handling solutions exist for top & bottom side contact. - Use carrier like Film Frame to handle thinned, processed wafers - Use non-contact (x-ray, infrared, thermagrophy, EM, etc) to inspect structures. - s need to be reliably tested. PPM can have big effect. Adds Test Yield Concerns

Summary High Pin There are possible solutions to allow continued use of conventional wafer test architecture. They mostly require: Silicon Solutions (Test Access Ports & DFT) New Probe Card Solutions These may come at a Test Yield penalty. Probably Good Die could become Maybe Good Die and unacceptable yield loss at stack.

Conclusion A Non-Conventional Test Methodology that enables KGD is needed. - Wafer vs. Singulated Die test - Zero Force Contacting - Carrier technologies - Combined Non-Electrical test - Top Bottom & Side contacting KGD will be essential to making Stacking cost effective. The final yield 100% 90% 80% 70% 60% 50% 40% 30% Yield of single-chip 100% 99% 98% 97% 96% 95% 94% 93% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Number of chips to be stacked SoC Memory

Thank You Domo Arigato