Simple Combination Lock Circuit Project. Johnathan Sam

Similar documents
SEQUENTIAL CIRCUITS THE RELAY CIRCUIT

(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Lecture 8: Sequential Logic

Light Emitting Diodes and Digital Circuits I

10.1 Sequential logic circuits are a type of logic circuit where the output of the circuit depends not only on

16 Stage Bi-Directional LED Sequencer

Rensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory

Light Emitting Diodes and Digital Circuits I

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:

CS Part 1 1 Dr. Rajesh Subramanyan, 2005

Light Emitting Diodes and Digital Circuits I

Digital Circuits 4: Sequential Circuits

Assignment 2b. ASSIGNMENT 2b. due at the start of class, Wednesday Sept 25.

The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both).

A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states.

Chapter 4: One-Shots, Counters, and Clocks

Computer Systems Architecture

Chapter 5 Sequential Circuits

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

Engr354: Digital Logic Circuits

Introduction to Microprocessor & Digital Logic

Decade Counters Mod-5 counter: Decade Counter:

CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division

To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit.

Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers

Logic. Andrew Mark Allen March 4, 2012

(Refer Slide Time: 1:45)

CPS311 Lecture: Sequential Circuits

EXPERIMENT #6 DIGITAL BASICS

LATCHES & FLIP-FLOP. Chapter 7

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

Chapter 4. Logic Design

DIGITAL ELECTRONICS MCQs

VU Mobile Powered by S NO Group

Module 4:FLIP-FLOP. Quote of the day. Never think you are nothing, never think you are everything, but think you are something and achieve anything.

CPSC 121: Models of Computation Lab #5: Flip-Flops and Frequency Division

DIGITAL ELECTRONICS: LOGIC AND CLOCKS

RS flip-flop using NOR gate

Synchronous Sequential Logic

More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98

Asynchronous (Ripple) Counters

11.1 As mentioned in Experiment 10, sequential logic circuits are a type of logic circuit where the output

Laboratory 10. Required Components: Objectives. Introduction. Digital Circuits - Logic and Latching (modified from lab text by Alciatore)

Notes on Digital Circuits

Physics 323. Experiment # 10 - Digital Circuits

EKT 121/4 ELEKTRONIK DIGIT 1

EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043

Notes on Digital Circuits

EE 367 Lab Part 1: Sequential Logic

cascading flip-flops for proper operation clock skew Hardware description languages and sequential logic

Copyright 2011 by Enoch Hwang, Ph.D. and Global Specialties. All rights reserved. Printed in Taiwan.

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Digital Circuits I and II Nov. 17, 1999

PRE J. Figure 25.1a J-K flip-flop with Asynchronous Preset and Clear inputs

COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

Sequential Logic and Clocked Circuits

INC 253 Digital and electronics laboratory I

Sequential Circuits: Latches & Flip-Flops

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science SOLUTIONS

Rangkaian Sekuensial. Flip-flop

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M

A Review of logic design

Topic D-type Flip-flops. Draw a timing diagram to illustrate the significance of edge

SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur

The NOR latch is similar to the NAND latch

Chapter. Synchronous Sequential Circuits

B. Sc. III Semester (Electronics) - ( ) Digital Electronics-II) BE-301 MODEL ANSWER (AS-2791)

Sequential Logic Basics

1 Hour Sample Test Papers: Sample Test Paper 1. Roll No.

How to Design a Sequential Counter

ECB DIGITAL ELECTRONICS PROJECT BASED LEARNING PROJECT REPORT ON 7 SEGMENT DIGITAL STOP WATCH USING DECODER

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000

Combinational vs Sequential

Catch or Die! Julia A. and Andrew C. ECE 150 Cooper Union Spring 2010

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

Experimental Study to Show the Effect of Bouncing On Digital Systems

Introduction. Serial In - Serial Out Shift Registers (SISO)

EE292: Fundamentals of ECE

Topics. Microelectronics Revolution. Digital Circuits Part 1 Logic Gates. Introductory Medical Device Prototyping

Universidad Carlos III de Madrid Digital Electronics Exercises

Testing Digital Systems II

Design and Simulation of a Digital CMOS Synchronous 4-bit Up-Counter with Set and Reset

Week 4: Sequential Circuits

FLIP-FLOPS AND RELATED DEVICES

VTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers

WINTER 14 EXAMINATION

We are here. Assembly Language. Processors Arithmetic Logic Units. Finite State Machines. Circuits Gates. Transistors

Chapter 2. Digital Circuits

Software Engineering 2DA4. Slides 9: Asynchronous Sequential Circuits

Timing Pulses. Important element of laboratory electronics. Pulses can control logical sequences with precise timing.

WINTER 15 EXAMINATION Model Answer

EECS150 - Digital Design Lecture 19 - Finite State Machines Revisited

Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.

0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format

Digital 1 Final Project Sequential Digital System - Slot Machine

Digital Circuits Part 1 Logic Gates

LAB #4 SEQUENTIAL LOGIC CIRCUIT

Spring 2011 Microprocessors B Course Project (30% of your course Grade)

CS302 - Digital Logic Design FAQs By

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits

Transcription:

Simple Combination Lock Circuit Project Johnathan Sam Engr 210 5/16/2013

Bill Of Materials Resistors R1-5 Resistor 47 KOhm 1/4 Watt 5% Carbon Film R6 Resistor 4.7 KOhm 1/4 Watt 5% Carbon Film Transistors 2N2907 General purpose amplifier and switching Q1 transistor (pnp) ICs IC1 IC2 IC3 IC4 CD 4013 Dual D-Type Flip-Flop CD 4013 Dual D-Type Flip-Flop CD 4081 Quad 2-input AND buffered B series Gate CD 4072 Dual 4-input OR Gate Misc RELAY Relay DSDP miniature 5V relay LED Green x4/ Light Bulb Switches Pushbutton x9 Circuit Description: There are more simple but less secure circuits. This circuit has a 4-digit security code that is hardware selectable. It can have as many 'wrong' digits as you like, but up to 4 'correct' digits. Also, one digit cannot be more than once in the security code. Suppose for example that you choose to have 10 digit keypad with numbers from 0 to 9. One code could be the number 5293, or the 7520, but the code 4429 is wrong! The digit '4' is more than once in the code and that cannot happen. Each 'correct' key press will SET a flip-flop. When the 4th flip-flop is SET, the relay will be armed through the PNP transistor. Whenever a 'wrong' button is pressed, all 4 flip-flops will be RESET and the code must be entered again from the beginning. Also, the code must be entered in the correct order. If for example the code is 1234 and instead you press 1 and then 3, the flipflops will also RESET. The keypad can have as many keys as you like. From the circuit you have 5 inputs, the D1, D2, D3, D4 and the ERR. The 4 D inputs are the 'correct' buttons. Each one must go to one and only key! For example, someone could connect the D1 to key number 4, the D2 to key number 2, the D3 to key number 9 and D4 to key number 5. The code to open the lock would be '4295'.

All the other buttons that will reset the circuit must be connected to the 'ERR' input. So if the keypad had 10 keys and the code was '4295' the keys 1,3,4,6,7,8 and 0 must be connected to the ERR input. The circuit is designed to operate at any voltage between 5 and 15 volts. Logic: For this circuit there exist two states, no input (Stable State) and input entry (Set or Reset Flip Flops). During Stable state each flip flop is outputting a high value (Q = 1) which is an input for a single AND gate in the CD4081, but since the S pin (SET) on each flip flop is low due to ground each AND gate outputs low values. No high value is inputted into the gathering OR gate, therefore the RESET in all the flip flops is low (not Resetting). Also, since the last flip flop output is high, it is inverted by the pnp transistor to a low value not setting the relay. During a SET state the flip flops S pin goes high, making the output low (Q = 0). Unless a wrong input is entered and the reset goes high, the flip flops will stay in this state and is now SET. If the flip flops are entered out of order, the circuit resets. (The flip flops output low only when SET so if not SET the inputs into the corresponding AND gate are both high making the output high, making the OR gate output high which RESETs all the flip flops.) If a wrong entry is made the signal is sent straight to the OR gate, RESETing all the flip flops. Also, when the final flip flop is SET (Q = 0), the signal is inverted by the pnp transistor to a high value setting the relay.

Analysis: In order to analyze this circuit I grouped up all the gates into one network (one big supernode) and treated it as a single component. There is internal circuitry within the IC s which makes it hard to analyze with simple methods such as Nodal and Mesh. Therefore I incorporated switches that signify the different states of the circuit. Once that is done I was able to simplify my circuit, thus becoming a simple pnp transistor circuit.

Conclusion: Sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the past history of its inputs. Asynchronous implies that the circuit doesn t rely on clock signals (The D flip flops in this project were implemented as S-R flip flops). For my project a functional asynchronous sequential logic circuit was implemented successfully and analysis and test results seem to agree. The code lock design can be used in various real world applications, pretty much anywhere security is a priority. This simple code lock circuit can be usefully employed in cars so that the car can start only when the correct code sequence is entered in via the key pad. Though, the designs can be improved upon in order to safeguard against hackers and criminals. A difficulty I experienced was limited knowledge regarding logic design. No prior prep was taken before the construction of the circuit however, after walking through each scenario at each gate and flip flop, breaking down the circuit logically was fairly simple. Another difficulty was the analysis of the circuit. Simplifying the circuit to a small transistor switch helped but doesn t replace an actual analysis that includes the IC components.