SMPTE 259M EG-1 Color Bar Generation, RP 178 Pathological Generation, Grey Pattern Generation IP Core AN4087 Associated Project: No Associated Part Family: HOTLink II Video PHYs Associated Application Notes: None Application Note Abstract This application note explains about SMPTE 259M Color Bar Generation, RP 178 Pathological Generation, Grey Pattern Generation IP Core. Introduction The Society of Motion Picture and Television Engineers (SMPTE) specifies several test patterns to verify the integrity of a video system. There are three test patterns which comply with SMPTE 259M Standard Definition (SD) standards documented in this application note. The color bar test pattern conforms to the standards of SMPTE s Engineering Guideline 1 (EG-1). The purpose of the color bars is to have a standard to adjust chroma gain, chroma phase, and black level monitor controls. The Recommended Practice 178 (RP 178) test pattern is named as the pat.lhological test pattern. RP 178 test patterns are meant to stress parts in the system such as the equalizer and Phase Lock Loop (PLL). The final test pattern discussed in this document is the grey pattern. The grey pattern is a pattern specified by Cypress Semiconductor to test the video systems. All of the above test patterns comply with SMPTE 259M standards. Table 1 lists the different supported SD video types, and their properties. Once the video type is determined through the SEL input, the correct properties are chosen for the test pattern generators. The properties are used for the horizontal timing reference. Horizontal timing reference exists each line. Each line contains information regarding Start of Active Video (SAV) timing reference, Horizontal line blanking, End of Active Video timing reference (EAV), and the active data. Figure 1 displays the horizontal line data. Figure 1. Horizontal Line Data EAV EDH SAV Active Video Data Functional Blocks There are three HDL modules for SD test pattern generation. The EG-1 Color bars are generated by eg1.vhd; the RP 178 Pathologicals are generated by rp178.vhd; and the grey pattern is generated by grey.vhd. Although each test pattern is generated by a separate module, the initial test pattern set up is common to all the SD test patterns. Horizontal Blanking Interval ASL ASL + 3 TSL-4 0 ASL Active Sample Per Line TSL Total Sample Per Line ASL - 1 SMPTE 259M Pattern Generation Setup The HDL SMPTE 259M test pattern generators support multiple video formats. Therefore, it is first necessary to determine the video type used in an SD system before pattern generations can begin. The first packet of information generated is the EAV. The EAV consists of four words. The first three words are ancillary header data and are set at 3FF h, 000, and 000. The only word which varies is the last word, XYZ. The XYZ word is generated differently in SMPTE 259C, SMPTE 259D, and SMPTE 344M video types. The 10-bit XYZ word for SMPTE 259C, and SMPTE 259D video types contains information as seen in Table 2. Table 3 contains the values for S, and P2-P4 based on bits 6 through 8. January 27, 2011 Document No. 001-14934 Rev. *B 1
Table 1. SMPTE 259M Video Type Properties Video Type Total Number of Lines TSL ASL Vertical Blanking Interval Lines in Field 1 SMPTE 259C NTSC 270 Mb/S 525 1716 1440 19 263 SMPTE 259D NTSC 270 Mb/s 525 2288 1920 19 263 SMPTE 259C PAL 360 Mb/s 625 1728 1440 22 313 SMPTE 259D PAL 360 Mb/s 625 2304 1920 22 313 SMPTE 344M NTSC 4:4:4:4 540 Mb/s 525 3432 2880 19 263 SMPTE 344M PAL 4:4:4:4 540 Mb/s 625 3456 2880 22 313 Table 2. XYZ Word Bit Word 1923 and 2199 Description 9 1 Fixed 8 F F = 0 during field 1 F = 1 during field 2 7 V V=0 during active video V=1 during vertical blanking 6 H H=1 for EAV H=0 for SAV 5 S S=0 for GBR signals S=1 for Y, C b, C r signals 4 P4 Dependent on bits 8-6 3 P3 Dependent on bits 8-6 2 P2 Dependent on bits 8-6 1 P1 0 0 P0 0 Table 3. Bits 5 to 2 for the XYZ Word Bit 8 Bit 7 Bit 6 S P4 P3 P2 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 OTHER 0 0 0 1 January 27, 2011 Document No. 001-14934 Rev. *B 2
The XYZ word is generated differently for the SMPTE 344M NTSC and PAL 4:4:4:4 video types. Bits 6 to 9 of the XYZ word are generated in the same manner as in Table 2. Bit 5, the S bit, however, is always set to 1. Bits 0 to 4 are generated based on Bits 5 to 8, and the results are displayed in Table 4. After the EAV packet is generated, the horizontal blanking interval is generated. The horizontal blanking interval has values of 0x40 and 0x200 for odd and even words respectively. The horizontal timing interval also contains the Error Detection and Handling (EDH) packet for error detection. For more information on EDH, please refer to, SMPTE 295M Error Detection and Handling (EDH) Generation and Detection IP Core application note. The final packet generated prior to the active video data is the SAV packet. The SAV information occupies the last 4 words in a video line. Once again, there are three ancillary header words, 3FF h, 000, and 000. The final word is once again the XYZ word. Also generated with the test patterns are the wordcount and linecount. A counter keeps count of the current words and lines being processed and during each rising edge of the clock signal, the linecount and wordcount are updated.after generating the EAV, horizontal blanking interval, and SAV data, the active video data is generated. Table 4. Bits 0 to 4 for SMPTE 344M NTSC and PAL XYZ Word Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 0 Others 1 1 1 1 0 SMPTE 259M Color Bar Generation The active video data generation is the information which distinguishes ones test pattern from another. Figure 2 shows the color bar pattern in terms of the amount of active line time that each color bar requires. The first row of color bars requires 67% of the active line time, the second row requires 8% of the active line time, and the final row requires 25% of the active line time. The active video data generated according to the R,G,B, and Y, C B, C R as displayed in Table 5. The Y, C B, and C R numbers in Table 5 are generated according to the following formulas: The formulas which generate the values based on the normalized RGB values are as follows: Normalized formulas: Y = 0.299R + 0.587G + 0.114B P B = 0.168736R 0.331264G + 0.5B P R = 0.5R 0.418688G 0.081312B Scaling for 10-bit data: Y = 261.924R + 514.212G + 99.864B + 64 C B = 448R 375.144448G 72.855552B + 512 C R = 151.187456R 296.812544G + 448B + 512 In SMPTE 344M NTSC and PAL 4:4:4:4 video types there is one more parameter. SMPTE 344M NTSC and PAL video types also require the generation of an alpha keying (K) signal. The alpha key value is data required to mix two video signals and control the blending of the images. The K value for this test pattern generator is a constant of 64. Figure 3 shows how the Y, C B, C R,and K words are inserted in each line of active video data. January 27, 2011 Document No. 001-14934 Rev. *B 3
Figure 2. Color Bar Test Signal b b b b b b b GRAY YELLOW CYAN GREEN MAGENTA RED BLUE 67% 100% BLUE BLACK MAGENTA BLACK CYAN BLACK GRAY 8% -I WHITE +Q BLACK BLK BLK BLK BLACK 5/4b 5/4b 5/4b 5/4b b 3 b 3 b 3 b = 1/7 Active Line Time Figure 3. SMPTE 344M NTSC 4:4:4:4 and PAL 4:4:4:4 Active Data Word Allocation C B0 Y 0 C R0 K 0 C B END Y END C REND K END 0 1 2 3 ASL-4 ASL-3 ASL-2 ASL-1 If the video type is not SMPTE 344M NTSC 4:4:4:4 or PAL 4:4:4:4, then the K value is replaced by a Y value. The color bars are generated in sections. The first section generated is the row of color bars which require 67% of the line time. The color bars in the first row are evenly spaced horizontally.therefore, each bar requires ASL/7 words in each line. For example, in the HDL module a test condition is placed on the current word, if the word is between 0 and ASL/7-1 then the grey bar data is placed into the output data. After the first row of bars are generated, the second row of bars is generated in a similar fashion. The difference for the second row is that it only requires 8% of the line time. The final row to be generated is not evenly spaced horizontally. This is easily accounted for by the different test conditions on the current word number. All of the test pattern data is only generated on the rising edge of the clock source. January 27, 2011 Document No. 001-14934 Rev. *B 4
Table 5. SMPTE 259M Active Video Data for Color Bar Generation Color Bar R G B Y C B C R 100% White 1 1 1 940 512 512 75% White 0.75 0.75 0.75 721 512 512 75% Yellow 0.75 0.75 0 646 176 567 75% Cyan 0 0.75 0.75 525 625 176 75% Green 0 0.75 0 450 289 231 75% Magenta 0.75 0 0.75 335 735 793 75% Red 0.75 0 0 260 399 848 75% Blue 0 0 0.75 139 848 457 black - 4% 0.04 0.04 0.04 29 512 512 black +4% 0.04 0.04 0.04 99 512 512 -I (legal RGB) 0.0000 0.2456 0.4125 231 624 390 +Q (legal RGB) 0.2536 0.0000 0.4703 177 684 591 RP 178 Pathologicals Test Pattern In digital communications systems, it is desirable to have an equal number of ones and zeros. Digital video systems employ scramblers to optimize systems for such a scenario. There are, however, three cases in which the scrambler does not optimize the video data and there is a poor ratio of ones to zeros. The special cases which cause poor ones to zeros ratios are called pathologicals. The equalizer test and the PLL test are two of the pathologicals. The third pathological occurs during the vertical blanking interval, and rarely occurs, therefore it is not included in the test pattern generator. Equalizer Test One of the pathologicals occurs when there is a continuous pattern of 19 HIGHs and 1 LOW or 1 LOW and 19 HIGHs. This pattern appears as a flat magenta-like color. The scrambler used in SMPTE 259M video systems does not optimize for this pattern, and the ratio of ones to zeros becomes 1 to 19 or 19 to 1. This results in a large amount of low-frequency energy, and stresses the equalizer. As a result, this pattern is referred to as the equalizer test. The 19 HIGHs and 1 LOW pattern is easily generated by transmitting continuous 198 h and 300 h data in the luminance and color difference output vectors respectively. If a designer wishes to transmit 19 LOWs and 1 HIGH, the std_altn input signal should be set to LOW. This will switch the data, and 300 h will be transmitted as the luminance data and 198 h will be transmitted as the color difference data. Also specified in RP 178 is that the last active sample directly after the vertical blanking interval must be set to 80 h to ensure that both polarities (either 19 HIGH or 19 LOW) are realized. For this HDL module, the equalizer test is generated in the first half of the active video picture. Figure 4 shows the data allocation in each frame for RP 198 HDL module. PLL Test The second pathological pattern included in the RP 178 HDL module is the PLL test. To generate the PLL test, a continuous pattern of 20 HIGHs and 20 LOWs, or vice versa, is generated. This pattern has a low transition density of ones and zeros. For better performance, the PLL requires high transition density. Therefore, this test is referred to as the PLL test and is displayed as grey in the video picture. The PLL test pattern is generated by continuously transmitting 110 h in the luminance output vector, and 300 h in the color difference output vector. If a designer wishes to transmit 20 LOWs and 20 HIGHs, then the data can be switched, and 300 h is transmitted as the luminance data and 110 h is transmitted as the color difference data. The PLL pathological is generated on the second half of the active video picture in the RP 178 HDL module. Grey Pattern Generation The grey pattern test generation is simply the continuous generation of 511 for the luminance data and 512 for the color difference data. The generated video picture will be a grey picture. January 27, 2011 Document No. 001-14934 Rev. *B 5
Figure 4. RP 178 Frame Data Allocation Vertical Blanking Interval 1st Half of Active Picture 300h, 198h (Equalizer Test) EAV SAV Horizontal Blanking Interval 2nd Half of Active Picture 200h, 110h (Phase Lock Loop Test) IP Core Features This IP Core includes HDL modules for SMPTE 259M EG-1 Color Bar, RP 178 Pathologicals, and Grey Pattern generation. This IP core allows designers to implement the test patterns and comply with SMPTE 259M SD standards. The deliverables for this IP Core include eg1.vhd, rp178.vhd, and grey.vhd. This IP Core assumes prior knowledge of the HOTLink II SERDES. Please visit www.cypress.com for more information. Complies with SMPTE 259M, EG-1, and RP 178 Supports SMPTE 259C NTSC 270Mb/s, SMPTE 259D NTSC 270 Mb/s, 259C PAL 360 Mb/s, SMPTE 259D PAL 360 Mb/s, SMPTE 344M NTSC 4:4:4:4 540 Mb/s, and SMPTE 344M PAL 4:4:4:4 540 Mb/s video Communicates with the HOTLink II SERDES Resource Usage EG-1 Color Bar Resource Usage The SMPTE 259M EG-1 color bar generator requires 404 logic cells out of a total of 20,060 logic cells in an Altera Cyclone FPGA, using the Quartus II compiler. This code will also work with Xilinx and other programmable logic devices. RP 178 Pathologicals Resource Usage The SMPTE 259M RP 178 pathologicals generator requires 191 logic cells out of a total of 20,060 logic cells in an Altera Cyclone FPGA, using the Quartus II compiler. This code will also work with Xilinx and other programmable logic devices. Grey Pattern Resource Usage The SMPTE 259M grey pattern generator requires 142 logic cells out of a total of 20,060 logic cells in an Altera Cyclone FPGA, using the Quartus II compiler. This code will also work with Xilinx and other programmable logic devices. January 27, 2011 Document No. 001-14934 Rev. *B 6
Block Diagrams Figure 5. SMPTE 259M Color Bar Pattern Generation Block Diagram CLK 10 DATA ENABLE SMPTE 259M Color Bar Pattern Generation 10 LINECOUNT_OUT SEL 3 12 WORDCOUNT_OUT Figure 6. SMPTE 259M Color Bar Pattern Generation Block Diagram CLK 10 DATA ENABLE 10 LINECOUNT_OUT SEL 3 RP 178 Pathologicals Generation 12 WORDCOUNT_OUT STD_ALTN Figure 7. SMPTE 259M Grey Pattern Generation Block Diagram CLK 10 DATA ENABLE SMPTE 259M Grey Pattern Generation 10 LINECOUNT_OUT SEL 3 12 WORDCOUNT_OUT January 27, 2011 Document No. 001-14934 Rev. *B 7
Signal Descriptions SMPTE 259M Color Bar Generation Signal Descriptions System Inputs Width Active Description SEL 3 N/A Indicates whether the video is NTSC 270 Mb/s, 360 Mb/s, 4:4:4:4 or PAL 270 Mb/s, 360 Mb/s, or 4:4:4:4. The data originates from video_detect.vhd. System Outputs Width Active Description LINECOUNT_OUT 10 N/A Indicates the current line being generated by the color bar test pattern. WORDCOUNT_OUT 12 N/A Indicates the current word being generated by the color bar test pattern. Signal Inputs Width Active Description CLK N/A N/A The clock signal for the FPGA provided by an external source. ENABLE 1 HIGH Enables the color pattern generation when HIGH. The color pattern generation is disabled when LOW. Signal Outputs Width Active Description DATA 10 N/A The output color bar test pattern transmitted to the HOTLink II family of SERDES devices. RP 178 Pathologicals Generation Signal Descriptions System Inputs Width Active Description SEL 3 N/A Indicates whether the video is NTSC 270 Mb/s, 360 Mb/s, 4:4:4:4 or PAL 270 Mb/s, 360 Mb/s, or 4:4:4:4. The data originates from video_detect.vhd. System Outputs Width Active Description LINECOUNT_OUT 10 N/A Indicates the current line being generated by the color bar test pattern. WORDCOUNT_OUT 12 N/A Indicates the current word being generated by the color bar test pattern. = Signal Inputs Width Active Description CLK N/A N/A The clock signal for the FPGA provided by an external source. ENABLE 1 HIGH Enables the color pattern generation when HIGH. The color pattern generation is disabled when LOW. STD_ALTN 1 HIGH Standard distribution is selected when HIGH. Alternate Distribution is selected when LOW. Signal Outputs Width Active Description DATA 10 N/A The output color bar test pattern transmitted to the HOTLink II family of SERDES devices. January 27, 2011 Document No. 001-14934 Rev. *B 8
Grey Pattern Generation Signal Descriptions System Inputs Width Active Description SEL 3 N/A Indicates whether the video is NTSC 270Mb/s, 360Mb/s, 4:4:4:4 or PAL 270Mb/s, 360Mb/s, or 4:4:4:4. The data originates from video_detect.vhd. System Outputs Width Active Description LINECOUNT_OUT 10 N/A Indicates the current line being generated by the color bar test pattern. WORDCOUNT_OUT 12 N/A Indicates the current word being generated by the color bar test pattern. Signal Inputs Width Active Description CLK N/A N/A The clock signal for the FPGA provided by an external source. ENABLE 1 HIGH Enables the color pattern generation when HIGH. The color pattern generation is disabled when LOW. Signal Outputs Width Active Description DATA 10 N/A The output color bar test pattern transmitted to the HOTLink II Family of SERDES devices. Summary The IP core complies with SMPTE 259M, EG-1, and RP 178 and communicates with HOTLinkII SERDES successfully. January 27, 2011 Document No. 001-14934 Rev. *B 9
Document History Page Document Title: SMPTE 259M EG-1 Color Bar Generation, RP 178 Pathological Generation, Grey Pattern Generation IP Core Document Number: 001-14934 Revision ECN Orig. of Change Submission Date Description of Change ** 999021 SFV 04/20/2007 Re-catalogued application note. *A 1785606 SAAC 11/29/2007 Template update. Google search requirement update. There were no technical updates to these notes. *B 3155555 FRE/ SAAC 01/27/2011 Template updates. Sunset review spec. In March of 2007, Cypress recataloged all of its Application Notes using a new documentation number and revision code. This new documentation number and revision code (001-xxxxx, beginning with rev. **), located in the footer of the document, will be used in all subsequent revisions. HOTLink II is a trademark of Cypress Semiconductor Corporation. All other product and company names mentioned in this document may be the trademarks of their respective holders. Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: 408-943-2600 Fax: 408-943-4730 http://www.cypress.com Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. January 27, 2011 Document No. 001-14934 Rev. *B 10