LAB #4 SEQUENTIAL LOGIC CIRCUIT OBJECTIVES 1. To learn how basic sequential logic circuit works 2. To test and investigate the operation of various latch and flip flop circuits INTRODUCTIONS Sequential circuit is a circuit with the output obtained is a function of the input state as well as the state's previous output, referred to as a series of sequential circuits with memory elements. We call this memory element Flip-Flop. Latch and Flip-Flop can store 1 bit binary information and have 2 output terminals. If one of output terminal is 1, the other outputs 0 and keeps opposite status of 2. Latch circuit does not use clock pulse so whenever the output is changed, the output status is changed. However Flip-Flop changes the output status only when other clock pulse is inputted. Latches are useful devices that contain feedback and thus enable memory. They are used in applications such as simple noise filtering circuits and flip-flops. The first latch have discussed in class was the SR/S R Latch which allowed us to Set or Reset the output. The drawback of such a latch was that it contained a transition that caused a metastable (indeterminate) state. A clock/enable signal was then added to prevent such a transition when the clock signal was low. Lastly, the Gated D-Latch eliminated this altogether by preventing S and R from changing at the same time. Hence, in our discussion the latches have become progressively more stable. REQUIREMENT 1. Full pack of HBE-LogicCircuit-Digital 2. Cooper Cable PRE-LAB WORK TASK 1. Read the Lab Work s Technical Guide first! 2. Learn the Data Sheet of each ICs of Logic Gates used in this lab work! 3. What is Clock? 4. Explain the differences between Latch with clock and without clock! 5. Explain how D Latch works with its circuit diagram! 6. What would happen if the two inputs of Latches and Flip-Flops are 1? 7. How could a sequential logic circuit store a memory? EXPERIMENT 1 : LATCHES [Trial 1] Simple SR Latch without Clock
I/O Device Slide Switch (SW1, SW2), LED (D1, D2) NAND Gate 1. Construct a simple SR Latch circuit as shown in Fig. IV-1 below. 2. Write the result on Table IV-1. Fig. IV-1. Simple SR Latch Operation Test Diagram Table IV-1. Result Table of Simple SR Latch Operation R (SW1) S (SW2) Q (D1) Q (D2) 0 0 0 1 1 0 1 1 EXPERIMENT 2 : FLIP-FLOPS [Trial 2] RS Flip-Flop I/O Device Slide Switch (SW1, SW2, SW4), LED (D1, D2) AND Gate, NOR Gate 1. Use all gate modules in order to make RS Flip-Flop circuit as Fig. IV-3 on the logic
Fig. IV-2. RS Flip-Flop Operation Test Diagram 2. Check and write the result on Table IV-2. Table IV-2. Result Table of RS Flip-Flop Operation R (SW1) S (SW2) Clock (SW4) Q (D1) Q (D2) 0 0-0 0 ^ 0 1-0 1 ^ 1 0-1 0 ^ 1 1-1 1 ^ [Trial 3] JK Flip-Flop I/O Device Slide Switch (SW1, SW2, SW4), LED (D3, D4) AND Gate, NOR Gate 1. Use all gate modules in order to make JK Flip-Flop circuit as Fig. IV-3 on the logic
Fig. IV-3. JK Flip-Flop Operation Test Diagram 2. Check and write the result on Table IV-3. Table IV-3. Result Table of JK Flip-Flop Operation K (SW1) J (SW2) Clock (SW4) Q (D1) Q (D2) 0 0-0 0 ^ 0 1-0 1 ^ 1 0-1 0 ^ 1 1-1 1 ^ [Trial 4] D Flip-Flop I/O Device Slide Switch (SW2, SW4), LED (D3, D4) AND Gate, NOR Gate, NOT Gate 1. Use all gate modules in order to make D Flip-Flop circuit as Fig. IV-4 on the logic
Fig. IV-4. D Flip-Flop Operation Test Diagram 2. Check and write the result on Table IV-4. Table IV-4. Result Table of D Flip-Flop Operation D (SW1) Clock (SW3) Q (D1) Q (D2) 0-0 ^ 1-1 ^ [Trial 5] T Flip-Flop I/O Device Slide Switch (SW2, SW4), LED (D3, D4) AND Gate, NOR Gate 1. Use all gate modules in order to make T Flip-Flop circuit as Fig. IV-5 on the logic Fig. IV-5. T Flip-Flop Operation Test Diagram
2. Check and write the result on Table IV-5. Table IV-5. Result Table of T Flip-Flop Operation S 1 (SW1) Clock (SW3) Q (D1) Q (D2) 0-0 ^ 1-1 ^ ASSIGNMENT 1. Simulate all of Trial in Circuit Maker! 2. What is the Edge-Triggered Flip-flop! 3. What is a Master-slave Flip-flop, explain the advantages the use of Master-Slave Flip-Flop! 4. Plan a series of Master-Slave SR Flip-flop and JK flip-flop! And explain how it works! Realize the circuit in the simulation file! 5. From the circuit that you created in question 3, give a conclusion uses a series of Master-slave Flip-Flop compared to the usual series of Flip-Flop!