the Boundary Scan perspective Rik Doorneweert, JTAG Technologies rik@jtag.com www.jtag.com
Subjects Economics of testing Test methods and strategy Boundary scan at: Component level Board level System level Emulative Testing and Programming Tools for HW engineers and Test engineers 2
The Test Challenge More than 90% of the PCBs produced will contain at least one structural fault Ref: Charles Robinson and Amit Verma, Teradyne Inc., APEX 2002 3
PCB Assembly errors Can you 1. detect them all? 2. locate them quickly? 4
Fundamentals of testing 1. Findthefailuresbeforeyourcustomersdo! 2. If it hasn t been tested then it doesn t work! 3. Assumption is the mother of all cock-ups!
If Simplified economics. Cost of tester equipment, adapters plus consumables, test development all amortised over 5 years, divided by the total number of tested PCBAs is less than Cost of wasted/discarded bone-pile plus reduced quality and cost of handling field returns and damage to business reputation etc.. then YOU BETTER TEST!
Why should I Test it, our EMS does it for us! Our supplier EMS only sends us 100% (are they?) working boards so we don t need to test.. BUT These boards will have been tested and you don t know - at what cost. Who is in control of these costs??
EMS Statements Garbage in = Garbage out During the production process we can only add errors to the PCBA s 8
OEM s better. Respect DFM rules Respect DFT rules Think upfront and decide on how boards will be tested (=Test Strategy) 9
Test Methods Functional test Structural: o AOI o X-Ray o MDA o Flying Probe o ICT o Boundary scan Which combination (=test strategy) of these is optimal for your project? 10
Functional testing as an approach Exercises the product the way it will be used functionally Very effective at assuring if quality standards are met Drawback 1: Test prepared manually, often requiring input from the design engineer Drawback 2: Faults found at functional test may be difficult to diagnose, often involving the designer Most factories have a bone-pile of boards that fail functional test, but are difficult to fix 11
Functional test PUSH
13 Functional testing failure localization Design Failures Manufacturing Failures: Analogue Nets Opens Bridges Stuck at 0 or 1 Wrong Analogue Components Missing Analogue Components Bad Orientation of Component (Complex) Digital Nets Opens Bridges Stuck at 0 or 1 Wrong Digital Components Missing Digital Components Bad Orientation of Component Wrong Programmed Device Defective Components Analogue Digital F-Test Long repair times High level repair engineers
Structural testing as an approach Intended to detect manufacturing faults Solder problems, incorrect parts, etc., so not the design faults Benefit 1: Can be generated automatically, by intelligent software tools, using an exhaustive list of the potential structural faults on the board Benefit 2: Detection and diagnosis of faults can be precise, if sufficient test points are available 14
Structural Test More detailed structural test => improved diagnostic resolution=> provides production process feedback & reduces bonepile
Traditional structural testing In-circuit testing will have difficulty finding these types of faults Potentially defective wire bond ESD damage Open under BGA Short to power or ground BGA BGA Power or GND Bridging fault Inner board layers, blind vias Boundary-scan can help! 16
Coverage with boundary-scan Test wire bond Detects ESD damage Finds open Finds short, s-a-0 or s-a-1 TAP BGA BGA Power or GND Finds solder bridge under BGA Provides access to blind vias, inner layers 17
18 Boundary-scan failure localization Design Failures Manufacturing Failures: Analogue Nets Opens Bridges Stuck at 0 or 1 Wrong Analogue Components Missing Analogue Components Bad Orientation of Component (Complex) Digital Nets Opens Bridges Stuck at 0 or 1 Wrong Digital Components Missing Digital Components Bad Orientation of Component Wrong Programmed Device Defective Components Analogue Digital BST
19 Overview fault failure localization Design Failures Manufacturing Failures: Analogue Nets Opens Bridges Stuck at 0 or 1 Wrong Analogue Components Missing Analogue Components Bad Orientation of Component (Complex) Digital Nets Opens Bridges Stuck at 0 or 1 Wrong Digital Components Missing Digital Components Bad Orientation of Component Wrong Programmed Device Defective Components Analogue Digital F-Test BST AOI MDA/FP ICT Insufficient probe access
Combining methods to meet the challenge Volume Low Moderate High Complexity F-test F test Vision Low FP F-test F-test Moderate FP MDA ICT Vision High F-test F-test F-test Vision 20
Coverage traditional Test Methods 21 Use of SMD (BGAs) limited physical access Increasing device complexity (SoCs) Increasing complexity in FCT dev and more difficult diagn.
Feasible coverage via JTAG Boundary Scan register: Only Bscan register is used to access the pins / nets CoreCommander: Embedded resources (instruments) in chips accessed and used via JTAG interface 22
Combining to get the max With the combination, high coverage and good diagnostic resolution for all types of boards 23
What is IEEE 1149.1 Boundary-scan? 0 1 1 A chip-level standard, adopted by the IEEE in 1990 1 1 0 1 1 Z 0 4 (or 5) added pins form the Test Access Port (TAP) 0 0 00 1 10 0 0 Additional logic inside the IC: scan cells on I/Os, controller & registers 1 1 1 IC Core 0 0 0 Data from the boundary-scan source (on TDI) can be loaded into the device and read from the device pins on TDO 0 TDI 0 0 Bypass Z Z 1 TDO Intest instructions communicate internally Instruction Reg. Extest instructions communicate externally ID Register TMS TCK Controller 24 Every I/O on a compliant IC becomes a test point
Applications at board level Testing TAP2 TAP1 Digital I/O scan module Infrastructure Interconnections Clusters Memory A/D buses & control signals R R SD up PLD + FPGA TAP Connector 25 Programming CPLDs, FPGAs Flash memories (w/ AutoWrite) SD F Cluster Cluster Connector
Presence of the Bscan data register 26
Emulative Test & Programming CPU FPGA 27
CoreCommander Application: Example 1 Using ADC as an embedded instrument 3V3 TDI R49 10k uc with JTAG Debug H1 ADC Address Debug R44 10k GND TDO
Extest based Memory connection test
Core Commander application example 2 at speed testing of memory connections
Multidrop system level Board 1 Board 2 Board 3 Board n Bridge Bridge Bridge Bridge TDI TDO TMS TCK TRST Slot ID Slot ID Slot ID Slot ID Backplane requirements: JTAG control signals plus address lines to select board slot ID Each board requires minimum of one bridging device 31
Tools for HW Engineers o JTAGLive Buzz Free connection checker o JTAG Maps Free Altium Designer extension o ProVision Testability report 32
Tools for Test Engineers BSDL files Schematics ISP & Test programs BOM file Testability reports
Tools for Production engineers Production Engineers Sequencers Sequencers Test Programs Reports
At our stand 35
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