2003 International Test Conference DESIGN CONSIDERATIONS IN USING 1149.1 AS A BACKPLANE TEST BUS Pete Collins petec@jtag.co.uk JTAG TECHNOLOGIES BTW03
PURPOSE The purpose of this presentation is to discuss the importance of correctly identifying the system test requirements at the design concept stage so that the optimal system test access architecture is implemented. This is because:- Hierarchical IEEE Std. 1149.1 backplane test access has become increasingly accepted as a test strategy for testing boards/modules within a system environment. The emergence of a variety of 1149.1 system test access devices from a number of silicon vendors now provides designers with more choice. System level architectural requirements dictate what system test access devices should be used.
CONTENT Introduction System Level Routing Strategies Supporting s Architectural Decisions Embedded Vector Delivery BIST Sequencer Overview Board & System Level BIST Strategy Conclusions
INTRODUCTION Implementation of a system level test architecture can be utilised to provide a more flexible test and enhanced diagnostic capability by:- Providing a single-point access to multiple scan chains in support of design and test partitioning. Support a board-to-board interconnect test strategy that will allow edge connector pin level diagnosis. Accommodate system checkout of firmware objects prior to customer shipment and facilitate field level firmware upgrades. Provide a system level infrastructure to exercise embedded test structures implemented within s and FPGA s.
System Architecture (Star) Board 1 Board 2 Board 3 Board N TDI TDO TCK TRST TMS(1) TMS(2) TMS(3) TMS(N) Multiple TMS lines significantly increases backplane signalling
System Architecture (Ring) Board 1 Board 2 Board 3 Slot Empty Breaks TDO/TDI Chain Board N TDI TDO TCK TRST TMS Boundary Scan cannot be performed due to empty slot which breaks the boundary scan chain
System Architecture (Multi-drop) Board 1 Board 2 Board 3 Board N System Access device System Access device System Access device System Access device TDI TDO TCK TRST TMS Slot ID Slot ID Slot ID Slot ID Backplane access limited to the 5 JTAG control signals + 6 address lines for selecting the board slot ID Each board requires the minimum of a single System Interface device
Hierarchical Boundary-Scan System Access A system level device contains one primary TAP and one or more secondary TAP s. The local board boundary-scan chains are connected to the secondary TAP s. The boundary-scan controller is connected to the primary TAP. By applying the appropriate system level device protocol, the primary TAP of the device can access the chains on the secondary TAP s Boundary-scan Controller Primary (Global) TAP1 System Access Secondary (Local) TAP1 TAP2 TAP3
System Level Configuration External Controller Printed Circuit Board 1 Scan Chain 3 Scan Chain 2 Scan Chain 3 Printed Circuit Scan Board Chain 1 3 Scan Chain Scan Chain 3 2 Scan Scan Chain Chain 2 1 Scan Chain 3 Scan Chain 1 Scan Chain 2 Scan Chain 1 Printed Circuit Board 2 Printed Circuit Board n Flash Flash External JTAG Controller External Scan Control Flash Flash TDI 1 TMS 1 TCLK 1 TDO 1 Auto-Write 1 TDI 1 TMS 1 TCLK 1 TDO 1 External Scan Control Auto-Write 1 TDI 1 TMS 1 TCLK 1 TDO 1 Auto-Write 1 Board ID Register TCLK 1 Auto-Write 1 Auto-Write Slot ID Board ID Register Auto-Write Slot ID External Scan Control External Scan Control TDI 1 TMS 1 TDO 1 Board ID Register Auto-Write Slot ID Board ID Register Auto-Write Slot ID Board ID Tracking Board ID Tracking Board ID Tracking Board ID Tracking TDI, TDO, TMS TRST, TCLK & AW Slot ID Standard Backplane I/O
System Level Configuration Embedded Controller Scan Chain 3 Scan Chain 2 Scan Chain 3 Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 1 Scan Chain 2 Scan Chain 3 Scan Chain 1 Scan Chain 2 Printed Circuit Board 1 Printed Circuit Board 2 Printed Circuit Board 3 System Controller Card Scan Chain 1 Flash Flash Flash FPGA External Scan Control TDI 1 External Scan Control TDI 1 TMS 1 TCLK 1 TDO 1 Auto-Write 1 TDI 1 TMS 1 TCLK 1 TDO 1 External Scan Control Auto-Write 1 TDI 1 TMS 1 TCLK 1 TDO 1 Auto-Write 1 Board ID Register TDO 1 Auto-Write Slot ID Auto-Write 1 Board ID Register & Auto-Write Slot ID Board ID Register Auto-Write Slot ID Board ID Register Auto-Write Slot ID External Scan Control Up Flash Scan Controller Board ID Tracking Board ID Tracking Board ID Tracking Board ID Tracking TDI, TDO, TMS TRST, TCLK & AW Slot ID Standard Backplane I/O
Types of System Level s Chipset Solution Providers JTS03 (IP Core or as device) JTS06 (IP Core or as device) Name Gateway Gateway Semi-house Firecron Ltd Firecron Ltd SCANSTA111 National Semiconductor SCANSTA112 National Semiconductor LSC BSCAN-1 LSC BSCAN-2 SN54/74LVT8996 SN54/74ACT8997 Multiple Scan Port Scan Path Linker Addressable Scan Port Scan-Path Linker Lattice Semiconductor Lattice Semiconductor Texas Instruments Texas Instruments SN54/74ACT8986 Linking Addressable Scan Port Texas Instruments Chipset Features How many local scan ports are supported? Does the system test access device support Multidrop access? Does the system test access device support parking of local scan chains? Is there provision to access proprietary test signals? Does the system test access device have a generic pass through capability? Does the system test access device have the capability to read back the board ID and Revision?
Multidrop Test Configuration Boundary-scan Controller Primary Tester TAP1 MULTIDROP 1 Board 1 (STA111) 1 2 3 4 LSC1 LSC2 No Chain Board 2 MULTIDROP 2 Gateway (JTS03) LSC3 LSC1 LSC2 Gateway (JTS03) LSC3 LSC4 No Chain
Proprietary Test Signal Pass-through Dependant upon specific board designs it may be necessary to route proprietary test signals from the edge connector to devices within the target local scan chain i.e. passing-through a WE Strobe pulse to optimise flash programming. This can be a generic pass-through capability i.e. input-to-output or dependant on local scan chain selection. This is important when the local distribution of the proprietary signal is to multiple chains and devices. Primary Scan Port Gateway/Bridge WE LSC 1 JTAG Bus LSC 1 WE LSC 2 N/C WE MPC8260 Processor Address Data Control WE Flash Memory WE Strobe JTAG Bus LSC 2 WE LSC 3 N/C DSP JTAG Bus LSC 3
Transparent Mode Vendor specific proprietary programming/emulation tools do not support the protocols necessary to communicate with system access devices. LSC 1 P/Thr Sel(0) 1 P/Thr Sel(1) 0 P/Thr Enable 0 Generic pass-through capability necessary to make the connection between primary JTAG port and LSP transparent by dedicated control pins or specific instruction. LSC 2 LSC 3 HIGHZ 0 1 X 0 1 1 X 0 0 0 1 0 Gateway/Bridge TRANSPARENTn Pass/Thru on LSP 1 FPGA s Primary Pass/thru Enable Pass/thru Sel 0 0 0 1 Pass/Thru on LSP 2 Pass/thru Sel 1 Pass/Thru on LSP 3 DSP s
How do I Read the Board ID and Revision? Gateway devices have an internal 16-bit Register which can be hard-coded by tying device pins to Vcc or GND dependant upon user-defined ID code. This register can be accessed once the Gateway is selected. Alternative devices do not have this utility, subsequently a set LSC on each card within the system will need to dedicate this LSC and 1149.1 compliant device to hard-wire the board ID code and revision i.e. or Scan buffer. The limitations in this alternative method is that board designs are subject to change due to obsolescence etc. that may change the boundary-scan infrastructure. Gateway/Bridge JTAG Bus LSC 1 Primary Scan Port BOARD_ID Register Hard-wire unused I/O pins To VCC or GND to provide User-definable ID code 16-bit User-definable Register hard-wired to Vcc or GND Depending upon ID code
Mother/Daughter Card Interconnect Testing Scan Bridge CONnection File Scan Bridge CONnection File TESTER_CHANNEL TAP1 TESTER_CHANNEL TAP1 MULTIDROP1 (JTS03,1,0,TAP1,CASCADE1, TAP3) MULTIDROP1 (JTS03,1,0,TAP1,CASCADE1, TAP3) CASCADE1 (STA111,0,TAP4,TAP5, TAP6) CASCADE1 (STA111,0,TAP4,TAP5, TAP6) END_CHANNEL END_CHANNEL Local Scan Port 1 Local Scan Port 1 Local Scan Port 2 Non-Scan Logic Local Scan Port 2 JTAG Bridge/Gateway JTAG Bridge/Gateway Plug On Daughter Card Local Scan Chain 3 Local Port Chain 3 Daughter Brd I/O & Slot ID Primary Board I/O Primary Primary to to Daughter Daughter board board connection connection tested tested using using Boundary-Scan Boundary-Scan
Hierarchical Interconnect Test Configuration (Parking of Local Scan Chains) Local Scan Port 1 Local Scan Port 2 Local Scan Port 1 Local Scan Port 2 Non-Scan Logic Non-Scan Logic JTAG Bridge/Gateway Local Scan Chain 3 JTAG Bridge/Gateway Local Scan Port3 Slot ID 0 Slot ID 1 Back-Plane Signals WE Strobe Back-Plane JTAG Signals TDI, TDO, TCK TMS & TRST
Local Scan Port (LSP) Termination Strategy Correct LSP termination is important to prevent erroneous sequencing of target scan chain devices. Correct TRST termination is important so that target devices are not asynchronously reset once control of the system access device is relinquished i.e. if devices are held in RTI whilst BIST is running the background. LSC buffering necessary if LSP s cannot provide sufficient drive i.e. when IP core function is implemented within. Vcc BRIDGE/ GATEWAY 10K 10K 10K TDO 0 TMS 0 TRST 0 WE 0 TDI 0 TCK 0 BUFFER TDI TMS TRST WE TDO TCK 22 68 1K 100 pf
Embedded Vector Delivery Passive Backplane Local Test Bus Master Slave Card A Slave Card B Slave Card C 3G 3G FPGA up up up MSC001 STA101 Scan Controller Scan Controller STA111 BIST EEPROM FPGA LSP3 LVDS MSC001 STA101 Scan Controller Scan Controller STA111 BIST EEPROM FPGA LSP3 LVDS MSC001 STA101 Scan Controller Scan Controller STA111 BIST EEPROM FPGA LSP3 LVDS Slot ID 0 Back-Plane Signals Slot ID 1 Slot ID 2 Back-Plane JTAG Signals TDI, TDO, TCK, TMS,TRST & WE Strobe
Embedded Vector Delivery Passive Backplane System Test Bus Master System Master Card Slave Card A Slave Card B FPGA FPGA up FPGA up FPGA up MSC001 STA101 Scan Controller Scan Controller STA111 EEPROM LSP 3 PCI Bridge JTS03 Gateway FPGA LSP3 LVDS STA111 FPGA LSP3 LVDS Slot ID 0 Slot ID 1 Back-Plane Signals Slot ID 2 Back-Plane JTAG Signals TDI, TDO, TCK, TMS,TRST & WE Strobe
Embedded Vector Delivery Active Backplane - System Test Bus Master Slave Card A Slave Card B up up FPGA FPGA JTS03 Gateway FPGA LSP3 LVDS STA111 FPGA LSP3 LVDS Active Back-Plane Slot ID 1 Slot ID 2 EEPROM up STA101 Scan Controller Back-Plane JTAG Signals TDI, TDO, TCK, TMS,TRST
Embedded Vector Delivery Passive Backplane BIST Sequencer System Master Card Slave Card A Slave Card B FPGA FPGA 3G up FPGA up up STA101 MSC001 Scan Controller Scan Controller STA111 EEPROM LSP 3 PCI Bridge JTS02 BIST Sequencer JTS03 Gateway BIST EEPROM FPGA LSP3 LVDS STA111 FPGA LSP3 LVDS Slot ID 0 Slot ID 1 Back-Plane Signals Slot ID 2 Back-Plane JTAG Signals TDI, TDO, TCK, TMS,TRST & WE Strobe
BIST Sequencer Overview The BIST Sequencer (JTS02) provides : The BIST Sequencer allows locally stored test vectors to be executed via the Bridge The resultant test signatures are compressed in the BIST Sequencer and compared against the expected signature Test result signatures are LSP 1, 2 & 3 stored within local flash for access via the SPI/I 2 C interface Board ID BIST Sequences can be initiated by:- Power ON Reset Front Panel Reset Run BIST command Gateway JTS03 BIST Data BIST Status & Control BIST Set-up/Control Logic CPU BIST Run Signal SPI Interface BIST Sequencer JTS02 BIST Flash Memory Data Primary Scan Port, A/W Pass thru & Slot address Power On & Push Button Resets
Board & Level BIST Strategy Memory BIST-Xt Test Memory CPU LSC 1 At Speed JTAG Interconnect Standard JTAG Interconnect with ICBIST, with MemBIST-Xt ICBIST & & JTAG XLI LSC 1 JTAG XLI LSC 1 Memory FPGA with ICBIST LSC 2 & 3 LSC 1 BIST Flash LSC 1 Combination JTAG Bridge/G-way & BIST Sequencer LSC 1 with ICBIST & JTAG XLI LSC 1 Interface Logic LSC 1 FPGA & Slot ID Primary Board I/O
CONCLUSION It is important that board & system designers are aware of the benefits and effectiveness of extending a 1149.1 test architecture for system level test and diagnosis. The architectural features discussed have been readily adopted by leading silicon vendors so that system architects have more choice and flexibility for implementing a system test architecture. Leading 1149.1 tools vendors provide ATPG support. There is now a definite affinity with the Multidrop solutions provided the Gateway, and Addressable Scan Port devices. There are limitations with robustness and fault tolerance of the 1149.1 solutions, some of which were addressed by the 1149.5 MTM-Bus Standard.