Test Data Compaction Tool from SynTest TM VirtualScan TM An Application Story January 29, 2004 Hiroshi Furukawa SoC No. 3 Group, SoC Development Division 1
Agenda Current Problems What is VirtualScan? Trial Results for Real Designs Achieved two tape outs for more than 4MGate Actual Application Results of Real Designs 2
Current Problems Test Cost Increase caused by LSI circuit size expansion Test Cycle Test time increasing along with LSI circuit size Test Pattern Pattern load overhead caused by larger test than pattern memory of ATE Test Coverage Co-mingling Ratio (ratio of defective devices with good devices) Omitting test patterns just for test cost reduction, results in sacrificing the comingling ratio Moreover Transition delay patterns for delay fault detection in addition to patterns for stuck-at faults No solution, but to keep unending purchase to fit for LSI increase 3
Position of DFT Tools Comparison of methodology Test cost Test Cycle Volume Test Pattern Volume N N L L W N : number of patterns L : scan chain length W : number of scan chains Scan Chain 1:1 (external:internal) TetraMAX,TurboScan Pattern data compaction with reducing N Scan ATPG Scan Chain 1:n Middle in between : scan ATPG and logic BIST Also middle for test cycle and test patterns, and for ease of implementation VirtualScan TestKompress XDBIST Pattern data compaction with shortening L Test compaction, test compression Scan Chain 1:n icbist,turbobist-logic,socbist No external scan patterns because of internal pattern generator Logic BIST Area, P&R, ECO, Design TAT Difficulty of Implementation 4
What is most important in test compaction? Why LBIST can t be so popular? - Difficult to implement - Definitely LBIST is superior just for compression ratio What is necessary for test compaction - Ease of Implementation - Above that, to get desired compaction ratio 5
What is VirtualScan TM? Feature: Scan chain split (L reduction) and ATPG (Ex) 1/5 Test cost reduction ATE Test Pattern W External Scan Input W Test cycle N L L Broadcaster (Pattern Supplier) Compactor (Result ( ) Compactor) L N 1/5L Pattern Volume N L W External Scan Output N 1/5 L W 6
Merits of VirtualScan TM Additional logic is only gate circuit (XOR) No need to modify clock, the most important factor in sequential circuits No need to think about clock, fmax/hold of added circuit, and inter clock External scan input Broadcaster (Pattern supplier) Composed of only XOR gates Compactor (Result compactor) External scan output Composed of only XOR gates No need to modify functional logic. Only need to modify scan chains Moreover, additional logic is only XOR between PI~REG and REG~OUT No additional pin Only 1 additional pin just for Top-up ATPG (Mode change for normal or VS) 7
Trial Results for Real Design A Design Overview Result Circuit Size - Logic part 1.2M Gates Hierarchical netlist Number of clocks Number of scan chains 31 28 7 clock groups Number of Scan FFs Max. scan chain length 102,647 3,666 14 times compaction with 20 split 7 times compaction with 10 split 20 Split 10 Split VirtualScan VirtualScan TurboScan Test Quality Test Coverage 92.03% 92.14% 92.14% Test Cost Number of patterns 3,128 3,065 2,207 Pattern increasing ratio 1.4 1.4 1 Pattern volume Pattern volume (in millions) 16.12 31.50 225.42 Compaction ratio (times x) 0.07 (14X) 0.14 (7X) 1 Test cost - Test cycle Number of test cycles 575,552 1,124,855 8,090,862 Compaction ratio (times x) 0.07 (14X) 0.14 (7X) 1 TAT - Circuit generation (h) 3 3 0 Design impact TAT - Pattern generation (h) 28 12 15 Increase in number of gates 4,879 2,354 0 Area OH 0.4% 0.2% 0 On SUN Blade2000/2900, 900MHz 8
Trial Results for Real Design B Design Overview Circuit Size - Logic part 4.2 M Gate Flat netlist Number of clocks 36 9 clock groups Number of scan chains 30 Number of Scan FFs 203, 578 Max. scan chain length 7,005 Results Test Coverage Number of patterns Pattern volume (in millions) Compaction ratio (times x) Number of test cycles Compaction ratio (times x) TAT - Circuit generation (h) TAT - Pattern generation (h) Increase in number of gates 14 times compaction with 2 split VirtualScan Existing ATPG Test Quality 92.61% 92.68% 2,546 19,094 Test Cost - Pattern volume 312.85 4379.71 0.07 1 Test cost - Test cycle 9,529,678 133,829,846 Design impact 0.07 (14X) 3 1 0 182 89 344 0 Area OH 0.01% 0 On SUN Blade2000/2900, 900MHz 9
Trial Results for Real Design C Design Overview Circuit Size - Logic part Number of clocks Number of scan chains Number of Scan FFs Max. scan chain length 4.5M Gate 52 32 250,364 7,824 Hierarchical netlist 12 clock groups Result Test Quality Test Cost - Pattern volume Test cost- Test cycle Design impact Test Coverage Number of patterns Pattern volume (in millions) Compaction ratio (times X) Number of test cycles Compaction ratio (times X) TAT - Circuit generation (h) TAT - Pattern generation (h) Increase in number of gates Area OH 20 times compaction with 4 split VirtualScan Existing ATPG 97.15% 97.49% 4,472 21,041 293.08 5343.40 0.05 (20X) 1 8,809,840 164,708,948 0.05 (20X) 1 1 0 273 101 899 0 0.02% 0 On SUN Blade2000, 990MHz 10
MultiCapture Default feature through SynTest tools, which show a differentiation All clocks are to be activated in order in one capture It enables drastic pattern number compaction than other tools Shift Capture Shift Issue Scan Enable CLK1 CLK2 CLK3 Need more CPU and memory 11
Compaction Ratio Design B 14 times compaction with 2 split MultiCapture Existing ATPG 7 times Chain split 2 times TurboScan VirtualScan Design C 20 times compaction with 4 split MultiCapture Chain split 5 times 4 times Existing ATPG TurboScan VirtualScan 12
Design Flow with VirtualScan Netlist generation for VirtualScan is between test compilation & layout Test compilation (DFT compiler) VirtualScan design Scan chain & conventional Netlist Scan chain & segmented Netlist Layout Final Netlist VirtualScan ATPG Coverage? No Top-Up ATPG Yes Pattern Verification & ATE I/F Test patterns 13
VirtualScan Process Flow (1/2) VirtualScan Netlist generation spf Scanned Netlist Library stil2dft Compile (vlogin, expin) dft sdb Clock analysis (cg123) dft Chain recognition (scansyn) dft pso Preparation of netlist generation (vsconfig) serial.dft _ vscan.dft _ pso cmd Netlist generation (vslink) VirtualScan netlist 14
VirtualScan Process Flow (2/2) ATPG - ATE Interface Test pattern generation (asicgen) Test pattern (tp or btp format) Pattern conversion (btptcl) Pattern conversion (tpout) Test pattern (tp or btp format) Test bench Pattern conversion (tpout) Test pattern (WGL) Test bench 15
Summary Easy to implement Circuit added is just combinational, so no clock care needed Small area overhead Less than 1%, depending only on split number, and easy to estimate Short implementation TAT Only 1-3 hours even for 4M gate design Long TAT for ATPG, (but short TAT for top-up ATPG) 7-11 days for design with 4M gates & 10 clock group Slightly lower fault coverage (vs. scan ATPG) However, Top-Up ATPG enables to get same coverage as scan ATPG Predictable compaction ratio Scan ATPG-like, and almost proportional to split ratio Applicable to all LSI circuits from small one to big one 16
Action Items To run more chain splits (in progress) To split 10 to 20 to confirm higher compaction ratio To run with distributed ATPG environment (in progress) Shorten large ATPG TAT To apply transition delay ATPG to real design (in progress) To reject delay faults in real devices To run with transition delay fault with PLL circuit (Q1) To Enable At-speed test exceeding ATE clock frequency To confirm Integration with MAGMA Blast Fusion (Q1) To realize physical synthesis of RTL-to-GDS To integrate with logic BIST (Q2) TurboBIST-Logic and top-up ATPG by VirtualScan Many bugs were found initially because it was new, but has matured recently. 17
DFT Tools Segmentation Test compaction is enough for current LSI size Test cost 10MGate? Scan ATPG Test compaction Test compression Logic BIST Chip size Is LBIST only for board test? 18
Home page: http://www.nms.necel.com/ Contact: hiroshi.furukawa@nms.necel.com 19