FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design (Session - 4) Time: 90 min Marks: 58 For Teacher's Use Only Q 1 2 3 4 5 6 7 8 Total No. Marks Q No. 9 10 11 12 13 14 15 16 Marks Q No. 17 18 19 20 21 22 23 24 Marks Q No. 25 26 27 28 29 30 31 32 Marks Q No. 33 34 35 36 Marks
Question No: 1 ( Marks: 1 ) - Please choose one The ANSI/IEEE Standard 754 defines a Single-Precision Floating Point format for binary numbers. 8-bit 16-bit 32-bit 64-bit Question No: 2 ( Marks: 1 ) - Please choose one The decimal 17 in BCD will be represented as 11101 11011 10111 11110 Question No: 3 ( Marks: 1 ) - Please choose one The basic building block for a logical circuit is A Flip-Flop A Logical Gate An Adder None of given options Question No: 4 ( Marks: 1 ) - Please choose one The output of the expression F=A.B.C will be Logic when A=1, B=0, C=1. Undefined One Zero No Output as input is invalid. Question No: 5 ( Marks: 1 ) - Please choose one is invalid number of cells in a single group formed by the adjacent cells in K- map 2 8 12 16 Question No: 6 ( Marks: 1 ) - Please choose one
The PROM consists of a fixed non-programmable Gate array configured as a decoder. AND OR NOT XOR Question No: 7 ( Marks: 1 ) - Please choose one is one of the examples of synchronous inputs. J-K input EN input Preset input (PRE) Clear Input (CLR) Question No: 8 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 9 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 10 ( Marks: 1 ) - Please choose one occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options Question No: 11 ( Marks: 1 ) - Please choose one Consider an up/down counter that counts between 0 and 15, if external input(x) is 0 the counter counts upward (0000 to 1111) and if external input (X) is 1 the counter counts downward (1111 to 0000), now suppose that the present state is 1100 and X=1, the next state of the counter will be 0000
1101 1011 1111 Question No: 12 ( Marks: 1 ) - Please choose one In a state diagram, the transition from a current state to the next state is determined by Current state and the inputs Current state and outputs Previous state and inputs Previous state and outputs Question No: 13 ( Marks: 1 ) - Please choose one is used to minimize the possible no. of states of a circuit. State assignment State reduction Next state table State diagram Question No: 14 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 15 ( Marks: 1 ) - Please choose one The best state assignment tends to. Maximizes the number of state variables that don t change in a group of related states Minimizes the number of state variables that don t change in a group of related states Minimize the equivalent states None of given options Question No: 16 ( Marks: 1 ) - Please choose one The output of this circuit is always.
1 0 A Question No: 17 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. 1 2 4 8 Question No: 18 ( Marks: 1 ) - Please choose one 5-bit Johnson counter sequences through states 7 10 32 25 Question No: 19 ( Marks: 1 ) - Please choose one Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) 1100 0011 0000 1111 Question No: 20 ( Marks: 1 ) - Please choose one The address from which the data is read, is provided by Depends on circuitry None of given options RAM Microprocessor Question No: 21 ( Marks: 1 ) - Please choose one
FIFO is an acronym for First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 22 ( Marks: 1 ) - Please choose one LUT is acronym for Look Up Table Local User Terminal Least Upper Time Period None of given options Question No: 23 ( Marks: 1 ) - Please choose one The voltage gain of the Inverting Amplifier is given by the relation V out / V in = - R f / R i V out / R f = - V in / R i R f / V in = - R i / V out R f / V in = R i / V out Question No: 24 ( Marks: 1 ) - Please choose one of a D/A converter is determined by comparing the actual output of a D/A converter with the expected output. Resolution Accuracy Quantization Missing Code Question No: 25 ( Marks: 1 ) - Please choose one Above is the circuit diagram of.
Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 26 ( Marks: 1 ) - Please choose one The sequence of states that are implemented by a n-bit Johnson counter is n+2 (n plus 2) 2n (n multiplied by 2) 2 n (2 raise to power n) n 2 (n raise to power 2) Question No: 27 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch input output S R Q T +1 0 0 Q T 0 1 0 1 0 1 1 1 INVALID Question No: 28 ( Marks: 2 ) Two state assignments are given in the table below. Identify which state assignment is best and why? States State assignment 1 State assignment 2 A 00 00 B 01 01 C 11 10 D 10 11 Ans: State assignment 2 is best assignment it Minimizes the number of state variables that don t change in a group of related states. Question No: 29 ( Marks: 2 )
Write down at least two functions of a register. Ans: 1. Registers are operating as a coherent unit to hold and generate data. 2. registers functions also include configuration and start-up of certain features, especially during initialization, buffer storage e.g. video memory for graphics cards, input/output (I/O) of different kinds, Question No: 30 ( Marks: 2 ) Define quantization process. Ans: The process by which we can convert an analogue signal into digital signal (code) is known as quantization process. Question No: 31 ( Marks: 3 ) How can we calculate the frequency of an unknown signal? Ans: The frequency of a particular event is accomplished by counting the number of times that event occurs within a specific time interval, then dividing the count by the length of the time interval. Question No: 32 ( Marks: 3 ) Given the following statement used in PLD programming: Y PIN 23 ISTYPE com ; Explain what does this statement mean? Ans: The Y variable is a Combinational output available directly from the AND-OR gate array output. The active-low or active-high output of the Registered Mode can also be specified in the declaration statement Question No: 33 ( Marks: 3 ) Explain dynamic RAM in your own words. Ans: Dram use latch to store a single bit of information.the main drawback of it id the discharge of capacitor over a period of time.here four gates are used in making a singlelatch. In terms of transistors, 4 to 6 transistors are required to implement a single storage cell. In order to build memories with higher densities, a single transistor is used to store a binary value. A single transistor can not store a binary value however it is used
to charge and discharge a capacitor. The capacitor can not retain the charge, therefore it has to be periodically charged through a refresh cycle. Question No: 34 ( Marks: 5 ) You are given the Next-state table of a moor machine, using this information draw the state diagram of the machine. Present State Next State Q 2 Q 1 Q 0 Q 2 Q 1 Q 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 1 Question No: 35 ( Marks: 5 ) Explain Memory Select or Enable Signals Memory Select or Enable Signal: There are more than one memory chips to store program Information in daily use computers. read or write operation is carried out on a single addressable location instantaneously. The unique location is accessed in one of the several memory chips, so single memory chips is selected before a read or write operation can be carried out. All memory chips have a chip enable or chip select signal which has to be activated before the memory can be accessed. Question No: 36 ( Marks: 5 ) Performance characteristics of D/A converters are determined by five parameters. Name them. Ans: Performances characteristics of D/A converters are determined by five parameters are as follow: 1. Accuracy 2. Setting time
3. Monotonicity 4. Linearity 5. Resolution FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 4) Ref No: 1129612 Time: 120 min Marks: 75 For Teacher's Use Only Q 1 2 3 4 5 6 7 8 Total No. Marks Q No. 9 10 11 12 13 14 15 16 Marks Q No. 17 18 19 20 21 22 23 24 Marks Q No. 25 26 27 28 29 30 31 32 Marks Q No. 33 34 35 36 37 38 39 40 Marks Q No. 41 Marks
Question No: 1 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE Question No: 2 ( Marks: 1 ) - Please choose one The output of an XNOR gate is 1 when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only II and III only Question No: 3 ( Marks: 1 ) - Please choose one NAND gate is formed by connecting AND Gate and then NOT Gate NOT Gate and then AND Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be Zero One Undefined No output as input is invalid Question No: 5 ( Marks: 1 ) - Please choose one The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called Radiation-Erase programming method (REPM) In-System Programming (ISP) In-chip Programming (ICP) Electronically-Erase programming method(eepm) Question No: 6 ( Marks: 1 ) - Please choose one
The ABEL symbol for OR operation is! & # $ Question No: 7 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flipflop Doesn t have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one For a gated D-Latch if EN=1 and D=1 then Q(t+1) = 0 1 Q(t) Invalid Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False Question No: 11 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 12 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input
Clear Input (CLR) Question No: 13 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 14 ( Marks: 1 ) - Please choose one Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit. AND NAND NOR XNOR Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the combination of current state and inputs. Mealy machine Moore Machine State Reduction table State Assignment table Question No: 16 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel
Parallel data to serial Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high Remains in previous state State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one In the following statement Z PIN 20 ISTYPE reg.invert ; The keyword reg.invert indicates An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output Question No: 20 ( Marks: 1 ) - Please choose one A Nibble consists of bits 2 4 8 16 Question No: 21 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A
Question No: 22 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? 2 4 6 8 Question No: 23 ( Marks: 1 ) - Please choose one A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing. 1110 0111 1000 1001 Question No: 24 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory Flash Memory Fast Page Access Mode Memory Question No: 26 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options
Question No: 27 ( Marks: 1 ) - Please choose one The process of converting the analogue signal into a digital representation (code) is known as Strobing Amplification Quantization Digitization Question No: 28 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 29 ( Marks: 1 ) - Please choose one ( A + B)(A + B + C)(A + C) is an example of Product of sum form Sum of product form Demorgans law Associative law Question No: 30 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3
Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3 Question No: 31 ( Marks: 1 ) How the hour counter is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)? Question No: 32 ( Marks: 1 ) The top of the stack contains the value 5 and bottom of the stack contains the value 6, a pop (read data from stack) operation was executed, which value would be read? Question No: 33 ( Marks: 2 ) What kind of devices use the shift register based First In First Out (FIFO) memory? Ans: FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. Question No: 34 ( Marks: 2 ) Differentiate between positive-edge triggered flip-flop and negative edgetriggered flip-flop. Ans: A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.
The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge. Question No: 35 ( Marks: 3 ) Name some of the important operating characteristics of flip-flops Ans; The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit. Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur. Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered. Power Dissipation - is the total power consumption of the device. Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR inputs. Question No: 36 ( Marks: 3 ) What is memory expansion process? Computers ad digital system have the capability to to allow RAM memory to be extended as the needed arise by inserting extra memory in dedicated memory sockets on the computer motherboard.th e total amount of memory that is supported by any digital system depends upon the size of the address bus of micro processor or a micro controller. Question No: 37 ( Marks: 3 ) Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans:
A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. Question No: 38 ( Marks: 5 ) Explain Flash Analogue-to Digital Converter. Flash Analogue-to Digital Converter: A flash analogue to digital converter is the fastest type of converter we use. Like the successive approximation converter it works by comparing the input signal to a reference voltage, but a flash converter has as many comparators as there are steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256, comparators. The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output. Question No: 39 ( Marks: 5 ) Explain the next-state table with the help of a table for any sequential circuit. Ans State Table The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. Present state Next state x=0 Next state x=1 Out put x=0 Out put x=1 Q1Q2 00 11 01 0 0 01 11 00 0 0 10 10 11 0 1 11 10 10 0 1
Question No: 40 ( Marks: 10 ) Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of PRE and CLR inputs on flip-flops. Ans: The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear: When the preset input is activated, the flip-flop will be set (Q=1, not-q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once. Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them, to further denote the negative logic of these inputs: Question No: 41 ( Marks: 10 ) Explain the following in context of Memory: Address signals A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
Data signals Method of how information is transferred; usually it is transferred in binary code in signals or pulses. A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero. It is known that spurious variations in the mechanical or electrical parameters of a storage system cause unwanted displacement and shift of the signal being processed, thus necessitating frequency and phase compensation. To this end, synchronizing systems, servosystems, phase lock oscillator circuits, separation circuits and the like are employed. FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 4) Ref No: 1129612 Time: 120 min Marks: 75 For Teacher's Use Only Q 1 2 3 4 5 6 7 8 Total No. Marks Q No. 9 10 11 12 13 14 15 16 Marks Q No. 17 18 19 20 21 22 23 24 Marks Q No. 25 26 27 28 29 30 31 32 Marks
Q No. 33 34 35 36 37 38 39 40 Marks Q No. 41 Marks
Question No: 1 ( Marks: 1 ) - Please choose one NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE Question No: 2 ( Marks: 1 ) - Please choose one The output of an XNOR gate is 1 when I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one I Only IV Only I and IV only II and III only Question No: 3 ( Marks: 1 ) - Please choose one NAND gate is formed by connecting AND Gate and then NOT Gate NOT Gate and then AND Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be Zero One Undefined No output as input is invalid Question No: 5 ( Marks: 1 ) - Please choose one The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called Radiation-Erase programming method (REPM) In-System Programming (ISP) In-chip Programming (ICP) Electronically-Erase programming method(eepm) Question No: 6 ( Marks: 1 ) - Please choose one
The ABEL symbol for OR operation is! & # $ Question No: 7 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = for negative edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flipflop Doesn t have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one For a gated D-Latch if EN=1 and D=1 then Q(t+1) = 0 1 Q(t) Invalid Question No: 10 ( Marks: 1 ) - Please choose one In asynchronous digital systems all the circuits change their state with respect to a common clock True False Question No: 11 ( Marks: 1 ) - Please choose one A positive edge-triggered flip-flop changes its state when Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 12 ( Marks: 1 ) - Please choose one is one of the examples of asynchronous inputs. J-K input S-R input D input
Clear Input (CLR) Question No: 13 ( Marks: 1 ) - Please choose one The input overrides the input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE) Question No: 14 ( Marks: 1 ) - Please choose one Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit. AND NAND NOR XNOR Question No: 15 ( Marks: 1 ) - Please choose one In outputs depend only on the combination of current state and inputs. Mealy machine Moore Machine State Reduction table State Assignment table Question No: 16 ( Marks: 1 ) - Please choose one is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment Question No: 17 ( Marks: 1 ) - Please choose one A multiplexer with a register circuit converts Serial data to parallel
Parallel data to serial Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one In asynchronous transmission when the transmission line is idle, It is set to logic low It is set to logic high Remains in previous state State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one In the following statement Z PIN 20 ISTYPE reg.invert ; The keyword reg.invert indicates An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output Question No: 20 ( Marks: 1 ) - Please choose one A Nibble consists of bits 2 4 8 16 Question No: 21 ( Marks: 1 ) - Please choose one The output of this circuit is always. 1 0 A
Question No: 22 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? 2 4 6 8 Question No: 23 ( Marks: 1 ) - Please choose one A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing. 1110 0111 1000 1001 Question No: 24 ( Marks: 1 ) - Please choose one The high density FLASH memory cell is implemented using 1 floating-gate MOS transistor 2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 ) - Please choose one In order to synchronize two devices that consume and produce data at different rates, we can use Read Only Memory Fist In First Out Memory Flash Memory Fast Page Access Mode Memory Question No: 26 ( Marks: 1 ) - Please choose one If the FIFO Memory output is already filled with data then It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options
Question No: 27 ( Marks: 1 ) - Please choose one The process of converting the analogue signal into a digital representation (code) is known as Strobing Amplification Quantization Digitization Question No: 28 ( Marks: 1 ) - Please choose one Above is the circuit diagram of. Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 29 ( Marks: 1 ) - Please choose one ( A + B)(A + B + C)(A + C) is an example of Product of sum form Sum of product form Demorgans law Associative law Question No: 30 ( Marks: 1 ) - Please choose one Q2 :=Q1 OR X OR Q3 The above ABEL expression will be Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3
Q2:= Q1 & X & Q3 Q2:= Q1! X! Q3 Question No: 31 ( Marks: 1 ) How the hour counter is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)? Question No: 32 ( Marks: 1 ) The top of the stack contains the value 5 and bottom of the stack contains the value 6, a pop (read data from stack) operation was executed, which value would be read? Question No: 33 ( Marks: 2 ) What kind of devices use the shift register based First In First Out (FIFO) memory? Ans: FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of nontrivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. Question No: 34 ( Marks: 2 ) Differentiate between positive-edge triggered flip-flop and negative edgetriggered flip-flop. Ans: A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal.
The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge. Question No: 35 ( Marks: 3 ) Name some of the important operating characteristics of flip-flops Ans; The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit. Propagation Delay Time - is the interval of time required after an input signal has been applied for the resulting output change to occur. Set-Up Time - is the minimum interval required for the logic levels to be maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Hold Time - is the minimum interval required for the logic levels to remain on the inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop. Maximum Clock Frequency - is the highest rate that a flip-flop can be reliably triggered. Power Dissipation - is the total power consumption of the device. Pulse Widths - are the minimum pulse widths specified by the manufacturer for the Clock, SET and CLEAR inputs. Question No: 36 ( Marks: 3 ) What is memory expansion process? Computers ad digital system have the capability to to allow RAM memory to be extended as the needed arise by inserting extra memory in dedicated memory sockets on the computer motherboard.th e total amount of memory that is supported by any digital system depends upon the size of the address bus of micro processor or a micro controller. Question No: 37 ( Marks: 3 ) Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans:
A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. Question No: 38 ( Marks: 5 ) Explain Flash Analogue-to Digital Converter. Flash Analogue-to Digital Converter: A flash analogue to digital converter is the fastest type of converter we use. Like the successive approximation converter it works by comparing the input signal to a reference voltage, but a flash converter has as many comparators as there are steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256, comparators. The resistor net and comparators provide an input to the combinational logic circuit, so the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output. Question No: 39 ( Marks: 5 ) Explain the next-state table with the help of a table for any sequential circuit. Ans State Table The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. Present state Next state x=0 Next state x=1 Out put x=0 Out put x=1 Q1Q2 00 11 01 0 0 01 11 00 0 0 10 10 11 0 1 11 10 10 0 1
Question No: 40 ( Marks: 10 ) Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of PRE and CLR inputs on flip-flops. Ans: The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear: When the preset input is activated, the flip-flop will be set (Q=1, not-q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be reset (Q=0, not-q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once. Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them, to further denote the negative logic of these inputs: Question No: 41 ( Marks: 10 ) Explain the following in context of Memory: Address signals A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
Data signals Method of how information is transferred; usually it is transferred in binary code in signals or pulses. A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero. It is known that spurious variations in the mechanical or electrical parameters of a storage system cause unwanted displacement and shift of the signal being processed, thus necessitating frequency and phase compensation. To this end, synchronizing systems, servosystems, phase lock oscillator circuits, separation circuits and the like are employed. Question No: 1 ( Marks: 1 ) - Please choose one In the binary number 10011 the weight of the most significant digit is 2 4 (2 raise to power 4) 2 3 (2 raise to power 3) 2 0 (2 raise to power 0) 2 1 (2 raise to power 1) Question No: 2 ( Marks: 1 ) - Please choose one An S-R latch can be implemented by using gates AND, OR NAND, NOR NAND, XOR NOT, XOR Question No: 3 ( Marks: 1 ) - Please choose one A latch has stable states One Two Three
Four Question No: 4 ( Marks: 1 ) - Please choose one Sequential circuits have storage elements True False Question No: 5 ( Marks: 1 ) - Please choose one The ABEL symbol for XOR operation is $ #! & Question No: 6 ( Marks: 1 ) - Please choose one A Demultiplexer is not available commercially. True False Question No: 7 ( Marks: 1 ) - Please choose one Using multiplexer as parallel to serial converter requires connected to the multiplexer A parallel to serial converter circuit A counter circuit A BCD to Decimal decoder A 2-to-8 bit decoder Question No: 8 ( Marks: 1 ) - Please choose one The device shown here is most likely a Comparator Multiplexer
Demultiplexer Parity generator Question No: 9 ( Marks: 1 ) - Please choose one The main use of the Multiplexer is to Select data from multiple sources and to route it to a single Destination Select data from Single source and to route it to a multiple Destinations Select data from Single source and to route to single destination Select data from multiple sources and to route to multiple destinations Question No: 10 ( Marks: 1 ) - Please choose one A logic circuit with an output consists of. two AND gates, two OR gates, two inverters three AND gates, two OR gates, one inverter two AND gates, one OR gate, two inverters two AND gates, one OR gate Question No: 11 ( Marks: 1 ) - Please choose one The binary value of 1010 is converted to the product term True False Question No: 12 ( Marks: 1 ) - Please choose one The 3-variable Karnaugh Map (K-Map) has cells for min or max terms 4 8 12 16 Question No: 13 ( Marks: 1 ) - Please choose one Following is standard POS expression
True False Question No: 14 ( Marks: 1 ) - Please choose one The output of the expression F=A+B+C will be Logic when A=0, B=1, C=1. the symbol + here represents OR Gate. Undefined One Zero 10 (binary) Question No: 15 ( Marks: 1 ) - Please choose one The Extended ASCII Code (American Standard Code for Information Interchange) is a code 2-bit 7-bit 8-bit 16-bit Question No: 1 ( Marks: 1 ) - Please choose one The maximum number that can be represented using unsigned octal system is 1 7 9 16 Question No: 2 ( Marks: 1 ) - Please choose one If we add 723 and 134 by representing them in floating point notation i.e. by first, converting them in floating point representation and then adding them, the value of exponent of result will be 0 1 2 3 Question No: 3 ( Marks: 1 ) - Please choose one The diagram given below represents
Demorgans law Associative law Product of sum form Sum of product form Question No: 4 ( Marks: 1 ) - Please choose one The range of Excess-8 code is from to +7 to -8 +8 to -7 +9 to -8-9 to +8 Question No: 5 ( Marks: 1 ) - Please choose one A non-standard POS is converted into a standard POS by using the rule A A = 0 A+B = B+A Question No: 6 ( Marks: 1 ) - Please choose one The 3-variable Karnaugh Map (K-Map) has cells for min or max terms 4 8 12 16 Question No: 7 ( Marks: 1 ) - Please choose one The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels? A > B = 1, A < B = 0, A < B = 1 A > B = 0, A < B = 1, A = B = 0
A > B = 1, A < B = 0, A = B = 0 A > B = 0, A < B = 1, A = B = 1 Question No: 8 ( Marks: 1 ) - Please choose one A particular Full Adder has 3 inputs and 2 output 3 inputs and 3 output 2 inputs and 3 output 2 inputs and 2 output Question No: 9 ( Marks: 1 ) - Please choose one The function to be performed by the processor is selected by set of inputs known as Function Select Inputs MicroOperation selectors OPCODE Selectors None of given option Question No: 10 ( Marks: 1 ) - Please choose one For a 3-to-8 decoder how many 2-to-4 decoders will be required? 2 1 3 4 Question No: 11 ( Marks: 1 ) - Please choose one GAL is an acronym for. Giant Array Logic General Array Logic Generic Array Logic Generic Analysis Logic Question No: 12 ( Marks: 1 ) - Please choose one The Quad Multiplexer has outputs 4 8 12 16 Question No: 13 ( Marks: 1 ) - Please choose one
A.(B.C) = (A.B).C is an expression of Demorgan s Law Distributive Law Commutative Law Associative Law Question No: 14 ( Marks: 1 ) - Please choose one 2's complement of any binary number can be calculated by adding 1's complement twice adding 1 to 1's complement subtracting 1 from 1's complement. calculating 1's complement and inverting Most significant bit Question No: 15 ( Marks: 1 ) - Please choose one The binary value 1010110 is equivalent to decimal 86 87 88 89 Question No: 16 ( Marks: 1 ) - Please choose one Tri-State Buffer is basically a/an gate. According to Demorgan s theorem: A.B.C Question No: 2 ( Marks: 1 ) - Please choose one The Extended ASCII Code (American Standard Code for Information Interchange) is a code 2-bit 7-bit 8-bit 16-bit Question No: 3 ( Marks: 1 ) - Please choose one
The AND Gate performs a logical function Addition Subtraction Multiplication Division Question No: 4 ( Marks: 1 ) - Please choose one NOR gate is formed by connecting OR Gate and then NOT Gate NOT Gate and then OR Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 5 ( Marks: 1 ) - Please choose one Generally, the Power dissipation of devices remains constant throughout their operation. TTL CMOS 3.5 series CMOS 5 Series Power dissipation of all circuits increases with time. Question No: 6 ( Marks: 1 ) - Please choose one Two 2-bit comparator circuits can be connected to form single 4-bit comparator True False Question No: 7 ( Marks: 1 ) - Please choose one When the control line in tri-state buffer is high the buffer operates like a gate AND OR NOT XOR Question No: 8 ( Marks: 1 ) - Please choose one The GAL22V10 has inputs 22 10
44 20 Question No: 9 ( Marks: 1 ) - Please choose one The ABEL symbol for OR operation is! & # $ Question No: 10 ( Marks: 1 ) - Please choose one The OLMC of the GAL16V8 is to the OLMC of the GAL22V10 Similar Different Similar with some enhancements Depends on the type of PALs input size Question No: 11 ( Marks: 1 ) - Please choose one All the ABEL equations must end with. (a dot) $ (a dollar symbol) ; (a semicolon) endl (keyword endl ) Question No: 12 ( Marks: 1 ) - Please choose one The Quad Multiplexer has outputs 4 8 12 16 Question No: 13 ( Marks: 1 ) - Please choose one "Sum-of-Weights" method is used to convert from one number system to other to encode data to decode data to convert from serial to parralel data Question No: 14 ( Marks: 1 ) - Please choose one Circuits having a bubble at their outputs are considered to have an active-low output.
True False Question No: 15 ( Marks: 1 ) - Please choose one ( A + B)(A + B + C)(A + C) is an example of Product of sum form Sum of product form Demorgans law Associative law AND OR NOT XOR Question No: 17 ( Marks: 2 ) For what values of A, B, C and D, value of the expression given below will be logic 1. Explain at least one combination. A. B + A. B. CD. Ans: Question No: 18 ( Marks: 2 ) provide some of the inputs for which the adjacent 1s detector circuit have active high output? Ans: The Adjacent 1s Detector accepts 4-bit inputs. If two adjacent 1s are detected in the input, the output is set to high. input combinations will be 1. 0011, 2. 0110, 3. 0111, 4. 1011, 5. 1100,
6. 1101, 7. 1110 and 8. 1111 the output function is a 1. Question No: 19 ( Marks: 2 ) Draw the Truth-Table of NOR based S-R Latch Question No: 20 ( Marks: 3 ) For a two bit comparator circuit specify the inputs for which A > B Ans: 1. 01 00, 2. 10 00, 3. 10 01, 4. 11 00, 5. 11 01 and 6. 11 10 Question No: 16 ( Marks: 1 ) - Please choose one The diagram given below represents
Demorgans law Associative law Product of sum form Sum of product form How can a PLD be programmed? PLDs are programmed with the help of computer which runs the programming software. The computer is connected to a programmer socket in which the PLD is inserted for programming. PLDs can also be programmed when they are installed on a circuit board Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder? The circuit of the 1-to-4 Demultiplexer is similar to the 2-to-4 Binary Decoder described earlier figure 16.9. The only difference between the two is the addition of the Data Input line, which is used as enable line in the 2-to-4 Decoder circuit figure Name the three declarations that are included in declaration section of the module that is created when an Input (source) file is created in ABEL. Device declaration, pin declarations and set declarations. Explain with example how noise affects Operation of a CMOS AND Gate circuit. Two CMOS 5 volt series AND gates are connected together. Figure 7.3 The first AND gate has both its inputs connected to logic high, therefore the output of the gate is guaranteed to be logic high. The logic high voltage output of the first AND gate is assumed to be 4.6 volts well within the valid VOH range of 5-4.4 volts. Assume the same noise signal (as described earlier) is added to the output signal of the first AND gate. explain the SOP based implementation of the Adjacent 1s Detector Circuit The Adjacent 1s Detector accepts 4-bit inputs. If two adjacent 1s are detected in the input, the output is set to high. The operation of the Adjacent 1s Detector is represented by the function table. Table 13.6. In the function table, for the input combinations 0011, 0110, 0111, 1011, 1100, 1101, 1110 and 1111 the output function is a 1.
Implementing the circuit directly from the function table based on the SOP form requires 8 AND gates for the 8 product terms (minterms) with an 8-input OR gate. Figure 13.3. The total gate count is One 8 input OR gate Eight 4 input AND gates Ten NOT gates The expression can be simplified using a Karnaugh map, figure 13.4, and then the simplified expression can be implemented to reduce the gate count. The simplified expression isab + CD +BC. The circuit implemented using the expression AB + CD +BC has reduced to 3 input OR gate and 2 input AND gates. The simplified Adjacent 1s Detector circuit uses only four gates reducing the cost, the size of the circuit and the power requirement. The propagation delay of the circuit is of the order of two gates FINALTERM EXAMINATION Spring 2010 CS302- Digital Logic Design Time: 90 min Marks: 58 Question No: 1 ( Marks: 1 ) - Please choose one A 8-bit serial in / parallel out shift register contains the value 8, clock signal(s) will be required to shift the value completely out of the register. 1 2 4 8 Question No: 2 ( Marks: 1 ) - Please choose one A frequency counter Counts pulse width Counts no. of clock pulses in 1 second Counts high and low range of given clock pulse None of given options Question No: 3 ( Marks: 1 ) - Please choose one In a sequential circuit the next state is determined by and State variable, current state Current state, flip-flop output Current state and external input Input and clock signal applied Question No: 4 ( Marks: 1 ) - Please choose one The divide-by-60 counter in digital clock is implemented by using two cascading counters: